From a055b530c37ce4c14be1a391e968f6b0fb749a09 Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Tue, 29 Jun 2010 16:32:42 +0900 Subject: [PATCH] --- yaml --- r: 207176 b: refs/heads/master c: 4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/tile/include/asm/cache.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 948d2b08cad8..bc63d4c1c5e5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0707ad30d10110aebc01a5a64fb63f4b32d20b73 +refs/heads/master: 4b2bf4b3fc066d45870b7f33fa23dbcb9cb1a27f diff --git a/trunk/arch/tile/include/asm/cache.h b/trunk/arch/tile/include/asm/cache.h index c2b7dcfe5327..ee597147e5cd 100644 --- a/trunk/arch/tile/include/asm/cache.h +++ b/trunk/arch/tile/include/asm/cache.h @@ -20,7 +20,6 @@ /* bytes per L1 data cache line */ #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES) /* bytes per L1 instruction cache line */ #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()