diff --git a/[refs] b/[refs]
index b9580596d9f6..23bf7bcfe42e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
---
-refs/heads/master: b12f3cbd7a9a869eae1eb108da02526b132ba80b
+refs/heads/master: 9bbb851c7079ff670ba3fe6c7ce93bb5daa9a694
diff --git a/trunk/Documentation/DocBook/libata.tmpl b/trunk/Documentation/DocBook/libata.tmpl
index ff3e5bec1c24..ba9975771503 100644
--- a/trunk/Documentation/DocBook/libata.tmpl
+++ b/trunk/Documentation/DocBook/libata.tmpl
@@ -107,6 +107,10 @@ void (*dev_config) (struct ata_port *, struct ata_device *);
issue of SET FEATURES - XFER MODE, and prior to operation.
+ Called by ata_device_add() after ata_dev_identify() determines
+ a device is present.
+
+
This entry may be specified as NULL in ata_port_operations.
@@ -150,8 +154,8 @@ unsigned int (*mode_filter) (struct ata_port *, struct ata_device *, unsigned in
Taskfile read/write
-void (*sff_tf_load) (struct ata_port *ap, struct ata_taskfile *tf);
-void (*sff_tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
+void (*tf_load) (struct ata_port *ap, struct ata_taskfile *tf);
+void (*tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
@@ -160,35 +164,36 @@ void (*sff_tf_read) (struct ata_port *ap, struct ata_taskfile *tf);
hardware registers / DMA buffers, to obtain the current set of
taskfile register values.
Most drivers for taskfile-based hardware (PIO or MMIO) use
- ata_sff_tf_load() and ata_sff_tf_read() for these hooks.
+ ata_tf_load() and ata_tf_read() for these hooks.
PIO data read/write
-void (*sff_data_xfer) (struct ata_device *, unsigned char *, unsigned int, int);
+void (*data_xfer) (struct ata_device *, unsigned char *, unsigned int, int);
All bmdma-style drivers must implement this hook. This is the low-level
operation that actually copies the data bytes during a PIO data
transfer.
-Typically the driver will choose one of ata_sff_data_xfer_noirq(),
-ata_sff_data_xfer(), or ata_sff_data_xfer32().
+Typically the driver
+will choose one of ata_pio_data_xfer_noirq(), ata_pio_data_xfer(), or
+ata_mmio_data_xfer().
ATA command execute
-void (*sff_exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
+void (*exec_command)(struct ata_port *ap, struct ata_taskfile *tf);
causes an ATA command, previously loaded with
->tf_load(), to be initiated in hardware.
- Most drivers for taskfile-based hardware use ata_sff_exec_command()
+ Most drivers for taskfile-based hardware use ata_exec_command()
for this hook.
@@ -213,8 +218,8 @@ command.
Read specific ATA shadow registers
-u8 (*sff_check_status)(struct ata_port *ap);
-u8 (*sff_check_altstatus)(struct ata_port *ap);
+u8 (*check_status)(struct ata_port *ap);
+u8 (*check_altstatus)(struct ata_port *ap);
@@ -222,14 +227,20 @@ u8 (*sff_check_altstatus)(struct ata_port *ap);
hardware. On some hardware, reading the Status register has
the side effect of clearing the interrupt condition.
Most drivers for taskfile-based hardware use
- ata_sff_check_status() for this hook.
+ ata_check_status() for this hook.
+
+
+ Note that because this is called from ata_device_add(), at
+ least a dummy function that clears device interrupts must be
+ provided for all drivers, even if the controller doesn't
+ actually have a taskfile status register.
Select ATA device on bus
-void (*sff_dev_select)(struct ata_port *ap, unsigned int device);
+void (*dev_select)(struct ata_port *ap, unsigned int device);
@@ -240,7 +251,9 @@ void (*sff_dev_select)(struct ata_port *ap, unsigned int device);
Most drivers for taskfile-based hardware use
- ata_sff_dev_select() for this hook.
+ ata_std_dev_select() for this hook. Controllers which do not
+ support second drives on a port (such as SATA contollers) will
+ use ata_noop_dev_select().
@@ -428,13 +441,13 @@ void (*irq_clear) (struct ata_port *);
to struct ata_host_set.
- Most legacy IDE drivers use ata_sff_interrupt() for the
+ Most legacy IDE drivers use ata_interrupt() for the
irq_handler hook, which scans all ports in the host_set,
determines which queued command was active (if any), and calls
- ata_sff_host_intr(ap,qc).
+ ata_host_intr(ap,qc).
- Most legacy IDE drivers use ata_sff_irq_clear() for the
+ Most legacy IDE drivers use ata_bmdma_irq_clear() for the
irq_clear() hook, which simply clears the interrupt and error
flags in the DMA status register.
@@ -483,6 +496,10 @@ void (*host_stop) (struct ata_host_set *host_set);
data from port at this time.
+ Many drivers use ata_port_stop() as this hook, which frees the
+ PRD table.
+
+
->host_stop() is called after all ->port_stop() calls
have completed. The hook must finalize hardware shutdown, release DMA
and other resources, etc.
diff --git a/trunk/Documentation/feature-removal-schedule.txt b/trunk/Documentation/feature-removal-schedule.txt
index a5e381185de9..ed511af0f79a 100644
--- a/trunk/Documentation/feature-removal-schedule.txt
+++ b/trunk/Documentation/feature-removal-schedule.txt
@@ -520,6 +520,29 @@ Who: Hans de Goede
----------------------------
+What: corgikbd, spitzkbd, tosakbd driver
+When: 2.6.35
+Files: drivers/input/keyboard/{corgi,spitz,tosa}kbd.c
+Why: We now have a generic GPIO based matrix keyboard driver that
+ are fully capable of handling all the keys on these devices.
+ The original drivers manipulate the GPIO registers directly
+ and so are difficult to maintain.
+Who: Eric Miao
+
+----------------------------
+
+What: corgi_ssp and corgi_ts driver
+When: 2.6.35
+Files: arch/arm/mach-pxa/corgi_ssp.c, drivers/input/touchscreen/corgi_ts.c
+Why: The corgi touchscreen is now deprecated in favour of the generic
+ ads7846.c driver. The noise reduction technique used in corgi_ts.c,
+ that's to wait till vsync before ADC sampling, is also integrated into
+ ads7846 driver now. Provided that the original driver is not generic
+ and is difficult to maintain, it will be removed later.
+Who: Eric Miao
+
+----------------------------
+
What: capifs
When: February 2011
Files: drivers/isdn/capi/capifs.*
@@ -566,26 +589,3 @@ Why: Useful in 2003, implementation is a hack.
Generally invoked by accident today.
Seen as doing more harm than good.
Who: Len Brown
-
-----------------------------
-
-What: video4linux /dev/vtx teletext API support
-When: 2.6.35
-Files: drivers/media/video/saa5246a.c drivers/media/video/saa5249.c
- include/linux/videotext.h
-Why: The vtx device nodes have been superseded by vbi device nodes
- for many years. No applications exist that use the vtx support.
- Of the two i2c drivers that actually support this API the saa5249
- has been impossible to use for a year now and no known hardware
- that supports this device exists. The saa5246a is theoretically
- supported by the old mxb boards, but it never actually worked.
-
- In summary: there is no hardware that can use this API and there
- are no applications actually implementing this API.
-
- The vtx support still reserves minors 192-223 and we would really
- like to reuse those for upcoming new functionality. In the unlikely
- event that new hardware appears that wants to use the functionality
- provided by the vtx API, then that functionality should be build
- around the sliced VBI API instead.
-Who: Hans Verkuil
diff --git a/trunk/Documentation/input/elantech.txt b/trunk/Documentation/input/elantech.txt
index 56941ae1f5db..a10c3b6ba7c4 100644
--- a/trunk/Documentation/input/elantech.txt
+++ b/trunk/Documentation/input/elantech.txt
@@ -333,14 +333,14 @@ byte 0:
byte 1:
bit 7 6 5 4 3 2 1 0
- . . . . . x10 x9 x8
+ x15 x14 x13 x12 x11 x10 x9 x8
byte 2:
bit 7 6 5 4 3 2 1 0
x7 x6 x5 x4 x4 x2 x1 x0
- x10..x0 = absolute x value (horizontal)
+ x15..x0 = absolute x value (horizontal)
byte 3:
@@ -350,14 +350,14 @@ byte 3:
byte 4:
bit 7 6 5 4 3 2 1 0
- . . . . . . y9 y8
+ y15 y14 y13 y12 y11 y10 y8 y8
byte 5:
bit 7 6 5 4 3 2 1 0
y7 y6 y5 y4 y3 y2 y1 y0
- y9..y0 = absolute y value (vertical)
+ y15..y0 = absolute y value (vertical)
4.2.2 Two finger touch
diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS
index a67112feba18..d5b0b1b6dc52 100644
--- a/trunk/MAINTAINERS
+++ b/trunk/MAINTAINERS
@@ -586,12 +586,6 @@ F: drivers/mtd/nand/bcm_umi_bch.c
F: drivers/mtd/nand/bcm_umi_hamming.c
F: drivers/mtd/nand/nand_bcm_umi.h
-ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
-M: Anton Vorontsov
-S: Maintained
-F: arch/arm/mach-cns3xxx/
-T: git git://git.infradead.org/users/cbou/linux-cns3xxx.git
-
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
M: Hartley Sweeten
M: Ryan Mallon
@@ -781,10 +775,11 @@ M: Philipp Zabel
S: Maintained
ARM/Marvell Loki/Kirkwood/MV78xx0/Orion SOC support
-M: Lennert Buytenhek
-M: Nicolas Pitre
+M: Lennert Buytenhek
+M: Nicolas Pitre
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Odd Fixes
+T: git git://git.marvell.com/orion
+S: Maintained
F: arch/arm/mach-loki/
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mv78xx0/
@@ -999,20 +994,6 @@ W: http://www.arm.linux.org.uk/
S: Maintained
F: arch/arm/vfp/
-ARM/VOIPAC PXA270 SUPPORT
-M: Marek Vasut
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: arch/arm/mach-pxa/vpac270.c
-F: arch/arm/mach-pxa/include/mach-pxa/vpac270.h
-
-ARM/ZIPIT Z2 SUPPORT
-M: Marek Vasut
-L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S: Maintained
-F: arch/arm/mach-pxa/z2.c
-F: arch/arm/mach-pxa/include/mach-pxa/z2.h
-
ASC7621 HARDWARE MONITOR DRIVER
M: George Joseph
L: lm-sensors@lm-sensors.org
@@ -3643,8 +3624,7 @@ F: drivers/net/wireless/mwl8k.c
MARVELL SOC MMC/SD/SDIO CONTROLLER DRIVER
M: Nicolas Pitre
-S: Odd Fixes
-F: drivers/mmc/host/mvsdio.*
+S: Maintained
MARVELL YUKON / SYSKONNECT DRIVER
M: Mirko Lindner
@@ -5141,7 +5121,7 @@ F: mm/sl?b.c
SMC91x ETHERNET DRIVER
M: Nicolas Pitre
-S: Odd Fixes
+S: Maintained
F: drivers/net/smc91x.*
SMSC47B397 HARDWARE MONITOR DRIVER
diff --git a/trunk/Makefile b/trunk/Makefile
index 701bc65b3952..5f05f8cbeda4 100644
--- a/trunk/Makefile
+++ b/trunk/Makefile
@@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 34
-EXTRAVERSION = -rc7
+EXTRAVERSION = -rc6
NAME = Sheep on Meth
# *DOCUMENTATION*
diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig
index 3806d636a401..92622eb5cc0d 100644
--- a/trunk/arch/arm/Kconfig
+++ b/trunk/arch/arm/Kconfig
@@ -297,15 +297,6 @@ config ARCH_CLPS711X
help
Support for Cirrus Logic 711x/721x based boards.
-config ARCH_CNS3XXX
- bool "Cavium Networks CNS3XXX family"
- select CPU_V6
- select GENERIC_TIME
- select GENERIC_CLOCKEVENTS
- select ARM_GIC
- help
- Support for Cavium Networks CNS3XXX platform.
-
config ARCH_GEMINI
bool "Cortina Systems Gemini"
select CPU_FA526
@@ -610,15 +601,14 @@ config ARCH_PXA
config ARCH_MSM
bool "Qualcomm MSM"
- select HAVE_CLK
+ select CPU_V6
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
- Support for Qualcomm MSM/QSD based systems. This runs on the
- apps processor of the MSM/QSD and depends on a shared memory
- interface to the modem processor which runs the baseband
- stack and controls some vital subsystems
- (clock and power control, etc).
+ Support for Qualcomm MSM7K based systems. This runs on the ARM11
+ apps processor of the MSM7K and depends on a shared memory
+ interface to the ARM9 modem processor which runs the baseband stack
+ and controls some vital subsystems (clock and power control, etc).
config ARCH_SHMOBILE
bool "Renesas SH-Mobile"
@@ -827,8 +817,6 @@ source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
-source "arch/arm/mach-cns3xxx/Kconfig"
-
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-dove/Kconfig"
diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile
index 3e312ec8e624..ed820e737a8a 100644
--- a/trunk/arch/arm/Makefile
+++ b/trunk/arch/arm/Makefile
@@ -121,7 +121,6 @@ machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_BCMRING) := bcmring
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
-machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) := davinci
machine-$(CONFIG_ARCH_DOVE) := dove
machine-$(CONFIG_ARCH_EBSA110) := ebsa110
diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S
index c5191b1532e8..6ab6b337a913 100644
--- a/trunk/arch/arm/boot/compressed/head.S
+++ b/trunk/arch/arm/boot/compressed/head.S
@@ -685,8 +685,8 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv4_mmu_cache_flush
- .word 0x56056900
- .word 0xffffff00 @ PXA9xx
+ .word 0x56056930
+ .word 0xff0ffff0 @ PXA935
W(b) __armv4_mmu_cache_on
W(b) __armv4_mmu_cache_off
W(b) __armv4_mmu_cache_flush
@@ -697,6 +697,12 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv5tej_mmu_cache_flush
+ .word 0x56056930
+ .word 0xff0ffff0 @ PXA935
+ W(b) __armv4_mmu_cache_on
+ W(b) __armv4_mmu_cache_off
+ W(b) __armv4_mmu_cache_flush
+
.word 0x56050000 @ Feroceon
.word 0xff0f0000
W(b) __armv4_mmu_cache_on
diff --git a/trunk/arch/arm/configs/cns3420vb_defconfig b/trunk/arch/arm/configs/cns3420vb_defconfig
deleted file mode 100644
index d5c088149e46..000000000000
--- a/trunk/arch/arm/configs/cns3420vb_defconfig
+++ /dev/null
@@ -1,831 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc6
-# Sun May 2 21:58:08 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_OPROFILE_ARMV6=y
-CONFIG_OPROFILE_ARM11_CORE=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_TINY_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_NS is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CGROUP_DEVICE is not set
-# CONFIG_CPUSETS is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_RELAY=y
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_SLOW_WORK=y
-# CONFIG_SLOW_WORK_DEBUG is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=m
-# CONFIG_CFQ_GROUP_IOSCHED is not set
-CONFIG_DEFAULT_DEADLINE=y
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="deadline"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-CONFIG_INLINE_SPIN_UNLOCK=y
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-CONFIG_INLINE_READ_UNLOCK=y
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-CONFIG_INLINE_WRITE_UNLOCK=y
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-CONFIG_ARCH_CNS3XXX=y
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P6440 is not set
-# CONFIG_ARCH_S5P6442 is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# CNS3XXX platform type
-#
-CONFIG_MACH_CNS3420VB=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_V6=y
-# CONFIG_CPU_32v6K is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_ABRT_EV6=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_ARM_ERRATA_411920 is not set
-CONFIG_ARM_GIC=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-
-#
-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-#
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=20000
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=y
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-# CONFIG_SATA_PMP is not set
-# CONFIG_ATA_SFF is not set
-# CONFIG_MD is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-# CONFIG_EXT2_FS_SECURITY is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=y
-# CONFIG_FSCACHE_STATS is not set
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-# CONFIG_CACHEFILES is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-# CONFIG_LOGFS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_LKDTM is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_RING_BUFFER=y
-CONFIG_RING_BUFFER_ALLOW_SWAP=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_OC_ETM is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_SMACK is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-# CONFIG_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_ATOMIC64=y
diff --git a/trunk/arch/arm/configs/imote2_defconfig b/trunk/arch/arm/configs/imote2_defconfig
index 21f2bff8a363..95d2becfc664 100644
--- a/trunk/arch/arm/configs/imote2_defconfig
+++ b/trunk/arch/arm/configs/imote2_defconfig
@@ -1,14 +1,13 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc2
-# Thu Apr 8 14:49:08 2010
+# Linux kernel version: 2.6.33-rc8
+# Sat Feb 13 21:48:53 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_HAVE_PROC_CPU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -20,7 +19,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
@@ -62,6 +60,11 @@ CONFIG_RCU_FANOUT=32
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUPS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
@@ -94,14 +97,10 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
#
# Kernel Performance Events And Counters
#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
@@ -185,7 +184,6 @@ CONFIG_MMU=y
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
@@ -195,6 +193,7 @@ CONFIG_MMU=y
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
@@ -211,26 +210,21 @@ CONFIG_MMU=y
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P6440 is not set
-# CONFIG_ARCH_S5P6442 is not set
# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_U8500 is not set
#
# Intel PXA2xx/PXA3xx Implementations
@@ -259,7 +253,6 @@ CONFIG_ARCH_PXA=y
# CONFIG_MACH_EM_X270 is not set
# CONFIG_MACH_EXEDA is not set
# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_CAPC7117 is not set
# CONFIG_ARCH_GUMSTIX is not set
CONFIG_MACH_INTELMOTE2=y
# CONFIG_MACH_STARGATE2 is not set
@@ -282,11 +275,7 @@ CONFIG_MACH_INTELMOTE2=y
# CONFIG_PXA_EZX is not set
# CONFIG_MACH_MP900C is not set
# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_RAUMFELD_RC is not set
-# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
-# CONFIG_MACH_RAUMFELD_SPEAKER is not set
# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_ICONTROL is not set
# CONFIG_ARCH_PXA_ESERIES is not set
CONFIG_PXA27x=y
CONFIG_PXA_SSP=y
@@ -313,7 +302,6 @@ CONFIG_ARM_THUMB=y
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_IWMMXT=y
CONFIG_XSCALE_PMU=y
-CONFIG_CPU_HAS_PMU=y
CONFIG_COMMON_CLKDEV=y
#
@@ -364,7 +352,7 @@ CONFIG_ALIGNMENT_TRAP=y
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M"
+CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
@@ -372,8 +360,24 @@ CONFIG_ATAGS_PROC=y
#
# CPU Power Management
#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
#
# Floating point emulation
@@ -405,7 +409,6 @@ CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_APM_EMULATION=y
CONFIG_PM_RUNTIME=y
-CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
@@ -413,6 +416,7 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
@@ -502,7 +506,6 @@ CONFIG_NF_CT_NETLINK=m
CONFIG_NETFILTER_XTABLES=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
-# CONFIG_NETFILTER_XT_TARGET_CT is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_LED=m
@@ -619,7 +622,6 @@ CONFIG_IP6_NF_RAW=m
# CONFIG_ATM is not set
CONFIG_STP=m
CONFIG_BRIDGE=m
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
@@ -644,7 +646,32 @@ CONFIG_NET_CLS_ROUTE=y
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+# CONFIG_BT_ATH3K is not set
# CONFIG_AF_RXRPC is not set
CONFIG_FIB_RULES=y
# CONFIG_WIRELESS is not set
@@ -660,8 +687,7 @@ CONFIG_FIB_RULES=y
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
@@ -677,9 +703,9 @@ CONFIG_MTD=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_AR7_PARTS=y
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
@@ -786,7 +812,6 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
-CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@@ -940,7 +965,6 @@ CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
@@ -969,7 +993,6 @@ CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@@ -983,9 +1006,15 @@ CONFIG_I2C_PXA=y
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@@ -1017,12 +1046,10 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
-# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
-# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@@ -1066,12 +1093,10 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
@@ -1080,25 +1105,22 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_TC6393XB is not set
CONFIG_PMIC_DA903X=y
# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
# CONFIG_AB4500_CORE is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
-# CONFIG_REGULATOR_DUMMY is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
CONFIG_REGULATOR_DA903X=y
# CONFIG_REGULATOR_LP3971 is not set
@@ -1196,7 +1218,6 @@ CONFIG_VIDEO_IR_I2C=y
# CONFIG_VIDEO_SAA7191 is not set
# CONFIG_VIDEO_TVP514X is not set
# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_TVP7002 is not set
# CONFIG_VIDEO_VPX3220 is not set
#
@@ -1243,7 +1264,15 @@ CONFIG_SOC_CAMERA_MT9M111=y
CONFIG_VIDEO_PXA27x=y
# CONFIG_VIDEO_SH_MOBILE_CEU is not set
# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_RADIO_TEA5764=y
+CONFIG_RADIO_TEA5764_XTAL=y
+# CONFIG_RADIO_TEF6862 is not set
# CONFIG_DAB is not set
#
@@ -1369,6 +1398,8 @@ CONFIG_HID=y
#
# Special HID drivers
#
+CONFIG_HID_APPLE=m
+# CONFIG_HID_WACOM is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1446,6 +1477,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@@ -1457,6 +1489,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
@@ -1496,7 +1529,6 @@ CONFIG_USB_ETH=y
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_NOKIA is not set
# CONFIG_USB_G_MULTI is not set
#
@@ -1523,6 +1555,8 @@ CONFIG_SDIO_UART=m
#
CONFIG_MMC_PXA=y
# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
CONFIG_MMC_SPI=y
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
@@ -1540,11 +1574,11 @@ CONFIG_LEDS_LP3944=y
# CONFIG_LEDS_REGULATOR is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
-CONFIG_LEDS_TRIGGERS=y
#
# LED Triggers
#
+CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
@@ -1622,7 +1656,7 @@ CONFIG_RTC_INTF_DEV=y
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_SA1100 is not set
-CONFIG_RTC_DRV_PXA=y
+# CONFIG_RTC_DRV_PXA is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
@@ -1647,10 +1681,19 @@ CONFIG_EXT3_FS_XATTR=y
CONFIG_JBD=m
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@@ -1673,7 +1716,9 @@ CONFIG_CUSE=m
#
# CD-ROM/DVD Filesystems
#
-# CONFIG_ISO9660_FS is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
# CONFIG_UDF_FS is not set
#
@@ -1705,14 +1750,12 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
@@ -1722,7 +1765,6 @@ CONFIG_JFFS2_RUBIN=y
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_LOGFS is not set
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
# CONFIG_SQUASHFS_EMBEDDED is not set
@@ -1760,7 +1802,6 @@ CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_CEPH_FS is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS=y
# CONFIG_CIFS_STATS2 is not set
@@ -1854,7 +1895,6 @@ CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
-# CONFIG_PROVE_RCU is not set
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_LOCKDEP is not set
@@ -1878,7 +1918,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
@@ -2022,9 +2061,9 @@ CONFIG_CRC32=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
@@ -2036,4 +2075,3 @@ CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
-CONFIG_GENERIC_ATOMIC64=y
diff --git a/trunk/arch/arm/configs/mmp2_defconfig b/trunk/arch/arm/configs/mmp2_defconfig
index 4b55dcb60029..03f76cfc941c 100644
--- a/trunk/arch/arm/configs/mmp2_defconfig
+++ b/trunk/arch/arm/configs/mmp2_defconfig
@@ -1,14 +1,13 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc5
-# Wed Apr 28 11:23:19 2010
+# Linux kernel version: 2.6.33-rc2
+# Tue Jan 5 13:55:22 2010
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_HAVE_PROC_CPU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -19,7 +18,6 @@ CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -34,12 +32,6 @@ CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_LZO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
@@ -60,6 +52,7 @@ CONFIG_RCU_FANOUT=32
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
@@ -92,14 +85,10 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
#
# Kernel Performance Events And Counters
#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
@@ -115,7 +104,6 @@ CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
-# CONFIG_GCOV_KERNEL is not set
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
@@ -182,7 +170,6 @@ CONFIG_MMU=y
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
@@ -192,6 +179,7 @@ CONFIG_MMU=y
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
@@ -208,26 +196,21 @@ CONFIG_ARCH_MMP=y
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P6440 is not set
-# CONFIG_ARCH_S5P6442 is not set
# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_U8500 is not set
# CONFIG_MACH_TAVOREVB is not set
#
@@ -235,10 +218,8 @@ CONFIG_ARCH_MMP=y
#
# CONFIG_MACH_ASPENITE is not set
# CONFIG_MACH_ZYLONITE2 is not set
-# CONFIG_MACH_AVENGERS_LITE is not set
# CONFIG_MACH_TTC_DKB is not set
CONFIG_MACH_FLINT=y
-CONFIG_MACH_MARVELL_JASPER=y
CONFIG_CPU_MMP2=y
CONFIG_PLAT_PXA=y
@@ -265,10 +246,7 @@ CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_OUTER_CACHE=y
-CONFIG_CACHE_TAUROS2=y
CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_CPU_HAS_PMU=y
# CONFIG_ARM_ERRATA_411920 is not set
CONFIG_COMMON_CLKDEV=y
@@ -320,7 +298,7 @@ CONFIG_ALIGNMENT_TRAP=y
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M user_debug=255"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
@@ -360,6 +338,7 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
@@ -553,7 +532,6 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
-CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@@ -662,7 +640,6 @@ CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@@ -690,7 +667,6 @@ CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@@ -703,9 +679,15 @@ CONFIG_I2C_PXA=y
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
#
@@ -720,16 +702,13 @@ CONFIG_GPIOLIB=y
#
# Memory mapped GPIO expanders:
#
-# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
-# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_ADP5588 is not set
#
# PCI GPIO expanders:
@@ -758,12 +737,10 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
-# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
@@ -772,27 +749,24 @@ CONFIG_MFD_CORE=y
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
-CONFIG_MFD_MAX8925=y
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
+CONFIG_MFD_88PM8607=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_MAX8649=y
-# CONFIG_REGULATOR_MAX8660 is not set
-CONFIG_REGULATOR_MAX8925=y
+CONFIG_REGULATOR_MAX8660=y
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_REGULATOR_88PM8607=y
# CONFIG_MEDIA_SUPPORT is not set
#
@@ -807,7 +781,6 @@ CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_MAX8925=y
#
# Display device support
@@ -848,7 +821,6 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
-CONFIG_RTC_DRV_MAX8925=y
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
@@ -900,6 +872,7 @@ CONFIG_RTC_DRV_MAX8925=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
+CONFIG_EXT4_USE_FOR_EXT23=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
@@ -910,7 +883,7 @@ CONFIG_FS_POSIX_ACL=y
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
+CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
@@ -967,7 +940,6 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_LOGFS is not set
CONFIG_CRAMFS=y
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@@ -995,7 +967,6 @@ CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
-# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@@ -1019,7 +990,7 @@ CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
@@ -1061,7 +1032,6 @@ CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
@@ -1082,7 +1052,6 @@ CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
-CONFIG_DYNAMIC_DEBUG=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
@@ -1090,7 +1059,9 @@ CONFIG_ARM_UNWIND=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_OC_ETM is not set
#
diff --git a/trunk/arch/arm/include/asm/elf.h b/trunk/arch/arm/include/asm/elf.h
index 51662feb9f1d..bff056489cc1 100644
--- a/trunk/arch/arm/include/asm/elf.h
+++ b/trunk/arch/arm/include/asm/elf.h
@@ -9,8 +9,6 @@
#include
#include
-struct task_struct;
-
typedef unsigned long elf_greg_t;
typedef unsigned long elf_freg_t[3];
diff --git a/trunk/arch/arm/kernel/entry-armv.S b/trunk/arch/arm/kernel/entry-armv.S
index 7ee48e7f8f31..e6a0fb0f392e 100644
--- a/trunk/arch/arm/kernel/entry-armv.S
+++ b/trunk/arch/arm/kernel/entry-armv.S
@@ -676,10 +676,10 @@ do_fpe:
* lr = unrecognised FP instruction return address
*/
- .pushsection .data
+ .data
ENTRY(fp_enter)
.word no_fp
- .popsection
+ .text
ENTRY(no_fp)
mov pc, lr
diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c
index a01194e583ff..577543f3857f 100644
--- a/trunk/arch/arm/kernel/smp.c
+++ b/trunk/arch/arm/kernel/smp.c
@@ -86,12 +86,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
return PTR_ERR(idle);
}
ci->idle = idle;
- } else {
- /*
- * Since this idle thread is being re-used, call
- * init_idle() to reinitialize the thread structure.
- */
- init_idle(idle, cpu);
}
/*
diff --git a/trunk/arch/arm/mach-cns3xxx/Kconfig b/trunk/arch/arm/mach-cns3xxx/Kconfig
deleted file mode 100644
index 9ebfcc46feb1..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-menu "CNS3XXX platform type"
- depends on ARCH_CNS3XXX
-
-config MACH_CNS3420VB
- bool "Support for CNS3420 Validation Board"
- help
- Include support for the Cavium Networks CNS3420 MPCore Platform
- Baseboard.
- This is a platform with an on-board ARM11 MPCore and has support
- for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
-
-endmenu
diff --git a/trunk/arch/arm/mach-cns3xxx/Makefile b/trunk/arch/arm/mach-cns3xxx/Makefile
deleted file mode 100644
index 427507a2d696..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
-obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
diff --git a/trunk/arch/arm/mach-cns3xxx/Makefile.boot b/trunk/arch/arm/mach-cns3xxx/Makefile.boot
deleted file mode 100644
index 777012865220..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
- zreladdr-y := 0x00008000
-params_phys-y := 0x00000100
-initrd_phys-y := 0x00C00000
diff --git a/trunk/arch/arm/mach-cns3xxx/cns3420vb.c b/trunk/arch/arm/mach-cns3xxx/cns3420vb.c
deleted file mode 100644
index 2e30c8288740..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/cns3420vb.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Cavium Networks CNS3420 Validation Board
- *
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2008 ARM Limited
- * Copyright 2008 Cavium Networks
- * Scott Shu
- * Copyright 2010 MontaVista Software, LLC.
- * Anton Vorontsov
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "core.h"
-
-/*
- * NOR Flash
- */
-static struct mtd_partition cns3420_nor_partitions[] = {
- {
- .name = "uboot",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE,
- }, {
- .name = "kernel",
- .size = 0x004C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "filesystem",
- .size = 0x7000000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "filesystem2",
- .size = 0x0AE0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "ubootenv",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data cns3420_nor_pdata = {
- .width = 2,
- .parts = cns3420_nor_partitions,
- .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
-};
-
-static struct resource cns3420_nor_res = {
- .start = CNS3XXX_FLASH_BASE,
- .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
-};
-
-static struct platform_device cns3420_nor_pdev = {
- .name = "physmap-flash",
- .id = 0,
- .resource = &cns3420_nor_res,
- .num_resources = 1,
- .dev = {
- .platform_data = &cns3420_nor_pdata,
- },
-};
-
-/*
- * UART
- */
-static void __init cns3420_early_serial_setup(void)
-{
-#ifdef CONFIG_SERIAL_8250_CONSOLE
- static struct uart_port cns3420_serial_port = {
- .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
- .mapbase = CNS3XXX_UART0_BASE,
- .irq = IRQ_CNS3XXX_UART0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .regshift = 2,
- .uartclk = 24000000,
- .line = 0,
- .type = PORT_16550A,
- .fifosize = 16,
- };
-
- early_serial_setup(&cns3420_serial_port);
-#endif
-}
-
-/*
- * Initialization
- */
-static struct platform_device *cns3420_pdevs[] __initdata = {
- &cns3420_nor_pdev,
-};
-
-static void __init cns3420_init(void)
-{
- platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
-
- pm_power_off = cns3xxx_power_off;
-}
-
-static struct map_desc cns3420_io_desc[] __initdata = {
- {
- .virtual = CNS3XXX_UART0_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-static void __init cns3420_map_io(void)
-{
- cns3xxx_map_io();
- iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
-
- cns3420_early_serial_setup();
-}
-
-MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
- .phys_io = CNS3XXX_UART0_BASE,
- .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
- .boot_params = 0x00000100,
- .map_io = cns3420_map_io,
- .init_irq = cns3xxx_init_irq,
- .timer = &cns3xxx_timer,
- .init_machine = cns3420_init,
-MACHINE_END
diff --git a/trunk/arch/arm/mach-cns3xxx/core.c b/trunk/arch/arm/mach-cns3xxx/core.c
deleted file mode 100644
index 9ca4d581016f..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/core.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright 1999 - 2003 ARM Limited
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "core.h"
-
-static struct map_desc cns3xxx_io_desc[] __initdata = {
- {
- .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_GPIOA_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_GPIOB_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_MISC_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = CNS3XXX_PM_BASE_VIRT,
- .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-void __init cns3xxx_map_io(void)
-{
- iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
-}
-
-/* used by entry-macro.S */
-void __iomem *gic_cpu_base_addr;
-
-void __init cns3xxx_init_irq(void)
-{
- gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
- gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
- gic_cpu_init(0, gic_cpu_base_addr);
-}
-
-void cns3xxx_power_off(void)
-{
- u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
- u32 clkctrl;
-
- printk(KERN_INFO "powering system down...\n");
-
- clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
- clkctrl &= 0xfffff1ff;
- clkctrl |= (0x5 << 9); /* Hibernate */
- writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
-
-}
-
-/*
- * Timer
- */
-static void __iomem *cns3xxx_tmr1;
-
-static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
- struct clock_event_device *clk)
-{
- unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- int pclk = cns3xxx_cpu_clock() / 8;
- int reload;
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- reload = pclk * 20 / (3 * HZ) * 0x25000;
- writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- /* period set, and timer enabled in 'next_event' hook */
- ctrl |= (1 << 2) | (1 << 9);
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- default:
- ctrl = 0;
- }
-
- writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-}
-
-static int cns3xxx_timer_set_next_event(unsigned long evt,
- struct clock_event_device *unused)
-{
- unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
- writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- return 0;
-}
-
-static struct clock_event_device cns3xxx_tmr1_clockevent = {
- .name = "cns3xxx timer1",
- .shift = 8,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = cns3xxx_timer_set_mode,
- .set_next_event = cns3xxx_timer_set_next_event,
- .rating = 350,
- .cpumask = cpu_all_mask,
-};
-
-static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
-{
- cns3xxx_tmr1_clockevent.irq = timer_irq;
- cns3xxx_tmr1_clockevent.mult =
- div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
- cns3xxx_tmr1_clockevent.shift);
- cns3xxx_tmr1_clockevent.max_delta_ns =
- clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
- cns3xxx_tmr1_clockevent.min_delta_ns =
- clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
-
- clockevents_register_device(&cns3xxx_tmr1_clockevent);
-}
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
- u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
- u32 val;
-
- /* Clear the interrupt */
- val = readl(stat);
- writel(val & ~(1 << 2), stat);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction cns3xxx_timer_irq = {
- .name = "timer",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = cns3xxx_timer_interrupt,
-};
-
-/*
- * Set up the clock source and clock events devices
- */
-static void __init __cns3xxx_timer_init(unsigned int timer_irq)
-{
- u32 val;
- u32 irq_mask;
-
- /*
- * Initialise to a known state (all timers off)
- */
-
- /* disable timer1 and timer2 */
- writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- /* stop free running timer3 */
- writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
-
- /* timer1 */
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
-
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
- writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
-
- /* mask irq, non-mask timer1 overflow */
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- irq_mask &= ~(1 << 2);
- irq_mask |= 0x03;
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-
- /* down counter */
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- val |= (1 << 9);
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- /* timer2 */
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
-
- /* mask irq */
- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
-
- /* down counter */
- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
- val |= (1 << 10);
- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
-
- /* Make irqs happen for the system timer */
- setup_irq(timer_irq, &cns3xxx_timer_irq);
-
- cns3xxx_clockevents_init(timer_irq);
-}
-
-static void __init cns3xxx_timer_init(void)
-{
- cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
-
- __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
-}
-
-struct sys_timer cns3xxx_timer = {
- .init = cns3xxx_timer_init,
-};
diff --git a/trunk/arch/arm/mach-cns3xxx/core.h b/trunk/arch/arm/mach-cns3xxx/core.h
deleted file mode 100644
index 6b33ec11346e..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/core.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2004 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __CNS3XXX_CORE_H
-#define __CNS3XXX_CORE_H
-
-extern void __iomem *gic_cpu_base_addr;
-extern struct sys_timer cns3xxx_timer;
-
-void __init cns3xxx_map_io(void);
-void __init cns3xxx_init_irq(void);
-void cns3xxx_power_off(void);
-void cns3xxx_pwr_power_up(unsigned int block);
-void cns3xxx_pwr_power_down(unsigned int block);
-
-#endif /* __CNS3XXX_CORE_H */
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
deleted file mode 100644
index 8a2f5a21d4ee..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ /dev/null
@@ -1,635 +0,0 @@
-/*
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_BOARD_CNS3XXXH
-#define __MACH_BOARD_CNS3XXXH
-
-/*
- * Memory map
- */
-#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
-#define CNS3XXX_FLASH_SIZE SZ_256M
-
-#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
-
-#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
-
-#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
-#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
-
-#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
-#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
-
-#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
-
-#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
-#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
-
-#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
-#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
-
-#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
-#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
-
-#define SMC_MEMC_STATUS_OFFSET 0x000
-#define SMC_MEMIF_CFG_OFFSET 0x004
-#define SMC_MEMC_CFG_SET_OFFSET 0x008
-#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
-#define SMC_DIRECT_CMD_OFFSET 0x010
-#define SMC_SET_CYCLES_OFFSET 0x014
-#define SMC_SET_OPMODE_OFFSET 0x018
-#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
-#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
-#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
-#define SMC_NAND_CYCLES0_0_OFFSET 0x100
-#define SMC_OPMODE0_0_OFFSET 0x104
-#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
-#define SMC_NAND_CYCLES0_1_OFFSET 0x120
-#define SMC_OPMODE0_1_OFFSET 0x124
-#define SMC_USER_STATUS_OFFSET 0x200
-#define SMC_USER_CONFIG_OFFSET 0x204
-#define SMC_ECC_STATUS_OFFSET 0x300
-#define SMC_ECC_MEMCFG_OFFSET 0x304
-#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
-#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
-#define SMC_ECC_ADDR0_OFFSET 0x310
-#define SMC_ECC_ADDR1_OFFSET 0x314
-#define SMC_ECC_VALUE0_OFFSET 0x318
-#define SMC_ECC_VALUE1_OFFSET 0x31C
-#define SMC_ECC_VALUE2_OFFSET 0x320
-#define SMC_ECC_VALUE3_OFFSET 0x324
-#define SMC_PERIPH_ID_0_OFFSET 0xFE0
-#define SMC_PERIPH_ID_1_OFFSET 0xFE4
-#define SMC_PERIPH_ID_2_OFFSET 0xFE8
-#define SMC_PERIPH_ID_3_OFFSET 0xFEC
-#define SMC_PCELL_ID_0_OFFSET 0xFF0
-#define SMC_PCELL_ID_1_OFFSET 0xFF4
-#define SMC_PCELL_ID_2_OFFSET 0xFF8
-#define SMC_PCELL_ID_3_OFFSET 0xFFC
-
-#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
-#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
-
-#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
-#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
-
-#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
-#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
-
-#define RTC_SEC_OFFSET 0x00
-#define RTC_MIN_OFFSET 0x04
-#define RTC_HOUR_OFFSET 0x08
-#define RTC_DAY_OFFSET 0x0C
-#define RTC_SEC_ALM_OFFSET 0x10
-#define RTC_MIN_ALM_OFFSET 0x14
-#define RTC_HOUR_ALM_OFFSET 0x18
-#define RTC_REC_OFFSET 0x1C
-#define RTC_CTRL_OFFSET 0x20
-#define RTC_INTR_STS_OFFSET 0x34
-
-#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
-
-#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
-
-#define PM_CLK_GATE_OFFSET 0x00
-#define PM_SOFT_RST_OFFSET 0x04
-#define PM_HS_CFG_OFFSET 0x08
-#define PM_CACTIVE_STA_OFFSET 0x0C
-#define PM_PWR_STA_OFFSET 0x10
-#define PM_SYS_CLK_CTRL_OFFSET 0x14
-#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
-#define PM_PLL_HM_PD_OFFSET 0x1C
-
-#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
-
-#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
-#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
-
-#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
-#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
-
-#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
-#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
-
-#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
-#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
-
-#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
-#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
-
-#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
-#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
-
-#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
-
-#define TIMER1_COUNTER_OFFSET 0x00
-#define TIMER1_AUTO_RELOAD_OFFSET 0x04
-#define TIMER1_MATCH_V1_OFFSET 0x08
-#define TIMER1_MATCH_V2_OFFSET 0x0C
-
-#define TIMER2_COUNTER_OFFSET 0x10
-#define TIMER2_AUTO_RELOAD_OFFSET 0x14
-#define TIMER2_MATCH_V1_OFFSET 0x18
-#define TIMER2_MATCH_V2_OFFSET 0x1C
-
-#define TIMER1_2_CONTROL_OFFSET 0x30
-#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
-#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
-
-#define TIMER_FREERUN_OFFSET 0x40
-#define TIMER_FREERUN_CONTROL_OFFSET 0x44
-
-#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
-#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
-
-#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
-#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
-
-#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
-#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
-
-#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
-#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
-
-#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
-#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
-
-#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
-#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
-
-#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
-#define CNS3XXX_SATA2_SIZE SZ_16M
-#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
-
-#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
-#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
-
-#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
-#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
-
-#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
-#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
-
-#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
-#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
-
-#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
-#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
-
-#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
-#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
-
-#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
-#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
-
-#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
-#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
-
-#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
-#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
-
-#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
-#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
-
-#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
-#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
-
-#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
-#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
-
-#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
-#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
-
-#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
-#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
-
-#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
-#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
-
-#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
-#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
-
-#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
-#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
-
-#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
-#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
-
-/*
- * Testchip peripheral and fpga gic regions
- */
-#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
-
-#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
-
-#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
-
-#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
-
-#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
-#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
-
-/*
- * Misc block
- */
-#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
-
-#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
-#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
-#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
-#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
-#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
-#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
-#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
-#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
-#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
-#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
-#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
-#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
-#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
-#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
-#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
-#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
-#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
-
-/*
- * Power management and clock control
- */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG PMU_REG_VALUE(0x030)
-
-/* PM_CLK_GATE_REG */
-#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
-#define PM_CLK_GATE_REG_OFFSET_GPU (24)
-#define PM_CLK_GATE_REG_OFFSET_CIM (23)
-#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
-#define PM_CLK_GATE_REG_OFFSET_I2S (21)
-#define PM_CLK_GATE_REG_OFFSET_RAID (20)
-#define PM_CLK_GATE_REG_OFFSET_SATA (19)
-#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
-#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
-#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
-#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
-#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
-#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
-#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
-#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
-#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
-#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
-#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
-#define PM_CLK_GATE_REG_OFFSET_RTC (5)
-#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
-#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
-#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
-#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
-
-/* PM_SOFT_RST_REG */
-#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
-#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
-#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
-#define PM_SOFT_RST_REG_OFFST_SDIO (25)
-#define PM_SOFT_RST_REG_OFFST_GPU (24)
-#define PM_SOFT_RST_REG_OFFST_CIM (23)
-#define PM_SOFT_RST_REG_OFFST_LCDC (22)
-#define PM_SOFT_RST_REG_OFFST_I2S (21)
-#define PM_SOFT_RST_REG_OFFST_RAID (20)
-#define PM_SOFT_RST_REG_OFFST_SATA (19)
-#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
-#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
-#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
-#define PM_SOFT_RST_REG_OFFST_TIMER (14)
-#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
-#define PM_SOFT_RST_REG_OFFST_HCIE (12)
-#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
-#define PM_SOFT_RST_REG_OFFST_GPIO (10)
-#define PM_SOFT_RST_REG_OFFST_UART3 (9)
-#define PM_SOFT_RST_REG_OFFST_UART2 (8)
-#define PM_SOFT_RST_REG_OFFST_UART1 (7)
-#define PM_SOFT_RST_REG_OFFST_RTC (5)
-#define PM_SOFT_RST_REG_OFFST_GDMA (4)
-#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
-#define PM_SOFT_RST_REG_OFFST_DMC (2)
-#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
-#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
-#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
-
-/* PMHS_CFG_REG */
-#define PM_HS_CFG_REG_OFFSET_SDIO (25)
-#define PM_HS_CFG_REG_OFFSET_GPU (24)
-#define PM_HS_CFG_REG_OFFSET_CIM (23)
-#define PM_HS_CFG_REG_OFFSET_LCDC (22)
-#define PM_HS_CFG_REG_OFFSET_I2S (21)
-#define PM_HS_CFG_REG_OFFSET_RAID (20)
-#define PM_HS_CFG_REG_OFFSET_SATA (19)
-#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
-#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
-#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
-#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
-#define PM_HS_CFG_REG_OFFSET_TIMER (14)
-#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
-#define PM_HS_CFG_REG_OFFSET_HCIE (12)
-#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
-#define PM_HS_CFG_REG_OFFSET_GPIO (10)
-#define PM_HS_CFG_REG_OFFSET_UART3 (9)
-#define PM_HS_CFG_REG_OFFSET_UART2 (8)
-#define PM_HS_CFG_REG_OFFSET_UART1 (7)
-#define PM_HS_CFG_REG_OFFSET_RTC (5)
-#define PM_HS_CFG_REG_OFFSET_GDMA (4)
-#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_HS_CFG_REG_OFFSET_DMC (2)
-#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
-#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
-#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
-
-/* PM_CACTIVE_STA_REG */
-#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
-#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
-#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
-#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
-#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
-#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
-#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
-#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
-#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
-#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
-#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
-#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
-#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
-#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
-#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
-#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
-#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
-#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
-#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
-#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
-#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
-#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
-#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
-#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
-
-/* PM_PWR_STA_REG */
-#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
-#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
-#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
-#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
-#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
-#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
-#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
-#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
-#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
-#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
-#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
-#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
-#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
-#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
-#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
-#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
-#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
-#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
-#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
-#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
-#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
-#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
-#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
-#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
-#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
-
-/* PM_CLK_CTRL_REG */
-#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
-#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
-#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
-#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
-#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
-#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
-#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
-#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
-#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
-#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
-#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
-#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
-#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
-#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
-#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
-#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
-
-#define PM_CPU_CLK_DIV(DIV) { \
- PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
- PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
-}
-
-#define PM_PLL_CPU_SEL(CPU) { \
- PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
- PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
-}
-
-/* PM_PLL_LCD_I2S_CTRL_REG */
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
-#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
-
-/* PM_PLL_HM_PD_CTRL_REG */
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
-#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
-#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
-
-/* PM_WDT_CTRL_REG */
-#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
-
-/* PM_CSR_REG - Clock Scaling Register*/
-#define PM_CSR_REG_OFFSET_CSR_EN (30)
-#define PM_CSR_REG_OFFSET_CSR_NUM (0)
-
-#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/trunk/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
deleted file mode 100644
index 5e1c5545680f..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Low-level IRQ helper macros for Cavium Networks platforms
- *
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =gic_cpu_base_addr
- ldr \base, [\base]
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
- /*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec. To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local. We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt. We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
- ldr \tmp, =1021
-
- bic \irqnr, \irqstat, #0x1c00
-
- cmp \irqnr, #29
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-
- .endm
-
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- cmpcs \irqnr, \irqnr
- .endm
-
- /* As above, this assumes that irqstat and base are preserved.. */
-
- .macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
- .endm
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/hardware.h b/trunk/arch/arm/mach-cns3xxx/include/mach/hardware.h
deleted file mode 100644
index 57e09836f9d7..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file contains the hardware definitions of the Cavium Networks boards.
- *
- * Copyright 2003 ARM Limited.
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include
-
-/* macro to get at IO space when running virtually */
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0x00000000
-#define pcibios_assign_all_busses() 1
-
-#endif
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/io.h b/trunk/arch/arm/mach-cns3xxx/include/mach/io.h
deleted file mode 100644
index 33b6fc1ece7c..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/io.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2008 Cavium Networks
- * Copyright 2003 ARM Limited
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#endif
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/irqs.h b/trunk/arch/arm/mach-cns3xxx/include/mach/irqs.h
deleted file mode 100644
index 2ab96f8085c8..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/irqs.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_LOCALTIMER 29
-#define IRQ_LOCALWDOG 30
-#define IRQ_TC11MP_GIC_START 32
-
-#include
-
-#ifndef NR_IRQS
-#error "NR_IRQS not defined by the board-specific files"
-#endif
-
-#endif
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/memory.h b/trunk/arch/arm/mach-cns3xxx/include/mach/memory.h
deleted file mode 100644
index 3b6b769b7a27..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MEMORY_H
-#define __MACH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PHYS_OFFSET UL(0x00000000)
-
-#define __phys_to_bus(x) ((x) + PHYS_OFFSET)
-#define __bus_to_phys(x) ((x) - PHYS_OFFSET)
-
-#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
-#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
-#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
-#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
-
-#endif
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/system.h b/trunk/arch/arm/mach-cns3xxx/include/mach/system.h
deleted file mode 100644
index 58bb03ae3cf4..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include
-#include
-#include
-
-static inline void arch_idle(void)
-{
- /*
- * This should do all the clock switching
- * and wait for interrupt tricks
- */
- cpu_do_idle();
-}
-
-void arch_reset(char mode, const char *cmd);
-
-#endif
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/timex.h b/trunk/arch/arm/mach-cns3xxx/include/mach/timex.h
deleted file mode 100644
index 1fd04217cacb..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Cavium Networks architecture timex specifications
- *
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/trunk/arch/arm/mach-cns3xxx/include/mach/uncompress.h
deleted file mode 100644
index de8ead9b91f7..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-
-#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
-
-/*
- * Return the UART base address
- */
-static inline unsigned long get_uart_base(void)
-{
- if (machine_is_cns3420vb())
- return CNS3XXX_UART0_BASE;
- else
- return 0;
-}
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
- unsigned long base = get_uart_base();
-
- while (AMBA_UART_FR(base) & (1 << 5))
- barrier();
-
- AMBA_UART_DR(base) = c;
-}
-
-static inline void flush(void)
-{
- unsigned long base = get_uart_base();
-
- while (AMBA_UART_FR(base) & (1 << 3))
- barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/trunk/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 4d381ec05278..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright 2000 Russell King.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#define VMALLOC_END 0xd8000000
diff --git a/trunk/arch/arm/mach-cns3xxx/pm.c b/trunk/arch/arm/mach-cns3xxx/pm.c
deleted file mode 100644
index 725e1a4fc231..000000000000
--- a/trunk/arch/arm/mach-cns3xxx/pm.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-
-void cns3xxx_pwr_clk_en(unsigned int block)
-{
- PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
-}
-
-void cns3xxx_pwr_power_up(unsigned int block)
-{
- PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
-
- /* Wait for 300us for the PLL output clock locked. */
- udelay(300);
-};
-
-void cns3xxx_pwr_power_down(unsigned int block)
-{
- /* write '1' to power down */
- PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
-};
-
-static void cns3xxx_pwr_soft_rst_force(unsigned int block)
-{
- /*
- * bit 0, 28, 29 => program low to reset,
- * the other else program low and then high
- */
- if (block & 0x30000001) {
- PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
- } else {
- PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
- PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
- }
-}
-
-void cns3xxx_pwr_soft_rst(unsigned int block)
-{
- static unsigned int soft_reset;
-
- if (soft_reset & block) {
- /* SPI/I2C/GPIO use the same block, reset once. */
- return;
- } else {
- soft_reset |= block;
- }
- cns3xxx_pwr_soft_rst_force(block);
-}
-
-void arch_reset(char mode, const char *cmd)
-{
- /*
- * To reset, we hit the on-board reset register
- * in the system FPGA.
- */
- cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
-}
-
-/*
- * cns3xxx_cpu_clock - return CPU/L2 clock
- * aclk: cpu clock/2
- * hclk: cpu clock/4
- * pclk: cpu clock/8
- */
-int cns3xxx_cpu_clock(void)
-{
- int cpu;
- int cpu_sel;
- int div_sel;
-
- cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
- div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
-
- cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
-
- return cpu;
-}
diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..17879a876be6 100644
--- a/trunk/arch/arm/mach-kirkwood/Kconfig
+++ b/trunk/arch/arm/mach-kirkwood/Kconfig
@@ -38,12 +38,6 @@ config MACH_ESATA_SHEEVAPLUG
Say 'Y' here if you want your kernel to support the
Marvell eSATA SheevaPlug Reference Board.
-config MACH_GURUPLUG
- bool "Marvell GuruPlug Reference Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell GuruPlug Reference Board.
-
config MACH_TS219
bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
help
@@ -87,18 +81,6 @@ config MACH_INETSPACE_V2
Say 'Y' here if you want your kernel to support the
LaCie Internet Space v2 NAS.
-config MACH_NET2BIG_V2
- bool "LaCie 2Big Network v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie 2Big Network v2 NAS.
-
-config MACH_NET5BIG_V2
- bool "LaCie 5Big Network v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie 5Big Network v2 NAS.
-
endmenu
endif
diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..a5530e36ba3e 100644
--- a/trunk/arch/arm/mach-kirkwood/Makefile
+++ b/trunk/arch/arm/mach-kirkwood/Makefile
@@ -6,13 +6,10 @@ obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
-obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
-obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
-obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c
deleted file mode 100644
index 54d07c89d4ff..000000000000
--- a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/guruplug-setup.c
- *
- * Marvell GuruPlug Reference Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition guruplug_nand_parts[] = {
- {
- .name = "u-boot",
- .offset = 0,
- .size = SZ_1M
- }, {
- .name = "uImage",
- .offset = MTDPART_OFS_NXTBLK,
- .size = SZ_4M
- }, {
- .name = "root",
- .offset = MTDPART_OFS_NXTBLK,
- .size = MTDPART_SIZ_FULL
- },
-};
-
-static struct mv643xx_eth_platform_data guruplug_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data guruplug_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(1),
-};
-
-static struct mv_sata_platform_data guruplug_sata_data = {
- .n_ports = 1,
-};
-
-static struct mvsdio_platform_data guruplug_mvsdio_data = {
- /* unfortunately the CD signal has not been connected */
-};
-
-static struct gpio_led guruplug_led_pins[] = {
- {
- .name = "guruplug:red:health",
- .gpio = 46,
- .active_low = 1,
- },
- {
- .name = "guruplug:green:health",
- .gpio = 47,
- .active_low = 1,
- },
- {
- .name = "guruplug:red:wmode",
- .gpio = 48,
- .active_low = 1,
- },
- {
- .name = "guruplug:green:wmode",
- .gpio = 49,
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data guruplug_led_data = {
- .leds = guruplug_led_pins,
- .num_leds = ARRAY_SIZE(guruplug_led_pins),
-};
-
-static struct platform_device guruplug_leds = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &guruplug_led_data,
- }
-};
-
-static unsigned int guruplug_mpp_config[] __initdata = {
- MPP46_GPIO, /* M_RLED */
- MPP47_GPIO, /* M_GLED */
- MPP48_GPIO, /* B_RLED */
- MPP49_GPIO, /* B_GLED */
- 0
-};
-
-static void __init guruplug_init(void)
-{
- /*
- * Basic setup. Needs to be called early.
- */
- kirkwood_init();
- kirkwood_mpp_conf(guruplug_mpp_config);
-
- kirkwood_uart0_init();
- kirkwood_nand_init(ARRAY_AND_SIZE(guruplug_nand_parts), 25);
-
- kirkwood_ehci_init();
- kirkwood_ge00_init(&guruplug_ge00_data);
- kirkwood_ge01_init(&guruplug_ge01_data);
- kirkwood_sata_init(&guruplug_sata_data);
- kirkwood_sdio_init(&guruplug_mvsdio_data);
-
- platform_device_register(&guruplug_leds);
-}
-
-MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
- /* Maintainer: Siddarth Gore */
- .phys_io = KIRKWOOD_REGS_PHYS_BASE,
- .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
- .boot_params = 0x00000100,
- .init_machine = guruplug_init,
- .map_io = kirkwood_map_io,
- .init_irq = kirkwood_init_irq,
- .timer = &kirkwood_timer,
-MACHINE_END
diff --git a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c
deleted file mode 100644
index 8a2bb0228e4f..000000000000
--- a/trunk/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/netxbig_v2-setup.c
- *
- * LaCie 2Big and 5Big Network v2 board setup
- *
- * Copyright (C) 2010 Simon Guinot
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include "common.h"
-#include "mpp.h"
-
-/*****************************************************************************
- * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
- ****************************************************************************/
-
-static struct mtd_partition netxbig_v2_flash_parts[] = {
- {
- .name = "u-boot",
- .size = MTDPART_SIZ_FULL,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE, /* force read-only */
- },
-};
-
-static const struct flash_platform_data netxbig_v2_flash = {
- .type = "mx25l4005a",
- .name = "spi_flash",
- .parts = netxbig_v2_flash_parts,
- .nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts),
-};
-
-static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
- {
- .modalias = "m25p80",
- .platform_data = &netxbig_v2_flash,
- .irq = -1,
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 0,
- },
-};
-
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-
-static struct mv643xx_eth_platform_data netxbig_v2_ge00_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
-};
-
-/*****************************************************************************
- * I2C devices
- ****************************************************************************/
-
-static struct at24_platform_data at24c04 = {
- .byte_len = SZ_4K / 8,
- .page_size = 16,
-};
-
-/*
- * i2c addr | chip | description
- * 0x50 | HT24LC04 | eeprom (512B)
- */
-
-static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
- {
- I2C_BOARD_INFO("24c04", 0x50),
- .platform_data = &at24c04,
- }
-};
-
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-
-static struct mv_sata_platform_data netxbig_v2_sata_data = {
- .n_ports = 2,
-};
-
-static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
-
-static void __init netxbig_v2_sata_power_init(void)
-{
- int i;
- int err;
- int hdd_nb;
-
- if (machine_is_net2big_v2())
- hdd_nb = 2;
- else
- hdd_nb = 5;
-
- /* Power up all hard disks. */
- for (i = 0; i < hdd_nb; i++) {
- err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
- if (err == 0) {
- err = gpio_direction_output(
- netxbig_v2_gpio_hdd_power[i], 1);
- /* Free the HDD power GPIOs. This allow user-space to
- * configure them via the gpiolib sysfs interface. */
- gpio_free(netxbig_v2_gpio_hdd_power[i]);
- }
- if (err)
- pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
- }
-}
-
-/*****************************************************************************
- * GPIO keys
- ****************************************************************************/
-
-#define NETXBIG_V2_GPIO_SWITCH_POWER_ON 13
-#define NETXBIG_V2_GPIO_SWITCH_POWER_OFF 15
-#define NETXBIG_V2_GPIO_FUNC_BUTTON 34
-
-#define NETXBIG_V2_SWITCH_POWER_ON 0x1
-#define NETXBIG_V2_SWITCH_POWER_OFF 0x2
-
-static struct gpio_keys_button netxbig_v2_buttons[] = {
- [0] = {
- .type = EV_SW,
- .code = NETXBIG_V2_SWITCH_POWER_ON,
- .gpio = NETXBIG_V2_GPIO_SWITCH_POWER_ON,
- .desc = "Back power switch (on|auto)",
- .active_low = 1,
- },
- [1] = {
- .type = EV_SW,
- .code = NETXBIG_V2_SWITCH_POWER_OFF,
- .gpio = NETXBIG_V2_GPIO_SWITCH_POWER_OFF,
- .desc = "Back power switch (auto|off)",
- .active_low = 1,
- },
- [2] = {
- .code = KEY_OPTION,
- .gpio = NETXBIG_V2_GPIO_FUNC_BUTTON,
- .desc = "Function button",
- .active_low = 1,
- },
-};
-
-static struct gpio_keys_platform_data netxbig_v2_button_data = {
- .buttons = netxbig_v2_buttons,
- .nbuttons = ARRAY_SIZE(netxbig_v2_buttons),
-};
-
-static struct platform_device netxbig_v2_gpio_buttons = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &netxbig_v2_button_data,
- },
-};
-
-/*****************************************************************************
- * GPIO LEDs
- ****************************************************************************/
-
-/*
- * The LEDs are controlled by a CPLD and can be configured through a GPIO
- * extension bus:
- *
- * - address register : bit [0-2] -> GPIO [47-49]
- * - data register : bit [0-2] -> GPIO [44-46]
- * - enable register : GPIO 29
- *
- * Address register selection:
- *
- * addr | register
- * ----------------------------
- * 0 | front LED
- * 1 | front LED brightness
- * 2 | HDD LED brightness
- * 3 | HDD1 LED
- * 4 | HDD2 LED
- * 5 | HDD3 LED
- * 6 | HDD4 LED
- * 7 | HDD5 LED
- *
- * Data register configuration:
- *
- * data | LED brightness
- * -------------------------------------------------
- * 0 | min (off)
- * - | -
- * 7 | max
- *
- * data | front LED mode
- * -------------------------------------------------
- * 0 | fix off
- * 1 | fix blue on
- * 2 | fix red on
- * 3 | blink blue on=1 sec and blue off=1 sec
- * 4 | blink red on=1 sec and red off=1 sec
- * 5 | blink blue on=2.5 sec and red on=0.5 sec
- * 6 | blink blue on=1 sec and red on=1 sec
- * 7 | blink blue on=0.5 sec and blue off=2.5 sec
- *
- * data | HDD LED mode
- * -------------------------------------------------
- * 0 | fix blue on
- * 1 | SATA activity blink
- * 2 | fix red on
- * 3 | blink blue on=1 sec and blue off=1 sec
- * 4 | blink red on=1 sec and red off=1 sec
- * 5 | blink blue on=2.5 sec and red on=0.5 sec
- * 6 | blink blue on=1 sec and red on=1 sec
- * 7 | blink blue on=0.5 sec and blue off=2.5 sec
- */
-
-/*****************************************************************************
- * Timer
- ****************************************************************************/
-
-static void netxbig_v2_timer_init(void)
-{
- kirkwood_tclk = 166666667;
- orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
-
-struct sys_timer netxbig_v2_timer = {
- .init = netxbig_v2_timer_init,
-};
-
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-
-static unsigned int net2big_v2_mpp_config[] __initdata = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Request power-off */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP13_GPIO, /* Rear power switch (on|auto) */
- MPP14_GPIO, /* USB fuse alarm */
- MPP15_GPIO, /* Rear power switch (auto|off) */
- MPP16_GPIO, /* SATA HDD1 power */
- MPP17_GPIO, /* SATA HDD2 power */
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP24_GPIO, /* USB mode select */
- MPP26_GPIO, /* USB device vbus */
- MPP28_GPIO, /* USB enable host vbus */
- MPP29_GPIO, /* CPLD extension ALE */
- MPP34_GPIO, /* Rear Push button */
- MPP35_GPIO, /* Inhibit switch power-off */
- MPP36_GPIO, /* SATA HDD1 presence */
- MPP37_GPIO, /* SATA HDD2 presence */
- MPP40_GPIO, /* eSATA presence */
- MPP44_GPIO, /* CPLD extension (data 0) */
- MPP45_GPIO, /* CPLD extension (data 1) */
- MPP46_GPIO, /* CPLD extension (data 2) */
- MPP47_GPIO, /* CPLD extension (addr 0) */
- MPP48_GPIO, /* CPLD extension (addr 1) */
- MPP49_GPIO, /* CPLD extension (addr 2) */
- 0
-};
-
-static unsigned int net5big_v2_mpp_config[] __initdata = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Request power-off */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP13_GPIO, /* Rear power switch (on|auto) */
- MPP14_GPIO, /* USB fuse alarm */
- MPP15_GPIO, /* Rear power switch (auto|off) */
- MPP16_GPIO, /* SATA HDD1 power */
- MPP17_GPIO, /* SATA HDD2 power */
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO, /* USB enable host vbus */
- MPP29_GPIO, /* CPLD extension ALE */
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO, /* Rear Push button */
- MPP35_GPIO, /* Inhibit switch power-off */
- MPP36_GPIO, /* SATA HDD1 presence */
- MPP37_GPIO, /* SATA HDD2 presence */
- MPP38_GPIO, /* SATA HDD3 presence */
- MPP39_GPIO, /* SATA HDD4 presence */
- MPP40_GPIO, /* SATA HDD5 presence */
- MPP41_GPIO, /* SATA HDD3 power */
- MPP42_GPIO, /* SATA HDD4 power */
- MPP43_GPIO, /* SATA HDD5 power */
- MPP44_GPIO, /* CPLD extension (data 0) */
- MPP45_GPIO, /* CPLD extension (data 1) */
- MPP46_GPIO, /* CPLD extension (data 2) */
- MPP47_GPIO, /* CPLD extension (addr 0) */
- MPP48_GPIO, /* CPLD extension (addr 1) */
- MPP49_GPIO, /* CPLD extension (addr 2) */
- 0
-};
-
-#define NETXBIG_V2_GPIO_POWER_OFF 7
-
-static void netxbig_v2_power_off(void)
-{
- gpio_set_value(NETXBIG_V2_GPIO_POWER_OFF, 1);
-}
-
-static void __init netxbig_v2_init(void)
-{
- /*
- * Basic setup. Needs to be called early.
- */
- kirkwood_init();
- if (machine_is_net2big_v2())
- kirkwood_mpp_conf(net2big_v2_mpp_config);
- else
- kirkwood_mpp_conf(net5big_v2_mpp_config);
-
- netxbig_v2_sata_power_init();
-
- kirkwood_ehci_init();
- kirkwood_ge00_init(&netxbig_v2_ge00_data);
- if (machine_is_net5big_v2())
- kirkwood_ge01_init(&netxbig_v2_ge01_data);
- kirkwood_sata_init(&netxbig_v2_sata_data);
- kirkwood_uart0_init();
- spi_register_board_info(netxbig_v2_spi_slave_info,
- ARRAY_SIZE(netxbig_v2_spi_slave_info));
- kirkwood_spi_init();
- kirkwood_i2c_init();
- i2c_register_board_info(0, netxbig_v2_i2c_info,
- ARRAY_SIZE(netxbig_v2_i2c_info));
-
- platform_device_register(&netxbig_v2_gpio_buttons);
-
- if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
- gpio_direction_output(NETXBIG_V2_GPIO_POWER_OFF, 0) == 0)
- pm_power_off = netxbig_v2_power_off;
- else
- pr_err("netxbig_v2: failed to configure power-off GPIO\n");
-}
-
-#ifdef CONFIG_MACH_NET2BIG_V2
-MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
- .phys_io = KIRKWOOD_REGS_PHYS_BASE,
- .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
- .boot_params = 0x00000100,
- .init_machine = netxbig_v2_init,
- .map_io = kirkwood_map_io,
- .init_irq = kirkwood_init_irq,
- .timer = &netxbig_v2_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_NET5BIG_V2
-MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
- .phys_io = KIRKWOOD_REGS_PHYS_BASE,
- .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
- .boot_params = 0x00000100,
- .init_machine = netxbig_v2_init,
- .map_io = kirkwood_map_io,
- .init_irq = kirkwood_init_irq,
- .timer = &netxbig_v2_timer,
-MACHINE_END
-#endif
diff --git a/trunk/arch/arm/mach-mmp/aspenite.c b/trunk/arch/arm/mach-mmp/aspenite.c
index 244655d323ea..a2d307ec0420 100644
--- a/trunk/arch/arm/mach-mmp/aspenite.c
+++ b/trunk/arch/arm/mach-mmp/aspenite.c
@@ -59,13 +59,6 @@ static unsigned long common_pin_config[] __initdata = {
/* UART1 */
GPIO107_UART1_RXD,
GPIO108_UART1_TXD,
-
- /* SSP1 */
- GPIO113_I2S_MCLK,
- GPIO114_I2S_FRM,
- GPIO115_I2S_BCLK,
- GPIO116_I2S_RXD,
- GPIO117_I2S_TXD,
};
static struct smc91x_platdata smc91x_info = {
@@ -130,18 +123,12 @@ static struct pxa3xx_nand_platform_data aspenite_nand_info = {
.nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
};
-static struct i2c_board_info aspenite_i2c_info[] __initdata = {
- { I2C_BOARD_INFO("wm8753", 0x1b), },
-};
-
static void __init common_init(void)
{
mfp_config(ARRAY_AND_SIZE(common_pin_config));
/* on-chip devices */
pxa168_add_uart(1);
- pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
- pxa168_add_ssp(1);
pxa168_add_nand(&aspenite_nand_info);
/* off-chip devices */
diff --git a/trunk/arch/arm/mach-mmp/include/mach/gpio.h b/trunk/arch/arm/mach-mmp/include/mach/gpio.h
index ee8b02ed8011..ab26d13295c4 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
-#define NR_BUILTIN_GPIO (192)
+#define NR_BUILTIN_GPIO (128)
#define gpio_to_bank(gpio) ((gpio) >> 5)
#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio))
diff --git a/trunk/arch/arm/mach-mmp/include/mach/irqs.h b/trunk/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d38..02701196ea03 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/irqs.h
@@ -5,10 +5,10 @@
* Interrupt numbers for PXA168
*/
#define IRQ_PXA168_NONE (-1)
-#define IRQ_PXA168_SSP4 0
-#define IRQ_PXA168_SSP3 1
-#define IRQ_PXA168_SSP2 2
-#define IRQ_PXA168_SSP1 3
+#define IRQ_PXA168_SSP3 0
+#define IRQ_PXA168_SSP2 1
+#define IRQ_PXA168_SSP1 2
+#define IRQ_PXA168_SSP0 3
#define IRQ_PXA168_PMIC_INT 4
#define IRQ_PXA168_RTC_INT 5
#define IRQ_PXA168_RTC_ALARM 6
@@ -20,7 +20,7 @@
#define IRQ_PXA168_TIMER2 14
#define IRQ_PXA168_TIMER3 15
#define IRQ_PXA168_CMU 16
-#define IRQ_PXA168_SSP5 17
+#define IRQ_PXA168_SSP4 17
#define IRQ_PXA168_MSP_WAKEUP 19
#define IRQ_PXA168_CF_WAKEUP 20
#define IRQ_PXA168_XD_WAKEUP 21
diff --git a/trunk/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/trunk/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 761c2dacc079..9f9f8143e272 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -9,175 +9,6 @@
#define MFP_DRIVE_FAST (0x8 << 13)
/* GPIO */
-#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0)
-#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0)
-#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0)
-#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0)
-#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1)
-#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1)
-#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1)
-#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1)
-#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1)
-#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1)
-#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1)
-#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1)
-#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1)
-#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1)
-#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1)
-#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1)
-#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0)
-#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0)
-#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0)
-#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0)
-#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0)
-#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0)
-#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0)
-#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0)
-#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0)
-#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0)
-#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0)
-#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0)
-#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0)
-#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0)
-#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0)
-#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1)
-#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1)
-#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1)
-#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1)
-#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1)
-#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1)
-#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1)
-#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1)
-#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1)
-#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1)
-#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1)
-#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1)
-#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1)
-#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1)
-#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1)
-#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1)
-#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1)
-#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1)
-#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1)
-#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1)
-#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1)
-#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1)
-#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1)
-#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1)
-#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1)
-#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1)
-#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1)
/* DFI */
#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
@@ -216,6 +47,7 @@
/* Ethernet */
#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2)
+#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1)
/* UART1 */
#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1)
@@ -327,8 +159,6 @@
#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW)
#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW)
#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW)
-#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW)
-#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW)
#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW)
#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW)
#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW)
@@ -388,6 +218,21 @@
#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST)
#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST)
+/* Wifi */
+#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0)
+#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0)
+#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0)
+
+/* Codec*/
+#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0)
+
+#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0)
+
/* PMIC */
#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0)
diff --git a/trunk/arch/arm/mach-mmp/include/mach/mmp2.h b/trunk/arch/arm/mach-mmp/include/mach/mmp2.h
index fec220bd5046..459f3be9cfb2 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -39,17 +39,17 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
int ret;
switch (id) {
- case 1: d = &mmp2_device_twsi1; break;
- case 2: d = &mmp2_device_twsi2; break;
- case 3: d = &mmp2_device_twsi3; break;
- case 4: d = &mmp2_device_twsi4; break;
- case 5: d = &mmp2_device_twsi5; break;
- case 6: d = &mmp2_device_twsi6; break;
+ case 0: d = &mmp2_device_twsi1; break;
+ case 1: d = &mmp2_device_twsi2; break;
+ case 2: d = &mmp2_device_twsi3; break;
+ case 3: d = &mmp2_device_twsi4; break;
+ case 4: d = &mmp2_device_twsi5; break;
+ case 5: d = &mmp2_device_twsi6; break;
default:
return -EINVAL;
}
- ret = i2c_register_board_info(id - 1, info, size);
+ ret = i2c_register_board_info(id, info, size);
if (ret)
return ret;
diff --git a/trunk/arch/arm/mach-mmp/include/mach/pxa168.h b/trunk/arch/arm/mach-mmp/include/mach/pxa168.h
index 3b2bd5d5eb05..3ad612cbdf09 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,11 +14,6 @@ extern struct pxa_device_desc pxa168_device_pwm1;
extern struct pxa_device_desc pxa168_device_pwm2;
extern struct pxa_device_desc pxa168_device_pwm3;
extern struct pxa_device_desc pxa168_device_pwm4;
-extern struct pxa_device_desc pxa168_device_ssp1;
-extern struct pxa_device_desc pxa168_device_ssp2;
-extern struct pxa_device_desc pxa168_device_ssp3;
-extern struct pxa_device_desc pxa168_device_ssp4;
-extern struct pxa_device_desc pxa168_device_ssp5;
extern struct pxa_device_desc pxa168_device_nand;
static inline int pxa168_add_uart(int id)
@@ -72,22 +67,6 @@ static inline int pxa168_add_pwm(int id)
return pxa_register_device(d, NULL, 0);
}
-static inline int pxa168_add_ssp(int id)
-{
- struct pxa_device_desc *d = NULL;
-
- switch (id) {
- case 1: d = &pxa168_device_ssp1; break;
- case 2: d = &pxa168_device_ssp2; break;
- case 3: d = &pxa168_device_ssp3; break;
- case 4: d = &pxa168_device_ssp4; break;
- case 5: d = &pxa168_device_ssp5; break;
- default:
- return -EINVAL;
- }
- return pxa_register_device(d, NULL, 0);
-}
-
static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
{
return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 1a96585336ba..712af03fd1af 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -26,6 +26,8 @@
#define APBC_PXA168_PWM2 APBC_REG(0x010)
#define APBC_PXA168_PWM3 APBC_REG(0x014)
#define APBC_PXA168_PWM4 APBC_REG(0x018)
+#define APBC_PXA168_SSP1 APBC_REG(0x01c)
+#define APBC_PXA168_SSP2 APBC_REG(0x020)
#define APBC_PXA168_RTC APBC_REG(0x028)
#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
#define APBC_PXA168_KPC APBC_REG(0x030)
@@ -33,16 +35,14 @@
#define APBC_PXA168_AIB APBC_REG(0x03c)
#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
+#define APBC_PXA168_SSP3 APBC_REG(0x04c)
#define APBC_PXA168_ASFAR APBC_REG(0x050)
#define APBC_PXA168_ASSAR APBC_REG(0x054)
+#define APBC_PXA168_SSP4 APBC_REG(0x058)
+#define APBC_PXA168_SSP5 APBC_REG(0x05c)
#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
#define APBC_PXA168_UART3 APBC_REG(0x070)
#define APBC_PXA168_AC97 APBC_REG(0x084)
-#define APBC_PXA168_SSP1 APBC_REG(0x81c)
-#define APBC_PXA168_SSP2 APBC_REG(0x820)
-#define APBC_PXA168_SSP3 APBC_REG(0x84c)
-#define APBC_PXA168_SSP4 APBC_REG(0x858)
-#define APBC_PXA168_SSP5 APBC_REG(0x85c)
/*
* APB Clock register offsets for PXA910
diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-smc.h b/trunk/arch/arm/mach-mmp/include/mach/regs-smc.h
deleted file mode 100644
index e484d40d71bd..000000000000
--- a/trunk/arch/arm/mach-mmp/include/mach/regs-smc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/regs-smc.h
- *
- * Static Memory Controller Registers
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_REGS_SMC_H
-#define __ASM_MACH_REGS_SMC_H
-
-#include
-
-#define SMC_VIRT_BASE (AXI_VIRT_BASE + 0x83800)
-#define SMC_REG(x) (SMC_VIRT_BASE + (x))
-
-#define SMC_MSC0 SMC_REG(0x0020)
-#define SMC_MSC1 SMC_REG(0x0024)
-#define SMC_SXCNFG0 SMC_REG(0x0030)
-#define SMC_SXCNFG1 SMC_REG(0x0034)
-#define SMC_MEMCLKCFG SMC_REG(0x0068)
-#define SMC_CSDFICFG0 SMC_REG(0x0090)
-#define SMC_CSDFICFG1 SMC_REG(0x0094)
-#define SMC_CLK_RET_DEL SMC_REG(0x00b0)
-#define SMC_ADV_RET_DEL SMC_REG(0x00b4)
-#define SMC_CSADRMAP0 SMC_REG(0x00c0)
-#define SMC_CSADRMAP1 SMC_REG(0x00c4)
-#define SMC_WE_AP0 SMC_REG(0x00e0)
-#define SMC_WE_AP1 SMC_REG(0x00e4)
-#define SMC_OE_AP0 SMC_REG(0x00f0)
-#define SMC_OE_AP1 SMC_REG(0x00f4)
-#define SMC_ADV_AP0 SMC_REG(0x0100)
-#define SMC_ADV_AP1 SMC_REG(0x0104)
-
-#endif /* __ASM_MACH_REGS_SMC_H */
diff --git a/trunk/arch/arm/mach-mmp/include/mach/timex.h b/trunk/arch/arm/mach-mmp/include/mach/timex.h
index 70c9f1d88c02..6cebbd0ca8f4 100644
--- a/trunk/arch/arm/mach-mmp/include/mach/timex.h
+++ b/trunk/arch/arm/mach-mmp/include/mach/timex.h
@@ -6,8 +6,4 @@
* published by the Free Software Foundation.
*/
-#ifdef CONFIG_CPU_MMP2
-#define CLOCK_TICK_RATE 6500000
-#else
#define CLOCK_TICK_RATE 3250000
-#endif
diff --git a/trunk/arch/arm/mach-mmp/jasper.c b/trunk/arch/arm/mach-mmp/jasper.c
index d77dd41d60e1..cfd4d66ef800 100644
--- a/trunk/arch/arm/mach-mmp/jasper.c
+++ b/trunk/arch/arm/mach-mmp/jasper.c
@@ -15,16 +15,12 @@
#include
#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
-#include
#include "common.h"
@@ -62,63 +58,6 @@ static unsigned long jasper_pin_config[] __initdata = {
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
-
- /* PMIC */
- PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
-};
-
-static struct regulator_consumer_supply max8649_supply[] = {
- REGULATOR_SUPPLY("vcc_core", NULL),
-};
-
-static struct regulator_init_data max8649_init_data = {
- .constraints = {
- .name = "vcc_core range",
- .min_uV = 1150000,
- .max_uV = 1280000,
- .always_on = 1,
- .boot_on = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &max8649_supply[0],
-};
-
-static struct max8649_platform_data jasper_max8649_info = {
- .mode = 2, /* VID1 = 1, VID0 = 0 */
- .extclk = 0,
- .ramp_timing = MAX8649_RAMP_32MV,
- .regulator = &max8649_init_data,
-};
-
-static struct max8925_backlight_pdata jasper_backlight_data = {
- .dual_string = 0,
-};
-
-static struct max8925_power_pdata jasper_power_data = {
- .batt_detect = 0, /* can't detect battery by ID pin */
- .topoff_threshold = MAX8925_TOPOFF_THR_10PER,
- .fast_charge = MAX8925_FCHG_1000MA,
-};
-
-static struct max8925_platform_data jasper_max8925_info = {
- .backlight = &jasper_backlight_data,
- .power = &jasper_power_data,
- .irq_base = IRQ_BOARD_START,
-};
-
-static struct i2c_board_info jasper_twsi1_info[] = {
- [0] = {
- .type = "max8649",
- .addr = 0x60,
- .platform_data = &jasper_max8649_info,
- },
- [1] = {
- .type = "max8925",
- .addr = 0x3c,
- .irq = IRQ_MMP2_PMIC,
- .platform_data = &jasper_max8925_info,
- },
};
static void __init jasper_init(void)
@@ -128,9 +67,6 @@ static void __init jasper_init(void)
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(3);
- mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
-
- regulator_has_full_constraints();
}
MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
diff --git a/trunk/arch/arm/mach-mmp/mmp2.c b/trunk/arch/arm/mach-mmp/mmp2.c
index 7f5eb059bb01..72eb9daeea99 100644
--- a/trunk/arch/arm/mach-mmp/mmp2.c
+++ b/trunk/arch/arm/mach-mmp/mmp2.c
@@ -15,14 +15,11 @@
#include
#include
-#include
-
#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -35,50 +32,7 @@
#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
static struct mfp_addr_map mmp2_addr_map[] __initdata = {
-
- MFP_ADDR_X(GPIO0, GPIO58, 0x54),
- MFP_ADDR_X(GPIO59, GPIO73, 0x280),
- MFP_ADDR_X(GPIO74, GPIO101, 0x170),
-
- MFP_ADDR(GPIO102, 0x0),
- MFP_ADDR(GPIO103, 0x4),
- MFP_ADDR(GPIO104, 0x1fc),
- MFP_ADDR(GPIO105, 0x1f8),
- MFP_ADDR(GPIO106, 0x1f4),
- MFP_ADDR(GPIO107, 0x1f0),
- MFP_ADDR(GPIO108, 0x21c),
- MFP_ADDR(GPIO109, 0x218),
- MFP_ADDR(GPIO110, 0x214),
- MFP_ADDR(GPIO111, 0x200),
- MFP_ADDR(GPIO112, 0x244),
- MFP_ADDR(GPIO113, 0x25c),
- MFP_ADDR(GPIO114, 0x164),
- MFP_ADDR_X(GPIO115, GPIO122, 0x260),
-
- MFP_ADDR(GPIO123, 0x148),
- MFP_ADDR_X(GPIO124, GPIO141, 0xc),
-
- MFP_ADDR(GPIO142, 0x8),
- MFP_ADDR_X(GPIO143, GPIO151, 0x220),
- MFP_ADDR_X(GPIO152, GPIO153, 0x248),
- MFP_ADDR_X(GPIO154, GPIO155, 0x254),
- MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
-
- MFP_ADDR(GPIO160, 0x250),
- MFP_ADDR(GPIO161, 0x210),
- MFP_ADDR(GPIO162, 0x20c),
- MFP_ADDR(GPIO163, 0x208),
- MFP_ADDR(GPIO164, 0x204),
- MFP_ADDR(GPIO165, 0x1ec),
- MFP_ADDR(GPIO166, 0x1e8),
- MFP_ADDR(GPIO167, 0x1e4),
- MFP_ADDR(GPIO168, 0x1e0),
-
- MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
- MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
-
MFP_ADDR(PMIC_INT, 0x2c4),
- MFP_ADDR(CLK_REQ, 0x160),
MFP_ADDR_END,
};
@@ -145,13 +99,9 @@ static struct clk_lookup mmp2_clkregs[] = {
static int __init mmp2_init(void)
{
if (cpu_is_mmp2()) {
-#ifdef CONFIG_CACHE_TAUROS2
- tauros2_init();
-#endif
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(mmp2_addr_map);
- pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
- clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+ clks_register(ARRAY_AND_SIZE(mmp2_clkregs));
}
return 0;
diff --git a/trunk/arch/arm/mach-mmp/pxa168.c b/trunk/arch/arm/mach-mmp/pxa168.c
index 652ae660634c..1873c821df90 100644
--- a/trunk/arch/arm/mach-mmp/pxa168.c
+++ b/trunk/arch/arm/mach-mmp/pxa168.c
@@ -72,11 +72,6 @@ static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APMU_CLK(nand, NAND, 0x01db, 208000000);
@@ -90,11 +85,6 @@ static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
- INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
- INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
- INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
- INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
- INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
};
@@ -142,8 +132,3 @@ PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
-PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53);
-PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
-PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
-PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
-PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
diff --git a/trunk/arch/arm/mach-msm/Kconfig b/trunk/arch/arm/mach-msm/Kconfig
index b9fd5c528e5b..f780086befd7 100644
--- a/trunk/arch/arm/mach-msm/Kconfig
+++ b/trunk/arch/arm/mach-msm/Kconfig
@@ -29,14 +29,12 @@ endchoice
config MACH_HALIBUT
depends on ARCH_MSM
- select CPU_V6
default y
bool "Halibut Board (QCT SURF7201A)"
help
Support for the Qualcomm SURF7201A eval board.
config MACH_TROUT
- select CPU_V6
default y
bool "HTC Dream (aka trout)"
help
diff --git a/trunk/arch/arm/mach-mx5/clock-mx51.c b/trunk/arch/arm/mach-mx5/clock-mx51.c
index 1ee6ce4087b8..8f85f73b83a8 100644
--- a/trunk/arch/arm/mach-mx5/clock-mx51.c
+++ b/trunk/arch/arm/mach-mx5/clock-mx51.c
@@ -16,7 +16,6 @@
#include
#include
-#include
#include
#include
diff --git a/trunk/arch/arm/mach-orion5x/dns323-setup.c b/trunk/arch/arm/mach-orion5x/dns323-setup.c
index 685f34a9634b..421b82f7c63d 100644
--- a/trunk/arch/arm/mach-orion5x/dns323-setup.c
+++ b/trunk/arch/arm/mach-orion5x/dns323-setup.c
@@ -439,7 +439,6 @@ static void __init dns323_init(void)
*/
if (dns323_dev_id() == MV88F5181_DEV_ID) {
dns323_leds[0].active_low = 1;
- gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
}
diff --git a/trunk/arch/arm/mach-pxa/Kconfig b/trunk/arch/arm/mach-pxa/Kconfig
index 3b51741a4810..5b6ee46fa7f6 100644
--- a/trunk/arch/arm/mach-pxa/Kconfig
+++ b/trunk/arch/arm/mach-pxa/Kconfig
@@ -19,6 +19,7 @@ config MACH_MAINSTONE
config MACH_ZYLONITE
bool
select PXA3xx
+ select PXA_SSP
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
@@ -38,6 +39,7 @@ config MACH_LITTLETON
select PXA3xx
select CPU_PXA300
select CPU_PXA310
+ select PXA_SSP
config MACH_TAVOREVB
bool "PXA930 Evaluation Board (aka TavorEVB)"
@@ -96,6 +98,7 @@ config MACH_ARMCORE
select PXA27x
select IWMMXT
select PXA25x
+ select PXA_SSP
config MACH_EM_X270
bool "CompuLab EM-x270 platform"
@@ -158,6 +161,7 @@ config MACH_XCEP
select MTD_CFI
select MTD_CHAR
select SMC91X
+ select PXA_SSP
help
PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
Tuned for usage in Libera instruments for particle accelerators.
@@ -176,6 +180,7 @@ config MACH_TRIZEPS4WL
depends on TRIZEPS_PXA
select TRIZEPS_PCMCIA
select PXA27x
+ select PXA_SSP
choice
prompt "Select base board for Trizeps module"
@@ -212,6 +217,7 @@ config MACH_PCM027
bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
select PXA27x
select IWMMXT
+ select PXA_SSP
select PXA_HAVE_BOARD_IRQS
config MACH_PCM990_BASEBOARD
@@ -249,19 +255,13 @@ config MACH_COLIBRI320
select PXA3xx
select CPU_PXA320
-config MACH_VPAC270
- bool "Voipac PXA270"
- select PXA27x
- select HAVE_PATA_PLATFORM
- help
- PXA270 based Single Board Computer.
-
comment "End-user Products (sorted by vendor name)"
config MACH_H4700
bool "HP iPAQ hx4700"
select PXA27x
select IWMMXT
+ select PXA_SSP
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
@@ -277,6 +277,7 @@ config MACH_MAGICIAN
bool "Enable HTC Magician Support"
select PXA27x
select IWMMXT
+ select PXA_SSP
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
@@ -430,11 +431,13 @@ config MACH_RAUMFELD_CONNECTOR
bool "Raumfeld Connector"
select PXA3xx
select CPU_PXA300
+ select PXA_SSP
config MACH_RAUMFELD_SPEAKER
bool "Raumfeld Speaker"
select PXA3xx
select CPU_PXA300
+ select PXA_SSP
config PXA_SHARPSL
bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
@@ -458,11 +461,21 @@ config SHARPSL_PM_MAX1111
select HWMON
select SENSORS_MAX1111
+config CORGI_SSP_DEPRECATED
+ bool
+ select PXA_SSP
+ select PXA_SSP_LEGACY
+ help
+ This option will include corgi_ssp.c and corgi_lcd.c
+ that corgi_ts.c and other legacy drivers (corgi_bl.c
+ and sharpsl_pm.c) may depend on.
+
config MACH_POODLE
bool "Enable Sharp SL-5600 (Poodle) Support"
depends on PXA_SHARPSL
select PXA25x
select SHARP_LOCOMO
+ select PXA_SSP
select PXA_HAVE_BOARD_IRQS
config MACH_CORGI
@@ -568,12 +581,6 @@ config MACH_E800
Say Y here if you intend to run this kernel on a Toshiba
e800 family PDA.
-config MACH_ZIPIT2
- bool "Zipit Z2 Handheld"
- select PXA27x
- select HAVE_PWM
- select PXA_HAVE_BOARD_IRQS
-
endmenu
config PXA25x
@@ -638,16 +645,28 @@ config CPU_PXA950
config PXA_SHARP_C7xx
bool
+ select PXA_SSP
select SHARPSL_PM
help
Enable support for all Sharp C7xx models
config PXA_SHARP_Cxx00
bool
+ select PXA_SSP
select SHARPSL_PM
help
Enable common support for Sharp Cxx00 models
+config PXA_SSP
+ tristate
+ help
+ Enable support for PXA2xx SSP ports
+
+config PXA_SSP_LEGACY
+ bool
+ help
+ Support of legacy SSP API
+
config TOSA_BT
tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
depends on MACH_TOSA
@@ -656,18 +675,6 @@ config TOSA_BT
This is a simple driver that is able to control
the state of built in bluetooth chip on tosa.
-config TOSA_USE_EXT_KEYCODES
- bool "Tosa keyboard: use extended keycodes"
- depends on MACH_TOSA
- default n
- help
- Say Y here to enable the tosa keyboard driver to generate extended
- (>= 127) keycodes. Be aware, that they can't be correctly interpreted
- by either console keyboard driver or by Kdrive keybd driver.
-
- Say Y only if you know, what you are doing!
-
-
config PXA_HAVE_BOARD_IRQS
bool
diff --git a/trunk/arch/arm/mach-pxa/Makefile b/trunk/arch/arm/mach-pxa/Makefile
index b8f1f4bc7ca7..86bc87b7f2dd 100644
--- a/trunk/arch/arm/mach-pxa/Makefile
+++ b/trunk/arch/arm/mach-pxa/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o
endif
# Generic drivers that other drivers may depend upon
+obj-$(CONFIG_PXA_SSP) += ssp.o
# SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
@@ -61,7 +62,6 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o
obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o
obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o
-obj-$(CONFIG_MACH_VPAC270) += vpac270.o
# End-user Products
obj-$(CONFIG_MACH_H4700) += hx4700.o
@@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_PALMLD) += palmld.o
obj-$(CONFIG_PALM_TREO) += palmtreo.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
+obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o
obj-$(CONFIG_MACH_POODLE) += poodle.o
obj-$(CONFIG_MACH_TOSA) += tosa.o
obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o
@@ -93,7 +94,6 @@ obj-$(CONFIG_MACH_E800) += e800.o
obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o
obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o
obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o
-obj-$(CONFIG_MACH_ZIPIT2) += z2.o
# Support for blinky lights
led-y := leds.o
diff --git a/trunk/arch/arm/mach-pxa/cm-x300.c b/trunk/arch/arm/mach-pxa/cm-x300.c
index fdda6be6c391..d37cfa132a65 100644
--- a/trunk/arch/arm/mach-pxa/cm-x300.c
+++ b/trunk/arch/arm/mach-pxa/cm-x300.c
@@ -30,9 +30,6 @@
#include
#include
-#include
-#include
-#include
#include
#include
@@ -433,7 +430,7 @@ static inline void cm_x300_init_nand(void) {}
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
static struct pxamci_platform_data cm_x300_mci_platform_data = {
- .detect_delay_ms = 200,
+ .detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = GPIO82_MMC_IRQ,
.gpio_card_ro = GPIO85_MMC_WP,
@@ -454,7 +451,7 @@ static void cm_x300_mci2_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data cm_x300_mci2_platform_data = {
- .detect_delay_ms = 200,
+ .detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci2_init,
.exit = cm_x300_mci2_exit,
@@ -587,87 +584,12 @@ static void __init cm_x300_init_rtc(void)
static inline void cm_x300_init_rtc(void) {}
#endif
-/* Battery */
-struct power_supply_info cm_x300_psy_info = {
- .name = "battery",
- .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .voltage_max_design = 4200000,
- .voltage_min_design = 3000000,
- .use_for_apm = 1,
-};
-
-static void cm_x300_battery_low(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_LOW_BATTERY);
-#endif
-}
-
-static void cm_x300_battery_critical(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_CRITICAL_SUSPEND);
-#endif
-}
-
-struct da9030_battery_info cm_x300_battery_info = {
- .battery_info = &cm_x300_psy_info,
-
- .charge_milliamp = 1000,
- .charge_millivolt = 4200,
-
- .vbat_low = 3600,
- .vbat_crit = 3400,
- .vbat_charge_start = 4100,
- .vbat_charge_stop = 4200,
- .vbat_charge_restart = 4000,
-
- .vcharge_min = 3200,
- .vcharge_max = 5500,
-
- .tbat_low = 197,
- .tbat_high = 78,
- .tbat_restart = 100,
-
- .batmon_interval = 0,
-
- .battery_low = cm_x300_battery_low,
- .battery_critical = cm_x300_battery_critical,
-};
-
-static struct regulator_consumer_supply buck2_consumers[] = {
- {
- .dev = NULL,
- .supply = "vcc_core",
- },
-};
-
-static struct regulator_init_data buck2_data = {
- .constraints = {
- .min_uV = 1375000,
- .max_uV = 1375000,
- .state_mem = {
- .enabled = 0,
- },
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- .apply_uV = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(buck2_consumers),
- .consumer_supplies = buck2_consumers,
-};
-
/* DA9030 */
struct da903x_subdev_info cm_x300_da9030_subdevs[] = {
{
- .name = "da903x-battery",
- .id = DA9030_ID_BAT,
- .platform_data = &cm_x300_battery_info,
- },
- {
- .name = "da903x-regulator",
- .id = DA9030_ID_BUCK2,
- .platform_data = &buck2_data,
- },
+ .name = "da903x-backlight",
+ .id = DA9030_ID_WLED,
+ }
};
static struct da903x_platform_data cm_x300_da9030_info = {
@@ -677,7 +599,7 @@ static struct da903x_platform_data cm_x300_da9030_info = {
static struct i2c_board_info cm_x300_pmic_info = {
I2C_BOARD_INFO("da9030", 0x49),
- .irq = IRQ_WAKEUP0,
+ .irq = IRQ_GPIO(0),
.platform_data = &cm_x300_da9030_info,
};
@@ -767,13 +689,13 @@ static void __init cm_x300_init(void)
static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
char **cmdline, struct meminfo *mi)
{
- /* Make sure that mi->bank[0].start = PHYS_ADDR */
- for (; tags->hdr.size; tags = tag_next(tags))
- if (tags->hdr.tag == ATAG_MEM &&
- tags->u.mem.start == 0x80000000) {
- tags->u.mem.start = 0xa0000000;
- break;
- }
+ mi->nr_banks = 2;
+ mi->bank[0].start = 0xa0000000;
+ mi->bank[0].node = 0;
+ mi->bank[0].size = (64*1024*1024);
+ mi->bank[1].start = 0xc0000000;
+ mi->bank[1].node = 0;
+ mi->bank[1].size = (64*1024*1024);
}
MACHINE_START(CM_X300, "CM-X300 module")
diff --git a/trunk/arch/arm/mach-pxa/colibri-pxa3xx.c b/trunk/arch/arm/mach-pxa/colibri-pxa3xx.c
index 199afa2ae303..e6c0a2287eb8 100644
--- a/trunk/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/trunk/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -96,7 +96,7 @@ static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
- .detect_delay_ms = 200,
+ .detect_delay = 20,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = colibri_pxa3xx_mci_init,
.exit = colibri_pxa3xx_mci_exit,
diff --git a/trunk/arch/arm/mach-pxa/corgi.c b/trunk/arch/arm/mach-pxa/corgi.c
index 3d1dcb9ac08f..da3156d8690b 100644
--- a/trunk/arch/arm/mach-pxa/corgi.c
+++ b/trunk/arch/arm/mach-pxa/corgi.c
@@ -106,18 +106,18 @@ static unsigned long corgi_pin_config[] __initdata = {
GPIO8_MMC_CS0,
/* GPIO Matrix Keypad */
- GPIO66_GPIO | MFP_LPM_DRIVE_HIGH, /* column 0 */
- GPIO67_GPIO | MFP_LPM_DRIVE_HIGH, /* column 1 */
- GPIO68_GPIO | MFP_LPM_DRIVE_HIGH, /* column 2 */
- GPIO69_GPIO | MFP_LPM_DRIVE_HIGH, /* column 3 */
- GPIO70_GPIO | MFP_LPM_DRIVE_HIGH, /* column 4 */
- GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, /* column 5 */
- GPIO72_GPIO | MFP_LPM_DRIVE_HIGH, /* column 6 */
- GPIO73_GPIO | MFP_LPM_DRIVE_HIGH, /* column 7 */
- GPIO74_GPIO | MFP_LPM_DRIVE_HIGH, /* column 8 */
- GPIO75_GPIO | MFP_LPM_DRIVE_HIGH, /* column 9 */
- GPIO76_GPIO | MFP_LPM_DRIVE_HIGH, /* column 10 */
- GPIO77_GPIO | MFP_LPM_DRIVE_HIGH, /* column 11 */
+ GPIO66_GPIO, /* column 0 */
+ GPIO67_GPIO, /* column 1 */
+ GPIO68_GPIO, /* column 2 */
+ GPIO69_GPIO, /* column 3 */
+ GPIO70_GPIO, /* column 4 */
+ GPIO71_GPIO, /* column 5 */
+ GPIO72_GPIO, /* column 6 */
+ GPIO73_GPIO, /* column 7 */
+ GPIO74_GPIO, /* column 8 */
+ GPIO75_GPIO, /* column 9 */
+ GPIO76_GPIO, /* column 10 */
+ GPIO77_GPIO, /* column 11 */
GPIO58_GPIO, /* row 0 */
GPIO59_GPIO, /* row 1 */
GPIO60_GPIO, /* row 2 */
@@ -128,20 +128,13 @@ static unsigned long corgi_pin_config[] __initdata = {
GPIO65_GPIO, /* row 7 */
/* GPIO */
- GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */
- GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */
- GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_MAIN_BAT_{LOW,COVER} */
- GPIO13_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_LED_ORANGE */
- GPIO21_GPIO, /* CORGI_GPIO_ADC_TEMP */
- GPIO22_GPIO, /* CORGI_GPIO_IR_ON */
- GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */
- GPIO38_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_ON */
- GPIO43_GPIO | MFP_LPM_KEEP_OUTPUT, /* CORGI_GPIO_CHRG_UKN */
- GPIO44_GPIO, /* CORGI_GPIO_HSYNC */
-
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_KEY_INT */
- GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, /* CORGI_GPIO_AC_IN */
- GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH, /* CORGI_GPIO_WAKEUP */
+ GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */
+ GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */
+ GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */
+ GPIO22_GPIO, /* CORGI_GPIO_IR_ON */
+ GPIO44_GPIO, /* CORGI_GPIO_HSYNC */
+
+ GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
};
/*
@@ -444,7 +437,6 @@ static struct platform_device corgiled_device = {
* to give the card a chance to fully insert/eject.
*/
static struct pxamci_platform_data corgi_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = -1,
.gpio_card_ro = CORGI_GPIO_nSD_WP,
@@ -680,15 +672,6 @@ static void __init corgi_init(void)
pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
- /* allow wakeup from various GPIOs */
- gpio_set_wake(CORGI_GPIO_KEY_INT, 1);
- gpio_set_wake(CORGI_GPIO_WAKEUP, 1);
- gpio_set_wake(CORGI_GPIO_AC_IN, 1);
- gpio_set_wake(CORGI_GPIO_CHRG_FULL, 1);
-
- if (!machine_is_corgi())
- gpio_set_wake(CORGI_GPIO_MAIN_BAT_LOW, 1);
-
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
@@ -696,6 +679,7 @@ static void __init corgi_init(void)
corgi_init_spi();
pxa_set_udc_info(&udc_info);
+ corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&corgi_mci_platform_data);
pxa_set_ficp_info(&corgi_ficp_platform_data);
pxa_set_i2c_info(NULL);
diff --git a/trunk/arch/arm/mach-pxa/corgi_lcd.c b/trunk/arch/arm/mach-pxa/corgi_lcd.c
new file mode 100644
index 000000000000..d9b96319d498
--- /dev/null
+++ b/trunk/arch/arm/mach-pxa/corgi_lcd.c
@@ -0,0 +1,288 @@
+/*
+ * linux/arch/arm/mach-pxa/corgi_lcd.c
+ *
+ * Corgi/Spitz LCD Specific Code
+ *
+ * Copyright (C) 2005 Richard Purdie
+ *
+ * Connectivity:
+ * Corgi - LCD to ATI Imageon w100 (Wallaby)
+ * Spitz - LCD to PXA Framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "generic.h"
+
+/* Register Addresses */
+#define RESCTL_ADRS 0x00
+#define PHACTRL_ADRS 0x01
+#define DUTYCTRL_ADRS 0x02
+#define POWERREG0_ADRS 0x03
+#define POWERREG1_ADRS 0x04
+#define GPOR3_ADRS 0x05
+#define PICTRL_ADRS 0x06
+#define POLCTRL_ADRS 0x07
+
+/* Register Bit Definitions */
+#define RESCTL_QVGA 0x01
+#define RESCTL_VGA 0x00
+
+#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
+#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
+#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
+
+#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
+#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
+#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
+
+#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
+#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
+#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
+#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
+#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
+
+#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
+#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
+#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
+
+#define PICTRL_INIT_STATE 0x01
+#define PICTRL_INIOFF 0x02
+#define PICTRL_POWER_DOWN 0x04
+#define PICTRL_COM_SIGNAL_OFF 0x08
+#define PICTRL_DAC_SIGNAL_OFF 0x10
+
+#define POLCTRL_SYNC_POL_FALL 0x01
+#define POLCTRL_EN_POL_FALL 0x02
+#define POLCTRL_DATA_POL_FALL 0x04
+#define POLCTRL_SYNC_ACT_H 0x08
+#define POLCTRL_EN_ACT_L 0x10
+
+#define POLCTRL_SYNC_POL_RISE 0x00
+#define POLCTRL_EN_POL_RISE 0x00
+#define POLCTRL_DATA_POL_RISE 0x00
+#define POLCTRL_SYNC_ACT_L 0x00
+#define POLCTRL_EN_ACT_H 0x00
+
+#define PHACTRL_PHASE_MANUAL 0x01
+#define DEFAULT_PHAD_QVGA (9)
+#define DEFAULT_COMADJ (125)
+
+/*
+ * This is only a psuedo I2C interface. We can't use the standard kernel
+ * routines as the interface is write only. We just assume the data is acked...
+ */
+static void lcdtg_ssp_i2c_send(u8 data)
+{
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
+ udelay(10);
+}
+
+static void lcdtg_i2c_send_bit(u8 data)
+{
+ lcdtg_ssp_i2c_send(data);
+ lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
+ lcdtg_ssp_i2c_send(data);
+}
+
+static void lcdtg_i2c_send_start(u8 base)
+{
+ lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
+ lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
+ lcdtg_ssp_i2c_send(base);
+}
+
+static void lcdtg_i2c_send_stop(u8 base)
+{
+ lcdtg_ssp_i2c_send(base);
+ lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
+ lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
+}
+
+static void lcdtg_i2c_send_byte(u8 base, u8 data)
+{
+ int i;
+ for (i = 0; i < 8; i++) {
+ if (data & 0x80)
+ lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
+ else
+ lcdtg_i2c_send_bit(base);
+ data <<= 1;
+ }
+}
+
+static void lcdtg_i2c_wait_ack(u8 base)
+{
+ lcdtg_i2c_send_bit(base);
+}
+
+static void lcdtg_set_common_voltage(u8 base_data, u8 data)
+{
+ /* Set Common Voltage to M62332FP via I2C */
+ lcdtg_i2c_send_start(base_data);
+ lcdtg_i2c_send_byte(base_data, 0x9c);
+ lcdtg_i2c_wait_ack(base_data);
+ lcdtg_i2c_send_byte(base_data, 0x00);
+ lcdtg_i2c_wait_ack(base_data);
+ lcdtg_i2c_send_byte(base_data, data);
+ lcdtg_i2c_wait_ack(base_data);
+ lcdtg_i2c_send_stop(base_data);
+}
+
+/* Set Phase Adjust */
+static void lcdtg_set_phadadj(int mode)
+{
+ int adj;
+ switch(mode) {
+ case 480:
+ case 640:
+ /* Setting for VGA */
+ adj = sharpsl_param.phadadj;
+ if (adj < 0) {
+ adj = PHACTRL_PHASE_MANUAL;
+ } else {
+ adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
+ }
+ break;
+ case 240:
+ case 320:
+ default:
+ /* Setting for QVGA */
+ adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
+ break;
+ }
+
+ corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
+}
+
+static int lcd_inited;
+
+void corgi_lcdtg_hw_init(int mode)
+{
+ if (!lcd_inited) {
+ int comadj;
+
+ /* Initialize Internal Logic & Port */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
+ | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
+
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
+ | POWER0_COM_OFF | POWER0_VCC5_OFF);
+
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
+
+ /* VDD(+8V), SVSS(-4V) ON */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
+ mdelay(3);
+
+ /* DAC ON */
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
+ | POWER0_COM_OFF | POWER0_VCC5_OFF);
+
+ /* INIB = H, INI = L */
+ /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
+
+ /* Set Common Voltage */
+ comadj = sharpsl_param.comadj;
+ if (comadj < 0)
+ comadj = DEFAULT_COMADJ;
+ lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
+
+ /* VCC5 ON, DAC ON */
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
+ POWER0_COM_OFF | POWER0_VCC5_ON);
+
+ /* GVSS(-8V) ON, VDD ON */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
+ mdelay(2);
+
+ /* COM SIGNAL ON (PICTL[3] = L) */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
+
+ /* COM ON, DAC ON, VCC5_ON */
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
+ | POWER0_COM_ON | POWER0_VCC5_ON);
+
+ /* VW ON, GVSS ON, VDD ON */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
+
+ /* Signals output enable */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
+
+ /* Set Phase Adjust */
+ lcdtg_set_phadadj(mode);
+
+ /* Initialize for Input Signals from ATI */
+ corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
+ | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
+ udelay(1000);
+
+ lcd_inited=1;
+ } else {
+ lcdtg_set_phadadj(mode);
+ }
+
+ switch(mode) {
+ case 480:
+ case 640:
+ /* Set Lcd Resolution (VGA) */
+ corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
+ break;
+ case 240:
+ case 320:
+ default:
+ /* Set Lcd Resolution (QVGA) */
+ corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
+ break;
+ }
+}
+
+void corgi_lcdtg_suspend(void)
+{
+ /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
+ mdelay(34);
+
+ /* (1)VW OFF */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
+
+ /* (2)COM OFF */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
+
+ /* (3)Set Common Voltage Bias 0V */
+ lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
+
+ /* (4)GVSS OFF */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
+
+ /* (5)VCC5 OFF */
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
+
+ /* (6)Set PDWN, INIOFF, DACOFF */
+ corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
+ PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
+
+ /* (7)DAC OFF */
+ corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
+
+ /* (8)VDD OFF */
+ corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
+
+ lcd_inited = 0;
+}
+
diff --git a/trunk/arch/arm/mach-pxa/corgi_pm.c b/trunk/arch/arm/mach-pxa/corgi_pm.c
index 3f1dc74ac048..d4a0733e905b 100644
--- a/trunk/arch/arm/mach-pxa/corgi_pm.c
+++ b/trunk/arch/arm/mach-pxa/corgi_pm.c
@@ -14,7 +14,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -26,8 +25,7 @@
#include
#include
#include
-
-#include "generic.h"
+#include
#include "sharpsl.h"
#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
@@ -37,46 +35,87 @@
#define SHARPSL_FATAL_ACIN_VOLT 182 /* 3.45V */
#define SHARPSL_FATAL_NOACIN_VOLT 170 /* 3.40V */
-static struct gpio charger_gpios[] = {
- { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
- { CORGI_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" },
- { CORGI_GPIO_CHRG_UKN, GPIOF_OUT_INIT_LOW, "Charger Unknown" },
- { CORGI_GPIO_KEY_INT, GPIOF_IN, "Key Interrupt" },
-};
-
static void corgi_charger_init(void)
{
- gpio_request_array(ARRAY_AND_SIZE(charger_gpios));
+ pxa_gpio_mode(CORGI_GPIO_ADC_TEMP_ON | GPIO_OUT);
+ pxa_gpio_mode(CORGI_GPIO_CHRG_ON | GPIO_OUT);
+ pxa_gpio_mode(CORGI_GPIO_CHRG_UKN | GPIO_OUT);
+ pxa_gpio_mode(CORGI_GPIO_KEY_INT | GPIO_IN);
}
static void corgi_measure_temp(int on)
{
- gpio_set_value(CORGI_GPIO_ADC_TEMP_ON, on);
+ if (on)
+ GPSR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON);
+ else
+ GPCR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON);
}
static void corgi_charge(int on)
{
if (on) {
if (machine_is_corgi() && (sharpsl_pm.flags & SHARPSL_SUSPENDED)) {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 1);
+ GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
+ GPSR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
} else {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 1);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
+ GPSR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
+ GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
}
} else {
- gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
- gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
+ GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
+ GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
}
}
static void corgi_discharge(int on)
{
- gpio_set_value(CORGI_GPIO_DISCHARGE_ON, on);
+ if (on)
+ GPSR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON);
+ else
+ GPCR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON);
}
static void corgi_presuspend(void)
{
+ int i;
+ unsigned long wakeup_mask;
+
+ /* charging , so CHARGE_ON bit is HIGH during OFF. */
+ if (READ_GPIO_BIT(CORGI_GPIO_CHRG_ON))
+ PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_ON);
+ else
+ PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_ON);
+
+ if (READ_GPIO_BIT(CORGI_GPIO_LED_ORANGE))
+ PGSR0 |= GPIO_bit(CORGI_GPIO_LED_ORANGE);
+ else
+ PGSR0 &= ~GPIO_bit(CORGI_GPIO_LED_ORANGE);
+
+ if (READ_GPIO_BIT(CORGI_GPIO_CHRG_UKN))
+ PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_UKN);
+ else
+ PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_UKN);
+
+ /* Resume on keyboard power key */
+ PGSR2 = (PGSR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(0);
+
+ wakeup_mask = GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) | GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_CHRG_FULL);
+
+ if (!machine_is_corgi())
+ wakeup_mask |= GPIO_bit(CORGI_GPIO_MAIN_BAT_LOW);
+
+ PWER = wakeup_mask | PWER_RTC;
+ PRER = wakeup_mask;
+ PFER = wakeup_mask;
+
+ for (i = 0; i <=15; i++) {
+ if (PRER & PFER & GPIO_bit(i)) {
+ if (GPLR0 & GPIO_bit(i) )
+ PRER &= ~GPIO_bit(i);
+ else
+ PFER &= ~GPIO_bit(i);
+ }
+ }
}
static void corgi_postsuspend(void)
diff --git a/trunk/arch/arm/mach-pxa/corgi_ssp.c b/trunk/arch/arm/mach-pxa/corgi_ssp.c
new file mode 100644
index 000000000000..9347254f8bcf
--- /dev/null
+++ b/trunk/arch/arm/mach-pxa/corgi_ssp.c
@@ -0,0 +1,274 @@
+/*
+ * SSP control code for Sharp Corgi devices
+ *
+ * Copyright (c) 2004-2005 Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include "sharpsl.h"
+
+static DEFINE_SPINLOCK(corgi_ssp_lock);
+static struct ssp_dev corgi_ssp_dev;
+static struct ssp_state corgi_ssp_state;
+static struct corgissp_machinfo *ssp_machinfo;
+
+/*
+ * There are three devices connected to the SSP interface:
+ * 1. A touchscreen controller (TI ADS7846 compatible)
+ * 2. An LCD controller (with some Backlight functionality)
+ * 3. A battery monitoring IC (Maxim MAX1111)
+ *
+ * Each device uses a different speed/mode of communication.
+ *
+ * The touchscreen is very sensitive and the most frequently used
+ * so the port is left configured for this.
+ *
+ * Devices are selected using Chip Selects on GPIOs.
+ */
+
+/*
+ * ADS7846 Routines
+ */
+unsigned long corgi_ssp_ads7846_putget(ulong data)
+{
+ unsigned long flag;
+ u32 ret = 0;
+
+ spin_lock_irqsave(&corgi_ssp_lock, flag);
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
+
+ ssp_write_word(&corgi_ssp_dev,data);
+ ssp_read_word(&corgi_ssp_dev, &ret);
+
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
+ spin_unlock_irqrestore(&corgi_ssp_lock, flag);
+
+ return ret;
+}
+
+/*
+ * NOTE: These functions should always be called in interrupt context
+ * and use the _lock and _unlock functions. They are very time sensitive.
+ */
+void corgi_ssp_ads7846_lock(void)
+{
+ spin_lock(&corgi_ssp_lock);
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
+}
+
+void corgi_ssp_ads7846_unlock(void)
+{
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
+ spin_unlock(&corgi_ssp_lock);
+}
+
+void corgi_ssp_ads7846_put(ulong data)
+{
+ ssp_write_word(&corgi_ssp_dev,data);
+}
+
+unsigned long corgi_ssp_ads7846_get(void)
+{
+ u32 ret = 0;
+ ssp_read_word(&corgi_ssp_dev, &ret);
+ return ret;
+}
+
+EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
+EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
+EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
+EXPORT_SYMBOL(corgi_ssp_ads7846_put);
+EXPORT_SYMBOL(corgi_ssp_ads7846_get);
+
+
+/*
+ * LCD/Backlight Routines
+ */
+unsigned long corgi_ssp_dac_put(ulong data)
+{
+ unsigned long flag, sscr1 = SSCR1_SPH;
+ u32 tmp;
+
+ spin_lock_irqsave(&corgi_ssp_lock, flag);
+
+ if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
+ sscr1 = 0;
+
+ ssp_disable(&corgi_ssp_dev);
+ ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
+ ssp_enable(&corgi_ssp_dev);
+
+ if (ssp_machinfo->cs_lcdcon >= 0)
+ GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
+ ssp_write_word(&corgi_ssp_dev,data);
+ /* Read null data back from device to prevent SSP overflow */
+ ssp_read_word(&corgi_ssp_dev, &tmp);
+ if (ssp_machinfo->cs_lcdcon >= 0)
+ GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
+
+ ssp_disable(&corgi_ssp_dev);
+ ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
+ ssp_enable(&corgi_ssp_dev);
+
+ spin_unlock_irqrestore(&corgi_ssp_lock, flag);
+
+ return 0;
+}
+
+void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
+{
+ corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
+}
+
+void corgi_ssp_blduty_set(int duty)
+{
+ corgi_ssp_lcdtg_send(0x02,duty);
+}
+
+EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
+EXPORT_SYMBOL(corgi_ssp_blduty_set);
+
+/*
+ * Max1111 Routines
+ */
+int corgi_ssp_max1111_get(ulong data)
+{
+ unsigned long flag;
+ long voltage = 0, voltage1 = 0, voltage2 = 0;
+
+ spin_lock_irqsave(&corgi_ssp_lock, flag);
+ if (ssp_machinfo->cs_max1111 >= 0)
+ GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
+ ssp_disable(&corgi_ssp_dev);
+ ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
+ ssp_enable(&corgi_ssp_dev);
+
+ udelay(1);
+
+ /* TB1/RB1 */
+ ssp_write_word(&corgi_ssp_dev,data);
+ ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
+
+ /* TB12/RB2 */
+ ssp_write_word(&corgi_ssp_dev,0);
+ ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
+
+ /* TB13/RB3*/
+ ssp_write_word(&corgi_ssp_dev,0);
+ ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
+
+ ssp_disable(&corgi_ssp_dev);
+ ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
+ ssp_enable(&corgi_ssp_dev);
+ if (ssp_machinfo->cs_max1111 >= 0)
+ GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
+ spin_unlock_irqrestore(&corgi_ssp_lock, flag);
+
+ if (voltage1 & 0xc0 || voltage2 & 0x3f)
+ voltage = -1;
+ else
+ voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
+
+ return voltage;
+}
+
+EXPORT_SYMBOL(corgi_ssp_max1111_get);
+
+/*
+ * Support Routines
+ */
+
+void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
+{
+ ssp_machinfo = machinfo;
+}
+
+static int __devinit corgi_ssp_probe(struct platform_device *dev)
+{
+ int ret;
+
+ /* Chip Select - Disable All */
+ if (ssp_machinfo->cs_lcdcon >= 0)
+ pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
+ if (ssp_machinfo->cs_max1111 >= 0)
+ pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
+
+ ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
+
+ if (ret)
+ printk(KERN_ERR "Unable to register SSP handler!\n");
+ else {
+ ssp_disable(&corgi_ssp_dev);
+ ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
+ ssp_enable(&corgi_ssp_dev);
+ }
+
+ return ret;
+}
+
+static int corgi_ssp_remove(struct platform_device *dev)
+{
+ ssp_exit(&corgi_ssp_dev);
+ return 0;
+}
+
+static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
+{
+ ssp_flush(&corgi_ssp_dev);
+ ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
+
+ return 0;
+}
+
+static int corgi_ssp_resume(struct platform_device *dev)
+{
+ if (ssp_machinfo->cs_lcdcon >= 0)
+ GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
+ if (ssp_machinfo->cs_max1111 >= 0)
+ GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
+ if (ssp_machinfo->cs_ads7846 >= 0)
+ GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
+ ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
+ ssp_enable(&corgi_ssp_dev);
+
+ return 0;
+}
+
+static struct platform_driver corgissp_driver = {
+ .probe = corgi_ssp_probe,
+ .remove = corgi_ssp_remove,
+ .suspend = corgi_ssp_suspend,
+ .resume = corgi_ssp_resume,
+ .driver = {
+ .name = "corgi-ssp",
+ },
+};
+
+int __init corgi_ssp_init(void)
+{
+ return platform_driver_register(&corgissp_driver);
+}
+
+arch_initcall(corgi_ssp_init);
diff --git a/trunk/arch/arm/mach-pxa/csb726.c b/trunk/arch/arm/mach-pxa/csb726.c
index 91fd4fea6a54..88575b87bd33 100644
--- a/trunk/arch/arm/mach-pxa/csb726.c
+++ b/trunk/arch/arm/mach-pxa/csb726.c
@@ -125,9 +125,18 @@ static unsigned long csb726_pin_config[] = {
GPIO118_I2C_SDA,
};
+static struct pxamci_platform_data csb726_mci_data;
+
+static int csb726_mci_init(struct device *dev,
+ irq_handler_t detect, void *data)
+{
+ csb726_mci_data.detect_delay = msecs_to_jiffies(500);
+ return 0;
+}
+
static struct pxamci_platform_data csb726_mci = {
- .detect_delay_ms = 500,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+ .init = csb726_mci_init,
/* FIXME setpower */
.gpio_card_detect = CSB726_GPIO_MMC_DETECT,
.gpio_card_ro = CSB726_GPIO_MMC_RO,
diff --git a/trunk/arch/arm/mach-pxa/em-x270.c b/trunk/arch/arm/mach-pxa/em-x270.c
index 0517c17978f3..aab04f33e49b 100644
--- a/trunk/arch/arm/mach-pxa/em-x270.c
+++ b/trunk/arch/arm/mach-pxa/em-x270.c
@@ -626,7 +626,6 @@ static int em_x270_mci_get_ro(struct device *dev)
}
static struct pxamci_platform_data em_x270_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
@@ -644,6 +643,7 @@ static void __init em_x270_init_mmc(void)
if (machine_is_em_x270())
em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro;
+ em_x270_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&em_x270_mci_platform_data);
}
#else
diff --git a/trunk/arch/arm/mach-pxa/generic.c b/trunk/arch/arm/mach-pxa/generic.c
index baabb3ce088e..3126a35aa002 100644
--- a/trunk/arch/arm/mach-pxa/generic.c
+++ b/trunk/arch/arm/mach-pxa/generic.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include "generic.h"
@@ -127,3 +128,33 @@ void __init pxa_map_io(void)
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
get_clk_frequency_khz(1);
}
+
+/*
+ * Configure pins for GPIO or other functions
+ */
+int pxa_gpio_mode(int gpio_mode)
+{
+ unsigned long flags;
+ int gpio = gpio_mode & GPIO_MD_MASK_NR;
+ int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
+ int gafr;
+
+ if (gpio > pxa_last_gpio)
+ return -EINVAL;
+
+ local_irq_save(flags);
+ if (gpio_mode & GPIO_DFLT_LOW)
+ GPCR(gpio) = GPIO_bit(gpio);
+ else if (gpio_mode & GPIO_DFLT_HIGH)
+ GPSR(gpio) = GPIO_bit(gpio);
+ if (gpio_mode & GPIO_MD_MASK_DIR)
+ GPDR(gpio) |= GPIO_bit(gpio);
+ else
+ GPDR(gpio) &= ~GPIO_bit(gpio);
+ gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
+ GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
+ local_irq_restore(flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(pxa_gpio_mode);
diff --git a/trunk/arch/arm/mach-pxa/include/mach/colibri.h b/trunk/arch/arm/mach-pxa/include/mach/colibri.h
index 5f2ba8d9015c..811743c56147 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/colibri.h
@@ -2,7 +2,6 @@
#define _COLIBRI_H_
#include
-#include
/*
* common settings for all modules
diff --git a/trunk/arch/arm/mach-pxa/include/mach/corgi.h b/trunk/arch/arm/mach-pxa/include/mach/corgi.h
index 585970ef08ce..7239281788de 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/corgi.h
@@ -113,6 +113,7 @@
* Shared data structures
*/
extern struct platform_device corgiscoop_device;
+extern struct platform_device corgissp_device;
#endif /* __ASM_ARCH_CORGI_H */
diff --git a/trunk/arch/arm/mach-pxa/include/mach/hardware.h b/trunk/arch/arm/mach-pxa/include/mach/hardware.h
index 3d8d8cb09685..7515757d6911 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/hardware.h
@@ -202,7 +202,7 @@
#define __cpu_is_pxa950(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
- _id == 0x697; \
+ id == 0x697; \
})
#else
#define __cpu_is_pxa950(id) (0)
diff --git a/trunk/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/trunk/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index c54cef25895c..658b28ed129b 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -25,8 +25,6 @@
#define MFP_DIR(x) (((x) >> 23) & 0x1)
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
-#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
-
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
diff --git a/trunk/arch/arm/mach-pxa/include/mach/mmc.h b/trunk/arch/arm/mach-pxa/include/mach/mmc.h
index 9eb515bb799d..02a69dc2ee63 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/mmc.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/mmc.h
@@ -9,7 +9,7 @@ struct mmc_host;
struct pxamci_platform_data {
unsigned int ocr_mask; /* available voltages */
- unsigned long detect_delay_ms; /* delay in millisecond before detecting cards after interrupt */
+ unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */
int (*init)(struct device *, irq_handler_t , void *);
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
diff --git a/trunk/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/trunk/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
new file mode 100644
index 000000000000..1209c44aa6f1
--- /dev/null
+++ b/trunk/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -0,0 +1,375 @@
+#ifndef __ASM_ARCH_PXA2XX_GPIO_H
+#define __ASM_ARCH_PXA2XX_GPIO_H
+
+#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
+
+#include
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST 1 /* reset */
+#define GPIO6_MMCCLK 6 /* MMC Clock */
+#define GPIO7_48MHz 7 /* 48 MHz clock output */
+#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz 12 /* 32 kHz out */
+#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */
+#define GPIO13_MBGNT 13 /* memory controller grant */
+#define GPIO14_MBREQ 14 /* alternate bus master request */
+#define GPIO15_nCS_1 15 /* chip select 1 */
+#define GPIO16_PWM0 16 /* PWM0 output */
+#define GPIO17_PWM1 17 /* PWM1 output */
+#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */
+#define GPIO18_RDY 18 /* Ext. Bus Ready */
+#define GPIO19_DREQ1 19 /* External DMA Request */
+#define GPIO20_DREQ0 20 /* External DMA Request */
+#define GPIO23_SCLK 23 /* SSP clock */
+#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */
+#define GPIO24_SFRM 24 /* SSP Frame */
+#define GPIO24_CIF_FV 24 /* Camera frame start signal */
+#define GPIO25_STXD 25 /* SSP transmit */
+#define GPIO25_CIF_LV 25 /* Camera line start signal */
+#define GPIO26_SRXD 26 /* SSP receive */
+#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */
+#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
+#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */
+#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC 31 /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK 32 /* I2S System Clock */
+#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5 33 /* chip select 5 */
+#define GPIO34_FFRXD 34 /* FFUART receive */
+#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
+#define GPIO35_FFCTS 35 /* FFUART Clear to send */
+#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
+#define GPIO37_FFDSR 37 /* FFUART data set ready */
+#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
+#define GPIO39_FFTXD 39 /* FFUART transmit data */
+#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
+#define GPIO41_FFRTS 41 /* FFUART request to send */
+#define GPIO42_BTRXD 42 /* BTUART receive data */
+#define GPIO42_HWRXD 42 /* HWUART receive data */
+#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */
+#define GPIO43_BTTXD 43 /* BTUART transmit data */
+#define GPIO43_HWTXD 43 /* HWUART transmit data */
+#define GPIO43_CIF_FV 43 /* Camera frame start signal */
+#define GPIO44_BTCTS 44 /* BTUART clear to send */
+#define GPIO44_HWCTS 44 /* HWUART clear to send */
+#define GPIO44_CIF_LV 44 /* Camera line start signal */
+#define GPIO45_BTRTS 45 /* BTUART request to send */
+#define GPIO45_HWRTS 45 /* HWUART request to send */
+#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
+#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */
+#define GPIO46_ICPRXD 46 /* ICP receive data */
+#define GPIO46_STRXD 46 /* STD_UART receive data */
+#define GPIO47_ICPTXD 47 /* ICP transmit data */
+#define GPIO47_STTXD 47 /* STD_UART transmit data */
+#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */
+#define GPIO48_nPOE 48 /* Output Enable for Card Space */
+#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */
+#define GPIO49_nPWE 49 /* Write Enable for Card Space */
+#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
+#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
+#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
+#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */
+#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
+#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */
+#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
+#define GPIO53_MMCCLK 53 /* MMC Clock */
+#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */
+#define GPIO54_MMCCLK 54 /* MMC Clock */
+#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
+#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
+#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */
+#define GPIO55_nPREG 55 /* Card Address bit 26 */
+#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */
+#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
+#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0 58 /* LCD data pin 0 */
+#define GPIO59_LDD_1 59 /* LCD data pin 1 */
+#define GPIO60_LDD_2 60 /* LCD data pin 2 */
+#define GPIO61_LDD_3 61 /* LCD data pin 3 */
+#define GPIO62_LDD_4 62 /* LCD data pin 4 */
+#define GPIO63_LDD_5 63 /* LCD data pin 5 */
+#define GPIO64_LDD_6 64 /* LCD data pin 6 */
+#define GPIO65_LDD_7 65 /* LCD data pin 7 */
+#define GPIO66_LDD_8 66 /* LCD data pin 8 */
+#define GPIO66_MBREQ 66 /* alternate bus master req */
+#define GPIO67_LDD_9 67 /* LCD data pin 9 */
+#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
+#define GPIO68_LDD_10 68 /* LCD data pin 10 */
+#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
+#define GPIO69_LDD_11 69 /* LCD data pin 11 */
+#define GPIO69_MMCCLK 69 /* MMC_CLK */
+#define GPIO70_LDD_12 70 /* LCD data pin 12 */
+#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13 71 /* LCD data pin 13 */
+#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14 72 /* LCD data pin 14 */
+#define GPIO72_32kHz 72 /* 32 kHz clock */
+#define GPIO73_LDD_15 73 /* LCD data pin 15 */
+#define GPIO73_MBGNT 73 /* Memory controller grant */
+#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
+#define GPIO75_LCD_LCLK 75 /* LCD line clock */
+#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
+#define GPIO78_nCS_2 78 /* chip select 2 */
+#define GPIO79_nCS_3 79 /* chip select 3 */
+#define GPIO80_nCS_4 80 /* chip select 4 */
+#define GPIO81_NSCLK 81 /* NSSP clock */
+#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */
+#define GPIO82_NSFRM 82 /* NSSP Frame */
+#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
+#define GPIO83_NSTXD 83 /* NSSP transmit */
+#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */
+#define GPIO84_NSRXD 84 /* NSSP receive */
+#define GPIO84_CIF_FV 84 /* Camera frame start signal */
+#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
+#define GPIO85_CIF_LV 85 /* Camera line start signal */
+#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */
+#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */
+#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
+#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
+#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
+#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
+#define GPIO96_FFRXD 96 /* FFUART recieve */
+#define GPIO98_FFRTS 98 /* FFUART request to send */
+#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
+#define GPIO99_FFTXD 99 /* FFUART transmit data */
+#define GPIO100_FFCTS 100 /* FFUART Clear to send */
+#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
+#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
+#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
+#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */
+#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */
+#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */
+#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */
+#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
+#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
+#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */
+#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */
+#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN 0x000
+#define GPIO_OUT 0x080
+#define GPIO_ALT_FN_1_IN 0x100
+#define GPIO_ALT_FN_1_OUT 0x180
+#define GPIO_ALT_FN_2_IN 0x200
+#define GPIO_ALT_FN_2_OUT 0x280
+#define GPIO_ALT_FN_3_IN 0x300
+#define GPIO_ALT_FN_3_OUT 0x380
+#define GPIO_MD_MASK_NR 0x07f
+#define GPIO_MD_MASK_DIR 0x080
+#define GPIO_MD_MASK_FN 0x300
+#define GPIO_DFLT_LOW 0x400
+#define GPIO_DFLT_HIGH 0x800
+
+#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN)
+#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN)
+#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT)
+#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT)
+#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT)
+#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
+#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN)
+#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
+#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN)
+#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
+#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT)
+#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
+#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
+#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
+#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN)
+#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN)
+#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN)
+#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
+#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
+#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
+#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
+#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN)
+#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN)
+#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN)
+#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT)
+#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
+#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
+#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN)
+#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
+#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
+#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
+#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN)
+#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
+#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
+#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
+#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
+#define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN)
+#define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT)
+#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
+#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
+#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN)
+#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN)
+#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
+#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
+#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
+#define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN)
+#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
+#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
+#define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT)
+#define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT)
+#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
+#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
+#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
+#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN)
+#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
+#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN)
+#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
+#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN)
+#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
+#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN)
+#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
+#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN)
+#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
+#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN)
+#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
+#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
+#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
+
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern int pxa_gpio_mode( int gpio_mode );
+
+#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/trunk/arch/arm/plat-pxa/include/plat/ssp.h b/trunk/arch/arm/mach-pxa/include/mach/regs-ssp.h
similarity index 75%
rename from trunk/arch/arm/plat-pxa/include/plat/ssp.h
rename to trunk/arch/arm/mach-pxa/include/mach/regs-ssp.h
index fe43150690ed..6a2ed35acd59 100644
--- a/trunk/arch/arm/plat-pxa/include/plat/ssp.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -1,26 +1,5 @@
-/*
- * ssp.h
- *
- * Copyright (C) 2003 Russell King, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This driver supports the following PXA CPU/SSP ports:-
- *
- * PXA250 SSP
- * PXA255 SSP, NSSP
- * PXA26x SSP, NSSP, ASSP
- * PXA27x SSP1, SSP2, SSP3
- * PXA3xx SSP1, SSP2, SSP3, SSP4
- */
-
-#ifndef __ASM_ARCH_SSP_H
-#define __ASM_ARCH_SSP_H
-
-#include
-#include
+#ifndef __ASM_ARCH_REGS_SSP_H
+#define __ASM_ARCH_REGS_SSP_H
/*
* SSP Serial Port Registers
@@ -40,7 +19,10 @@
#define SSRSA (0x34) /* SSP Rx Timeslot Active */
#define SSTSS (0x38) /* SSP Timeslot Status */
#define SSACD (0x3C) /* SSP Audio Clock Divider */
+
+#if defined(CONFIG_PXA3xx)
#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
+#endif
/* Common PXA2xx bits first */
#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
@@ -51,19 +33,29 @@
#define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
-#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
-/* PXA27x, PXA3xx */
+#if defined(CONFIG_PXA25x)
+#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#endif
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_EDSS (1 << 20) /* Extended data size select */
#define SSCR0_NCS (1 << 21) /* Network clock select */
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
-#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
#define SSCR0_ACS (1 << 30) /* Audio clock select */
#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
+#endif
+#if defined(CONFIG_PXA3xx)
+#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
+#endif
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
@@ -83,6 +75,10 @@
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
+#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS (1 << 21) /* Network Clock Select */
+#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
@@ -112,75 +108,27 @@
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
+#if defined(CONFIG_PXA3xx)
+#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
+#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
+#endif
-#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
-#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
-#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
-#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
-#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
-#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
-#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
-#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
-
-/* PXA3xx */
-#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
-#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
-#define SSPSP_TIMING_MASK (0x7f8001f0)
+#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
+#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
+#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
+#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
+#if defined(CONFIG_PXA3xx)
#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
+#endif
-enum pxa_ssp_type {
- SSP_UNDEFINED = 0,
- PXA25x_SSP, /* pxa 210, 250, 255, 26x */
- PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
- PXA27x_SSP,
- PXA168_SSP,
-};
-
-struct ssp_device {
- struct platform_device *pdev;
- struct list_head node;
-
- struct clk *clk;
- void __iomem *mmio_base;
- unsigned long phys_base;
-
- const char *label;
- int port_id;
- int type;
- int use_count;
- int irq;
- int drcmr_rx;
- int drcmr_tx;
-};
-
-/**
- * pxa_ssp_write_reg - Write to a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to write to
- * @val: Value to be written.
- */
-static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
-{
- __raw_writel(val, dev->mmio_base + reg);
-}
-
-/**
- * pxa_ssp_read_reg - Read from a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to read from
- */
-static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
-{
- return __raw_readl(dev->mmio_base + reg);
-}
-
-struct ssp_device *pxa_ssp_request(int port, const char *label);
-void pxa_ssp_free(struct ssp_device *);
-#endif /* __ASM_ARCH_SSP_H */
+
+#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/trunk/arch/arm/mach-pxa/include/mach/regs-u2d.h b/trunk/arch/arm/mach-pxa/include/mach/regs-u2d.h
index c15c0c57de08..44b0b20b69a4 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/regs-u2d.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/regs-u2d.h
@@ -166,8 +166,7 @@
#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */
#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */
#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */
-#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */
-#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */
+#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */
#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */
#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */
#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */
diff --git a/trunk/arch/arm/mach-pxa/include/mach/ssp.h b/trunk/arch/arm/mach-pxa/include/mach/ssp.h
new file mode 100644
index 000000000000..be1be5b6db51
--- /dev/null
+++ b/trunk/arch/arm/mach-pxa/include/mach/ssp.h
@@ -0,0 +1,109 @@
+/*
+ * ssp.h
+ *
+ * Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver supports the following PXA CPU/SSP ports:-
+ *
+ * PXA250 SSP
+ * PXA255 SSP, NSSP
+ * PXA26x SSP, NSSP, ASSP
+ * PXA27x SSP1, SSP2, SSP3
+ * PXA3xx SSP1, SSP2, SSP3, SSP4
+ */
+
+#ifndef __ASM_ARCH_SSP_H
+#define __ASM_ARCH_SSP_H
+
+#include
+#include
+
+enum pxa_ssp_type {
+ SSP_UNDEFINED = 0,
+ PXA25x_SSP, /* pxa 210, 250, 255, 26x */
+ PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
+ PXA27x_SSP,
+};
+
+struct ssp_device {
+ struct platform_device *pdev;
+ struct list_head node;
+
+ struct clk *clk;
+ void __iomem *mmio_base;
+ unsigned long phys_base;
+
+ const char *label;
+ int port_id;
+ int type;
+ int use_count;
+ int irq;
+ int drcmr_rx;
+ int drcmr_tx;
+};
+
+#ifdef CONFIG_PXA_SSP_LEGACY
+/*
+ * SSP initialisation flags
+ */
+#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */
+
+struct ssp_state {
+ u32 cr0;
+ u32 cr1;
+ u32 to;
+ u32 psp;
+};
+
+struct ssp_dev {
+ struct ssp_device *ssp;
+ u32 port;
+ u32 mode;
+ u32 flags;
+ u32 psp_flags;
+ u32 speed;
+ int irq;
+};
+
+int ssp_write_word(struct ssp_dev *dev, u32 data);
+int ssp_read_word(struct ssp_dev *dev, u32 *data);
+int ssp_flush(struct ssp_dev *dev);
+void ssp_enable(struct ssp_dev *dev);
+void ssp_disable(struct ssp_dev *dev);
+void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
+void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
+int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
+int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
+void ssp_exit(struct ssp_dev *dev);
+#endif /* CONFIG_PXA_SSP_LEGACY */
+
+/**
+ * ssp_write_reg - Write to a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to write to
+ * @val: Value to be written.
+ */
+static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
+{
+ __raw_writel(val, dev->mmio_base + reg);
+}
+
+/**
+ * ssp_read_reg - Read from a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to read from
+ */
+static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
+{
+ return __raw_readl(dev->mmio_base + reg);
+}
+
+struct ssp_device *ssp_request(int port, const char *label);
+void ssp_free(struct ssp_device *);
+#endif /* __ASM_ARCH_SSP_H */
diff --git a/trunk/arch/arm/mach-pxa/include/mach/tosa.h b/trunk/arch/arm/mach-pxa/include/mach/tosa.h
index 1bbd1f2e4beb..4df2d38507dc 100644
--- a/trunk/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/trunk/arch/arm/mach-pxa/include/mach/tosa.h
@@ -167,7 +167,7 @@
#define TOSA_KEY_SYNC KEY_102ND /* ??? */
-#ifndef CONFIG_TOSA_USE_EXT_KEYCODES
+#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
#define TOSA_KEY_RECORD KEY_YEN
#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
#define TOSA_KEY_CANCEL KEY_ESC
diff --git a/trunk/arch/arm/mach-pxa/include/mach/vpac270.h b/trunk/arch/arm/mach-pxa/include/mach/vpac270.h
deleted file mode 100644
index 7bfa3dd0fd5e..000000000000
--- a/trunk/arch/arm/mach-pxa/include/mach/vpac270.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * GPIOs and interrupts for Voipac PXA270
- *
- * Copyright (C) 2010
- * Marek Vasut
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _INCLUDE_VPAC270_H_
-#define _INCLUDE_VPAC270_H_
-
-#define GPIO1_VPAC270_USER_BTN 1
-
-#define GPIO15_VPAC270_LED_ORANGE 15
-
-#define GPIO81_VPAC270_BKL_ON 81
-#define GPIO83_VPAC270_NL_ON 83
-
-#define GPIO52_VPAC270_SD_READONLY 52
-#define GPIO53_VPAC270_SD_DETECT_N 53
-
-#define GPIO84_VPAC270_PCMCIA_CD 84
-#define GPIO35_VPAC270_PCMCIA_RDY 35
-#define GPIO107_VPAC270_PCMCIA_PPEN 107
-#define GPIO11_VPAC270_PCMCIA_RESET 11
-#define GPIO17_VPAC270_CF_CD 17
-#define GPIO12_VPAC270_CF_RDY 12
-#define GPIO16_VPAC270_CF_RESET 16
-
-#define GPIO41_VPAC270_UDC_DETECT 41
-
-#define GPIO114_VPAC270_ETH_IRQ 114
-
-#define GPIO36_VPAC270_IDE_IRQ 36
-
-#define GPIO113_VPAC270_TS_IRQ 113
-
-#endif
diff --git a/trunk/arch/arm/mach-pxa/include/mach/z2.h b/trunk/arch/arm/mach-pxa/include/mach/z2.h
deleted file mode 100644
index 8835c16bc82f..000000000000
--- a/trunk/arch/arm/mach-pxa/include/mach/z2.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/z2.h
- *
- * Author: Ken McGuire
- * Created: Feb 6, 2009
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef ASM_ARCH_ZIPIT2_H
-#define ASM_ARCH_ZIPIT2_H
-
-/* LEDs */
-#define GPIO10_ZIPITZ2_LED_WIFI 10
-#define GPIO85_ZIPITZ2_LED_CHARGED 85
-#define GPIO83_ZIPITZ2_LED_CHARGING 83
-
-/* SD/MMC */
-#define GPIO96_ZIPITZ2_SD_DETECT 96
-
-/* GPIO Buttons */
-#define GPIO1_ZIPITZ2_POWER_BUTTON 1
-#define GPIO98_ZIPITZ2_LID_BUTTON 98
-
-/* Libertas GSPI8686 WiFi */
-#define GPIO14_ZIPITZ2_WIFI_RESET 14
-#define GPIO15_ZIPITZ2_WIFI_POWER 15
-#define GPIO24_ZIPITZ2_WIFI_CS 24
-#define GPIO36_ZIPITZ2_WIFI_IRQ 36
-
-/* LCD */
-#define GPIO19_ZIPITZ2_LCD_RESET 19
-#define GPIO88_ZIPITZ2_LCD_CS 88
-
-/* MISC GPIOs */
-#define GPIO0_ZIPITZ2_AC_DETECT 0
-#define GPIO37_ZIPITZ2_HEADSET_DETECT 37
-
-#endif
diff --git a/trunk/arch/arm/mach-pxa/littleton.c b/trunk/arch/arm/mach-pxa/littleton.c
index 9b9046185b00..fa527b258d61 100644
--- a/trunk/arch/arm/mach-pxa/littleton.c
+++ b/trunk/arch/arm/mach-pxa/littleton.c
@@ -41,6 +41,7 @@
#include
#include
+#include
#include
#include
#include
@@ -271,7 +272,7 @@ static inline void littleton_init_keypad(void) {}
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
static struct pxamci_platform_data littleton_mci_platform_data = {
- .detect_delay_ms = 200,
+ .detect_delay = 20,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.gpio_card_detect = GPIO_MMC1_CARD_DETECT,
.gpio_card_ro = -1,
diff --git a/trunk/arch/arm/mach-pxa/lubbock.c b/trunk/arch/arm/mach-pxa/lubbock.c
index 330c3282856e..63d65a2a0387 100644
--- a/trunk/arch/arm/mach-pxa/lubbock.c
+++ b/trunk/arch/arm/mach-pxa/lubbock.c
@@ -478,7 +478,7 @@ static void lubbock_mci_exit(struct device *dev, void *data)
static struct pxamci_platform_data lubbock_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .detect_delay_ms = 10,
+ .detect_delay = 1,
.init = lubbock_mci_init,
.get_ro = lubbock_mci_get_ro,
.exit = lubbock_mci_exit,
diff --git a/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c b/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c
index 1d1419b73457..cf6b720c055f 100644
--- a/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/trunk/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -81,7 +81,6 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
PGSR(bank) &= ~mask;
is_out = 1;
break;
- case MFP_LPM_INPUT:
case MFP_LPM_DEFAULT:
break;
default:
@@ -179,17 +178,8 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
if (!d->valid)
return -EINVAL;
- /* Allow keypad GPIOs to wakeup system when
- * configured as generic GPIOs.
- */
- if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
- (d->config & MFP_LPM_CAN_WAKEUP)) {
- if (on)
- PKWR |= d->mask;
- else
- PKWR &= ~d->mask;
- return 0;
- }
+ if (d->keypad_gpio)
+ return -EINVAL;
mux_taken = (PWER & d->mux_mask) & (~d->mask);
if (on && mux_taken)
@@ -249,25 +239,21 @@ static int pxa27x_pkwr_gpio[] = {
int keypad_set_wake(unsigned int on)
{
unsigned int i, gpio, mask = 0;
- struct gpio_desc *d;
+
+ if (!on) {
+ PKWR = 0;
+ return 0;
+ }
for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
gpio = pxa27x_pkwr_gpio[i];
- d = &gpio_desc[gpio];
- /* skip if configured as generic GPIO */
- if (MFP_AF(d->config) == 0)
- continue;
-
- if (d->config & MFP_LPM_CAN_WAKEUP)
+ if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP)
mask |= gpio_desc[gpio].mask;
}
- if (on)
- PKWR |= mask;
- else
- PKWR &= ~mask;
+ PKWR = mask;
return 0;
}
@@ -342,17 +328,6 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
{
int i;
- /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
- for (i = 0; i < pxa_last_gpio; i++) {
- if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
- (GPDR(i) & GPIO_bit(i))) {
- if (GPLR(i) & GPIO_bit(i))
- PGSR(i) |= GPIO_bit(i);
- else
- PGSR(i) &= ~GPIO_bit(i);
- }
- }
-
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
saved_gafr[0][i] = GAFR_L(i);
diff --git a/trunk/arch/arm/mach-pxa/mioa701.c b/trunk/arch/arm/mach-pxa/mioa701.c
index d60db87dde08..7a50ed8fce94 100644
--- a/trunk/arch/arm/mach-pxa/mioa701.c
+++ b/trunk/arch/arm/mach-pxa/mioa701.c
@@ -426,7 +426,6 @@ struct gpio_vbus_mach_info gpio_vbus_data = {
* to give the card a chance to fully insert/eject.
*/
static struct pxamci_platform_data mioa701_mci_info = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.gpio_card_detect = GPIO15_SDIO_INSERT,
.gpio_card_ro = GPIO78_SDIO_RO,
@@ -792,6 +791,7 @@ static void __init mioa701_machine_init(void)
mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
bootstrap_init();
set_pxa_fb_info(&mioa701_pxafb_info);
+ mioa701_mci_info.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&mioa701_mci_info);
pxa_set_keypad_info(&mioa701_keypad_info);
wm97xx_bat_set_pdata(&mioa701_battery_data);
diff --git a/trunk/arch/arm/mach-pxa/mxm8x10.c b/trunk/arch/arm/mach-pxa/mxm8x10.c
index 462167ac05f9..8c9c6f0d56bb 100644
--- a/trunk/arch/arm/mach-pxa/mxm8x10.c
+++ b/trunk/arch/arm/mach-pxa/mxm8x10.c
@@ -325,7 +325,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
#if defined(CONFIG_MMC)
static struct pxamci_platform_data mxm_8x10_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
- .detect_delay_ms = 10,
+ .detect_delay = 1,
.gpio_card_detect = MXM_8X10_SD_nCD,
.gpio_card_ro = MXM_8X10_SD_WP,
.gpio_power = -1
diff --git a/trunk/arch/arm/mach-pxa/palmld.c b/trunk/arch/arm/mach-pxa/palmld.c
index 1963819dba98..f70c75b38769 100644
--- a/trunk/arch/arm/mach-pxa/palmld.c
+++ b/trunk/arch/arm/mach-pxa/palmld.c
@@ -168,7 +168,7 @@ static struct pxamci_platform_data palmld_mci_platform_data = {
.gpio_card_detect = GPIO_NR_PALMLD_SD_DETECT_N,
.gpio_card_ro = GPIO_NR_PALMLD_SD_READONLY,
.gpio_power = GPIO_NR_PALMLD_SD_POWER,
- .detect_delay_ms = 200,
+ .detect_delay = 20,
};
/******************************************************************************
diff --git a/trunk/arch/arm/mach-pxa/palmt5.c b/trunk/arch/arm/mach-pxa/palmt5.c
index 5305a3993e69..d902a813aae3 100644
--- a/trunk/arch/arm/mach-pxa/palmt5.c
+++ b/trunk/arch/arm/mach-pxa/palmt5.c
@@ -110,7 +110,7 @@ static struct pxamci_platform_data palmt5_mci_platform_data = {
.gpio_card_detect = GPIO_NR_PALMT5_SD_DETECT_N,
.gpio_card_ro = GPIO_NR_PALMT5_SD_READONLY,
.gpio_power = GPIO_NR_PALMT5_SD_POWER,
- .detect_delay_ms = 200,
+ .detect_delay = 20,
};
/******************************************************************************
diff --git a/trunk/arch/arm/mach-pxa/palmtc.c b/trunk/arch/arm/mach-pxa/palmtc.c
index 033b567e50bb..717d7a638675 100644
--- a/trunk/arch/arm/mach-pxa/palmtc.c
+++ b/trunk/arch/arm/mach-pxa/palmtc.c
@@ -121,7 +121,7 @@ static struct pxamci_platform_data palmtc_mci_platform_data = {
.gpio_power = GPIO_NR_PALMTC_SD_POWER,
.gpio_card_ro = GPIO_NR_PALMTC_SD_READONLY,
.gpio_card_detect = GPIO_NR_PALMTC_SD_DETECT_N,
- .detect_delay_ms = 200,
+ .detect_delay = 20,
};
/******************************************************************************
diff --git a/trunk/arch/arm/mach-pxa/palmtx.c b/trunk/arch/arm/mach-pxa/palmtx.c
index ecc1a401598e..007b58c11f8d 100644
--- a/trunk/arch/arm/mach-pxa/palmtx.c
+++ b/trunk/arch/arm/mach-pxa/palmtx.c
@@ -170,7 +170,7 @@ static struct pxamci_platform_data palmtx_mci_platform_data = {
.gpio_card_detect = GPIO_NR_PALMTX_SD_DETECT_N,
.gpio_card_ro = GPIO_NR_PALMTX_SD_READONLY,
.gpio_power = GPIO_NR_PALMTX_SD_POWER,
- .detect_delay_ms = 200,
+ .detect_delay = 20,
};
/******************************************************************************
diff --git a/trunk/arch/arm/mach-pxa/pcm990-baseboard.c b/trunk/arch/arm/mach-pxa/pcm990-baseboard.c
index f56ae1008759..9d0ecea1760c 100644
--- a/trunk/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/trunk/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -326,7 +326,7 @@ static void pcm990_mci_exit(struct device *dev, void *data)
#define MSECS_PER_JIFFY (1000/HZ)
static struct pxamci_platform_data pcm990_mci_platform_data = {
- .detect_delay_ms = 250,
+ .detect_delay = 250 / MSECS_PER_JIFFY,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = pcm990_mci_init,
.setpower = pcm990_mci_setpower,
diff --git a/trunk/arch/arm/mach-pxa/poodle.c b/trunk/arch/arm/mach-pxa/poodle.c
index f4abdaafdac4..d58a52415d75 100644
--- a/trunk/arch/arm/mach-pxa/poodle.c
+++ b/trunk/arch/arm/mach-pxa/poodle.c
@@ -40,12 +40,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
-#include
#include
#include
@@ -276,7 +277,6 @@ static void poodle_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data poodle_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = poodle_mci_init,
.setpower = poodle_mci_setpower,
@@ -450,6 +450,7 @@ static void __init poodle_init(void)
set_pxa_fb_parent(&poodle_locomo_device.dev);
set_pxa_fb_info(&poodle_fb_info);
pxa_set_udc_info(&udc_info);
+ poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&poodle_mci_platform_data);
pxa_set_ficp_info(&poodle_ficp_platform_data);
pxa_set_i2c_info(NULL);
diff --git a/trunk/arch/arm/mach-pxa/pxa3xx.c b/trunk/arch/arm/mach-pxa/pxa3xx.c
index f544e58e1536..4d7c03e72504 100644
--- a/trunk/arch/arm/mach-pxa/pxa3xx.c
+++ b/trunk/arch/arm/mach-pxa/pxa3xx.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
diff --git a/trunk/arch/arm/mach-pxa/raumfeld.c b/trunk/arch/arm/mach-pxa/raumfeld.c
index d4b61b3f08f3..44bb675e47f1 100644
--- a/trunk/arch/arm/mach-pxa/raumfeld.c
+++ b/trunk/arch/arm/mach-pxa/raumfeld.c
@@ -714,7 +714,7 @@ static void raumfeld_mci_exit(struct device *dev, void *data)
static struct pxamci_platform_data raumfeld_mci_platform_data = {
.init = raumfeld_mci_init,
.exit = raumfeld_mci_exit,
- .detect_delay_ms = 200,
+ .detect_delay = 20,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
@@ -983,7 +983,7 @@ static void __init raumfeld_common_init(void)
int i;
for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++)
- if (!strcmp(gpio_keys_button[i].desc, "on_off button"))
+ if (!strcmp(gpio_keys_button[i].desc, "on/off button"))
gpio_keys_button[i].active_low = 1;
}
@@ -1009,7 +1009,8 @@ static void __init raumfeld_common_init(void)
gpio_direction_output(GPIO_W2W_PDN, 0);
/* this can be used to switch off the device */
- ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, "supply shutdown");
+ ret = gpio_request(GPIO_SHUTDOWN_SUPPLY,
+ "supply shutdown");
if (ret < 0)
pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n");
else
diff --git a/trunk/arch/arm/mach-pxa/sharpsl.h b/trunk/arch/arm/mach-pxa/sharpsl.h
index 0cc1203c5bef..1439785d3979 100644
--- a/trunk/arch/arm/mach-pxa/sharpsl.h
+++ b/trunk/arch/arm/mach-pxa/sharpsl.h
@@ -9,6 +9,29 @@
#include
+/*
+ * SharpSL SSP Driver
+ */
+struct corgissp_machinfo {
+ int port;
+ int cs_lcdcon;
+ int cs_ads7846;
+ int cs_max1111;
+ int clk_lcdcon;
+ int clk_ads7846;
+ int clk_max1111;
+};
+
+void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo);
+
+
+/*
+ * SharpSL/Corgi LCD Driver
+ */
+void corgi_lcdtg_suspend(void);
+void corgi_lcdtg_hw_init(int mode);
+
+
/*
* SharpSL Battery/PM Driver
*/
diff --git a/trunk/arch/arm/mach-pxa/sharpsl_pm.c b/trunk/arch/arm/mach-pxa/sharpsl_pm.c
index cb4767251f3c..463d874bb867 100644
--- a/trunk/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/trunk/arch/arm/mach-pxa/sharpsl_pm.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/trunk/arch/arm/mach-pxa/spitz.c b/trunk/arch/arm/mach-pxa/spitz.c
index 4d2413ed0ffa..19b5109d9808 100644
--- a/trunk/arch/arm/mach-pxa/spitz.c
+++ b/trunk/arch/arm/mach-pxa/spitz.c
@@ -86,7 +86,6 @@ static unsigned long spitz_pin_config[] __initdata = {
/* GPIOs */
GPIO9_GPIO, /* SPITZ_GPIO_nSD_DETECT */
- GPIO16_GPIO, /* SPITZ_GPIO_SYNC */
GPIO81_GPIO, /* SPITZ_GPIO_nSD_WP */
GPIO41_GPIO, /* SPITZ_GPIO_USB_CONNECT */
GPIO37_GPIO, /* SPITZ_GPIO_USB_HOST */
@@ -120,8 +119,7 @@ static unsigned long spitz_pin_config[] __initdata = {
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
- GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* SPITZ_GPIO_KEY_INT */
- GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */
+ GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
};
/*
@@ -365,7 +363,7 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
.type = EV_PWR,
.code = KEY_SUSPEND,
.gpio = SPITZ_GPIO_ON_KEY,
- .desc = "On Off",
+ .desc = "On/Off",
.wakeup = 1,
},
/* Two buttons detecting the lid state */
@@ -539,7 +537,6 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
}
static struct pxamci_platform_data spitz_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.setpower = spitz_mci_setpower,
.gpio_card_detect = SPITZ_GPIO_nSD_DETECT,
@@ -760,6 +757,7 @@ static void __init common_init(void)
spitz_init_spi();
platform_add_devices(devices, ARRAY_SIZE(devices));
+ spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&spitz_mci_platform_data);
pxa_set_ohci_info(&spitz_ohci_platform_data);
pxa_set_ficp_info(&spitz_ficp_platform_data);
diff --git a/trunk/arch/arm/mach-pxa/spitz_pm.c b/trunk/arch/arm/mach-pxa/spitz_pm.c
index 4209ddf6da61..fc5a70c40358 100644
--- a/trunk/arch/arm/mach-pxa/spitz_pm.c
+++ b/trunk/arch/arm/mach-pxa/spitz_pm.c
@@ -24,10 +24,9 @@
#include
#include
-#include
-
+#include
+#include
#include "sharpsl.h"
-#include "generic.h"
#define SHARPSL_CHARGE_ON_VOLT 0x99 /* 2.9V */
#define SHARPSL_CHARGE_ON_TEMP 0xe0 /* 2.9V */
@@ -38,17 +37,10 @@
static int spitz_last_ac_status;
-static struct gpio spitz_charger_gpios[] = {
- { SPITZ_GPIO_KEY_INT, GPIOF_IN, "Keyboard Interrupt" },
- { SPITZ_GPIO_SYNC, GPIOF_IN, "Sync" },
- { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
- { SPITZ_GPIO_JK_B, GPIOF_OUT_INIT_LOW, "JK B" },
- { SPITZ_GPIO_CHRG_ON, GPIOF_OUT_INIT_LOW, "Charger On" },
-};
-
static void spitz_charger_init(void)
{
- gpio_request_array(ARRAY_AND_SIZE(spitz_charger_gpios));
+ pxa_gpio_mode(SPITZ_GPIO_KEY_INT | GPIO_IN);
+ pxa_gpio_mode(SPITZ_GPIO_SYNC | GPIO_IN);
}
static void spitz_measure_temp(int on)
@@ -84,11 +76,6 @@ static void spitz_discharge1(int on)
gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
}
-static unsigned long gpio18_config[] = {
- GPIO18_RDY,
- GPIO18_GPIO,
-};
-
static void spitz_presuspend(void)
{
spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
@@ -110,9 +97,7 @@ static void spitz_presuspend(void)
PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
- pxa2xx_mfp_config(&gpio18_config[0], 1);
- gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
- gpio_free(18);
+ pxa_gpio_mode(GPIO18_RDY|GPIO_OUT | GPIO_DFLT_HIGH);
PRER = GPIO_bit(SPITZ_GPIO_KEY_INT);
PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
@@ -129,7 +114,8 @@ static void spitz_presuspend(void)
static void spitz_postsuspend(void)
{
- pxa2xx_mfp_config(&gpio18_config[1], 1);
+ pxa_gpio_mode(GPIO18_RDY_MD);
+ pxa_gpio_mode(10 | GPIO_IN);
}
static int spitz_should_wakeup(unsigned int resume_on_alarm)
diff --git a/trunk/arch/arm/mach-pxa/ssp.c b/trunk/arch/arm/mach-pxa/ssp.c
new file mode 100644
index 000000000000..a81d6dbf662d
--- /dev/null
+++ b/trunk/arch/arm/mach-pxa/ssp.c
@@ -0,0 +1,510 @@
+/*
+ * linux/arch/arm/mach-pxa/ssp.c
+ *
+ * based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
+ *
+ * Copyright (C) 2003 Russell King.
+ * Copyright (C) 2003 Wolfson Microelectronics PLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * PXA2xx SSP driver. This provides the generic core for simple
+ * IO-based SSP applications and allows easy port setup for DMA access.
+ *
+ * Author: Liam Girdwood
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_PXA_SSP_LEGACY
+
+#define TIMEOUT 100000
+
+static irqreturn_t ssp_interrupt(int irq, void *dev_id)
+{
+ struct ssp_dev *dev = dev_id;
+ struct ssp_device *ssp = dev->ssp;
+ unsigned int status;
+
+ status = __raw_readl(ssp->mmio_base + SSSR);
+ __raw_writel(status, ssp->mmio_base + SSSR);
+
+ if (status & SSSR_ROR)
+ printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
+
+ if (status & SSSR_TUR)
+ printk(KERN_WARNING "SSP(%d): transmitter underrun\n", dev->port);
+
+ if (status & SSSR_BCE)
+ printk(KERN_WARNING "SSP(%d): bit count error\n", dev->port);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * ssp_write_word - write a word to the SSP port
+ * @data: 32-bit, MSB justified data to write.
+ *
+ * Wait for a free entry in the SSP transmit FIFO, and write a data
+ * word to the SSP port.
+ *
+ * The caller is expected to perform the necessary locking.
+ *
+ * Returns:
+ * %-ETIMEDOUT timeout occurred
+ * 0 success
+ */
+int ssp_write_word(struct ssp_dev *dev, u32 data)
+{
+ struct ssp_device *ssp = dev->ssp;
+ int timeout = TIMEOUT;
+
+ while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
+ if (!--timeout)
+ return -ETIMEDOUT;
+ cpu_relax();
+ }
+
+ __raw_writel(data, ssp->mmio_base + SSDR);
+
+ return 0;
+}
+
+/**
+ * ssp_read_word - read a word from the SSP port
+ *
+ * Wait for a data word in the SSP receive FIFO, and return the
+ * received data. Data is LSB justified.
+ *
+ * Note: Currently, if data is not expected to be received, this
+ * function will wait for ever.
+ *
+ * The caller is expected to perform the necessary locking.
+ *
+ * Returns:
+ * %-ETIMEDOUT timeout occurred
+ * 32-bit data success
+ */
+int ssp_read_word(struct ssp_dev *dev, u32 *data)
+{
+ struct ssp_device *ssp = dev->ssp;
+ int timeout = TIMEOUT;
+
+ while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
+ if (!--timeout)
+ return -ETIMEDOUT;
+ cpu_relax();
+ }
+
+ *data = __raw_readl(ssp->mmio_base + SSDR);
+ return 0;
+}
+
+/**
+ * ssp_flush - flush the transmit and receive FIFOs
+ *
+ * Wait for the SSP to idle, and ensure that the receive FIFO
+ * is empty.
+ *
+ * The caller is expected to perform the necessary locking.
+ */
+int ssp_flush(struct ssp_dev *dev)
+{
+ struct ssp_device *ssp = dev->ssp;
+ int timeout = TIMEOUT * 2;
+
+ /* ensure TX FIFO is empty instead of not full */
+ if (cpu_is_pxa3xx()) {
+ while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) {
+ if (!--timeout)
+ return -ETIMEDOUT;
+ cpu_relax();
+ }
+ timeout = TIMEOUT * 2;
+ }
+
+ do {
+ while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
+ if (!--timeout)
+ return -ETIMEDOUT;
+ (void)__raw_readl(ssp->mmio_base + SSDR);
+ }
+ if (!--timeout)
+ return -ETIMEDOUT;
+ } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
+
+ return 0;
+}
+
+/**
+ * ssp_enable - enable the SSP port
+ *
+ * Turn on the SSP port.
+ */
+void ssp_enable(struct ssp_dev *dev)
+{
+ struct ssp_device *ssp = dev->ssp;
+ uint32_t sscr0;
+
+ sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
+ sscr0 |= SSCR0_SSE;
+ __raw_writel(sscr0, ssp->mmio_base + SSCR0);
+}
+
+/**
+ * ssp_disable - shut down the SSP port
+ *
+ * Turn off the SSP port, optionally powering it down.
+ */
+void ssp_disable(struct ssp_dev *dev)
+{
+ struct ssp_device *ssp = dev->ssp;
+ uint32_t sscr0;
+
+ sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
+ sscr0 &= ~SSCR0_SSE;
+ __raw_writel(sscr0, ssp->mmio_base + SSCR0);
+}
+
+/**
+ * ssp_save_state - save the SSP configuration
+ * @ssp: pointer to structure to save SSP configuration
+ *
+ * Save the configured SSP state for suspend.
+ */
+void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
+{
+ struct ssp_device *ssp = dev->ssp;
+
+ state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
+ state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
+ state->to = __raw_readl(ssp->mmio_base + SSTO);
+ state->psp = __raw_readl(ssp->mmio_base + SSPSP);
+
+ ssp_disable(dev);
+}
+
+/**
+ * ssp_restore_state - restore a previously saved SSP configuration
+ * @ssp: pointer to configuration saved by ssp_save_state
+ *
+ * Restore the SSP configuration saved previously by ssp_save_state.
+ */
+void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
+{
+ struct ssp_device *ssp = dev->ssp;
+ uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
+
+ __raw_writel(sssr, ssp->mmio_base + SSSR);
+
+ __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
+ __raw_writel(state->cr1, ssp->mmio_base + SSCR1);
+ __raw_writel(state->to, ssp->mmio_base + SSTO);
+ __raw_writel(state->psp, ssp->mmio_base + SSPSP);
+ __raw_writel(state->cr0, ssp->mmio_base + SSCR0);
+}
+
+/**
+ * ssp_config - configure SSP port settings
+ * @mode: port operating mode
+ * @flags: port config flags
+ * @psp_flags: port PSP config flags
+ * @speed: port speed
+ *
+ * Port MUST be disabled by ssp_disable before making any config changes.
+ */
+int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
+{
+ struct ssp_device *ssp = dev->ssp;
+
+ dev->mode = mode;
+ dev->flags = flags;
+ dev->psp_flags = psp_flags;
+ dev->speed = speed;
+
+ /* set up port type, speed, port settings */
+ __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
+ __raw_writel(dev->flags, ssp->mmio_base + SSCR1);
+ __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
+
+ return 0;
+}
+
+/**
+ * ssp_init - setup the SSP port
+ *
+ * initialise and claim resources for the SSP port.
+ *
+ * Returns:
+ * %-ENODEV if the SSP port is unavailable
+ * %-EBUSY if the resources are already in use
+ * %0 on success
+ */
+int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags)
+{
+ struct ssp_device *ssp;
+ int ret;
+
+ ssp = ssp_request(port, "SSP");
+ if (ssp == NULL)
+ return -ENODEV;
+
+ dev->ssp = ssp;
+ dev->port = port;
+
+ /* do we need to get irq */
+ if (!(init_flags & SSP_NO_IRQ)) {
+ ret = request_irq(ssp->irq, ssp_interrupt,
+ 0, "SSP", dev);
+ if (ret)
+ goto out_region;
+ dev->irq = ssp->irq;
+ } else
+ dev->irq = NO_IRQ;
+
+ /* turn on SSP port clock */
+ clk_enable(ssp->clk);
+ return 0;
+
+out_region:
+ ssp_free(ssp);
+ return ret;
+}
+
+/**
+ * ssp_exit - undo the effects of ssp_init
+ *
+ * release and free resources for the SSP port.
+ */
+void ssp_exit(struct ssp_dev *dev)
+{
+ struct ssp_device *ssp = dev->ssp;
+
+ ssp_disable(dev);
+ if (dev->irq != NO_IRQ)
+ free_irq(dev->irq, dev);
+ clk_disable(ssp->clk);
+ ssp_free(ssp);
+}
+#endif /* CONFIG_PXA_SSP_LEGACY */
+
+static DEFINE_MUTEX(ssp_lock);
+static LIST_HEAD(ssp_list);
+
+struct ssp_device *ssp_request(int port, const char *label)
+{
+ struct ssp_device *ssp = NULL;
+
+ mutex_lock(&ssp_lock);
+
+ list_for_each_entry(ssp, &ssp_list, node) {
+ if (ssp->port_id == port && ssp->use_count == 0) {
+ ssp->use_count++;
+ ssp->label = label;
+ break;
+ }
+ }
+
+ mutex_unlock(&ssp_lock);
+
+ if (&ssp->node == &ssp_list)
+ return NULL;
+
+ return ssp;
+}
+EXPORT_SYMBOL(ssp_request);
+
+void ssp_free(struct ssp_device *ssp)
+{
+ mutex_lock(&ssp_lock);
+ if (ssp->use_count) {
+ ssp->use_count--;
+ ssp->label = NULL;
+ } else
+ dev_err(&ssp->pdev->dev, "device already free\n");
+ mutex_unlock(&ssp_lock);
+}
+EXPORT_SYMBOL(ssp_free);
+
+static int __devinit ssp_probe(struct platform_device *pdev)
+{
+ const struct platform_device_id *id = platform_get_device_id(pdev);
+ struct resource *res;
+ struct ssp_device *ssp;
+ int ret = 0;
+
+ ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
+ if (ssp == NULL) {
+ dev_err(&pdev->dev, "failed to allocate memory");
+ return -ENOMEM;
+ }
+ ssp->pdev = pdev;
+
+ ssp->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(ssp->clk)) {
+ ret = PTR_ERR(ssp->clk);
+ goto err_free;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no memory resource defined\n");
+ ret = -ENODEV;
+ goto err_free_clk;
+ }
+
+ res = request_mem_region(res->start, res->end - res->start + 1,
+ pdev->name);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "failed to request memory resource\n");
+ ret = -EBUSY;
+ goto err_free_clk;
+ }
+
+ ssp->phys_base = res->start;
+
+ ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
+ if (ssp->mmio_base == NULL) {
+ dev_err(&pdev->dev, "failed to ioremap() registers\n");
+ ret = -ENODEV;
+ goto err_free_mem;
+ }
+
+ ssp->irq = platform_get_irq(pdev, 0);
+ if (ssp->irq < 0) {
+ dev_err(&pdev->dev, "no IRQ resource defined\n");
+ ret = -ENODEV;
+ goto err_free_io;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
+ ret = -ENODEV;
+ goto err_free_io;
+ }
+ ssp->drcmr_rx = res->start;
+
+ res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
+ ret = -ENODEV;
+ goto err_free_io;
+ }
+ ssp->drcmr_tx = res->start;
+
+ /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
+ * starts from 0, do a translation here
+ */
+ ssp->port_id = pdev->id + 1;
+ ssp->use_count = 0;
+ ssp->type = (int)id->driver_data;
+
+ mutex_lock(&ssp_lock);
+ list_add(&ssp->node, &ssp_list);
+ mutex_unlock(&ssp_lock);
+
+ platform_set_drvdata(pdev, ssp);
+ return 0;
+
+err_free_io:
+ iounmap(ssp->mmio_base);
+err_free_mem:
+ release_mem_region(res->start, res->end - res->start + 1);
+err_free_clk:
+ clk_put(ssp->clk);
+err_free:
+ kfree(ssp);
+ return ret;
+}
+
+static int __devexit ssp_remove(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct ssp_device *ssp;
+
+ ssp = platform_get_drvdata(pdev);
+ if (ssp == NULL)
+ return -ENODEV;
+
+ iounmap(ssp->mmio_base);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(res->start, res->end - res->start + 1);
+
+ clk_put(ssp->clk);
+
+ mutex_lock(&ssp_lock);
+ list_del(&ssp->node);
+ mutex_unlock(&ssp_lock);
+
+ kfree(ssp);
+ return 0;
+}
+
+static const struct platform_device_id ssp_id_table[] = {
+ { "pxa25x-ssp", PXA25x_SSP },
+ { "pxa25x-nssp", PXA25x_NSSP },
+ { "pxa27x-ssp", PXA27x_SSP },
+ { },
+};
+
+static struct platform_driver ssp_driver = {
+ .probe = ssp_probe,
+ .remove = __devexit_p(ssp_remove),
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "pxa2xx-ssp",
+ },
+ .id_table = ssp_id_table,
+};
+
+static int __init pxa_ssp_init(void)
+{
+ return platform_driver_register(&ssp_driver);
+}
+
+static void __exit pxa_ssp_exit(void)
+{
+ platform_driver_unregister(&ssp_driver);
+}
+
+arch_initcall(pxa_ssp_init);
+module_exit(pxa_ssp_exit);
+
+#ifdef CONFIG_PXA_SSP_LEGACY
+EXPORT_SYMBOL(ssp_write_word);
+EXPORT_SYMBOL(ssp_read_word);
+EXPORT_SYMBOL(ssp_flush);
+EXPORT_SYMBOL(ssp_enable);
+EXPORT_SYMBOL(ssp_disable);
+EXPORT_SYMBOL(ssp_save_state);
+EXPORT_SYMBOL(ssp_restore_state);
+EXPORT_SYMBOL(ssp_init);
+EXPORT_SYMBOL(ssp_exit);
+EXPORT_SYMBOL(ssp_config);
+#endif
+
+MODULE_DESCRIPTION("PXA SSP driver");
+MODULE_AUTHOR("Liam Girdwood");
+MODULE_LICENSE("GPL");
+
diff --git a/trunk/arch/arm/mach-pxa/stargate2.c b/trunk/arch/arm/mach-pxa/stargate2.c
index af40d2a12d37..2041eb1d90ba 100644
--- a/trunk/arch/arm/mach-pxa/stargate2.c
+++ b/trunk/arch/arm/mach-pxa/stargate2.c
@@ -464,6 +464,8 @@ static struct platform_device smc91x_device = {
+static struct pxamci_platform_data stargate2_mci_platform_data;
+
/*
* The card detect interrupt isn't debounced so we delay it by 250ms
* to give the card a chance to fully insert / eject.
@@ -487,6 +489,8 @@ static int stargate2_mci_init(struct device *dev,
goto free_power_en;
}
gpio_direction_input(SG2_GPIO_nSD_DETECT);
+ /* Delay to allow for full insertion */
+ stargate2_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT),
stargate2_detect_int,
@@ -525,7 +529,6 @@ static void stargate2_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data stargate2_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = stargate2_mci_init,
.setpower = stargate2_mci_setpower,
diff --git a/trunk/arch/arm/mach-pxa/tosa.c b/trunk/arch/arm/mach-pxa/tosa.c
index 7512b822c6ca..ad552791c4ce 100644
--- a/trunk/arch/arm/mach-pxa/tosa.c
+++ b/trunk/arch/arm/mach-pxa/tosa.c
@@ -275,7 +275,6 @@ static void tosa_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data tosa_mci_platform_data = {
- .detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = tosa_mci_init,
.exit = tosa_mci_exit,
@@ -927,6 +926,7 @@ static void __init tosa_init(void)
dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12);
dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
+ tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&tosa_mci_platform_data);
pxa_set_udc_info(&udc_info);
pxa_set_ficp_info(&tosa_ficp_platform_data);
diff --git a/trunk/arch/arm/mach-pxa/trizeps4.c b/trunk/arch/arm/mach-pxa/trizeps4.c
index 69689112eae7..797f2544d0ce 100644
--- a/trunk/arch/arm/mach-pxa/trizeps4.c
+++ b/trunk/arch/arm/mach-pxa/trizeps4.c
@@ -349,7 +349,7 @@ static void trizeps4_mci_exit(struct device *dev, void *data)
static struct pxamci_platform_data trizeps4_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
- .detect_delay_ms= 10,
+ .detect_delay = 1,
.init = trizeps4_mci_init,
.exit = trizeps4_mci_exit,
.get_ro = NULL, /* write-protection not supported */
diff --git a/trunk/arch/arm/mach-pxa/viper.c b/trunk/arch/arm/mach-pxa/viper.c
index e90114a7e246..9e0c5c3988a1 100644
--- a/trunk/arch/arm/mach-pxa/viper.c
+++ b/trunk/arch/arm/mach-pxa/viper.c
@@ -34,7 +34,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -455,7 +454,7 @@ static struct i2c_gpio_platform_data i2c_bus_data = {
.sda_pin = VIPER_RTC_I2C_SDA_GPIO,
.scl_pin = VIPER_RTC_I2C_SCL_GPIO,
.udelay = 10,
- .timeout = HZ,
+ .timeout = 100,
};
static struct platform_device i2c_bus_device = {
@@ -780,7 +779,7 @@ static void __init viper_tpm_init(void)
.sda_pin = VIPER_TPM_I2C_SDA_GPIO,
.scl_pin = VIPER_TPM_I2C_SCL_GPIO,
.udelay = 10,
- .timeout = HZ,
+ .timeout = 100,
};
char *errstr;
diff --git a/trunk/arch/arm/mach-pxa/vpac270.c b/trunk/arch/arm/mach-pxa/vpac270.c
deleted file mode 100644
index 9884fa978f16..000000000000
--- a/trunk/arch/arm/mach-pxa/vpac270.c
+++ /dev/null
@@ -1,615 +0,0 @@
-/*
- * Hardware definitions for Voipac PXA270
- *
- * Copyright (C) 2010
- * Marek Vasut
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include