From a0aa525d90f01430daf8e2cedff2b201e6007d7c Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Thu, 25 Oct 2012 12:15:47 -0700
Subject: [PATCH] --- yaml --- r: 345274 b: refs/heads/master c:
 3ac7831314eba873d60b58718123c503f6961337 h: refs/heads/master v: v3

---
 [refs]                                        | 2 +-
 trunk/drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index dcaa0091d88d..c87d979fa81b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9a28977181724ebbd9bdc45291cf29da55a729ee
+refs/heads/master: 3ac7831314eba873d60b58718123c503f6961337
diff --git a/trunk/drivers/gpu/drm/i915/intel_ringbuffer.c b/trunk/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1591955044c8..f7617a4e005f 100644
--- a/trunk/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/trunk/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -245,7 +245,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);