From a0c0db7702b5fe5378c1da6315b37ecdc427e91e Mon Sep 17 00:00:00 2001
From: Mike Miller <mike.miller@hp.com>
Date: Fri, 21 Oct 2011 08:19:43 +0200
Subject: [PATCH] --- yaml --- r: 273847 b: refs/heads/master c:
 c4853efec665134b2e6fc9c13447323240980351 h: refs/heads/master i:   273845:
 cf9728100b3efc4965eb9c33bd96b1bd72efed38   273843:
 22651f8586a2a1397a42c078151cbe10dc0a1aaf   273839:
 8ff50d5c979e0b8b872edddd538add90d34bf278 v: v3

---
 [refs]                    | 2 +-
 trunk/drivers/scsi/hpsa.c | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index e926da28cea8..020964861fef 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ab5dbebe33e0c353e8545f09c34553ac3351dad6
+refs/heads/master: c4853efec665134b2e6fc9c13447323240980351
diff --git a/trunk/drivers/scsi/hpsa.c b/trunk/drivers/scsi/hpsa.c
index ec61bdb833ac..381929813cbd 100644
--- a/trunk/drivers/scsi/hpsa.c
+++ b/trunk/drivers/scsi/hpsa.c
@@ -3283,6 +3283,13 @@ static int hpsa_controller_hard_reset(struct pci_dev *pdev,
 		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
 		pmcsr |= PCI_D0;
 		pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
+
+		/*
+		 * The P600 requires a small delay when changing states.
+		 * Otherwise we may think the board did not reset and we bail.
+		 * This for kdump only and is particular to the P600.
+		 */
+		msleep(500);
 	}
 	return 0;
 }