From a0ec4d188aaa6f1f5ea68bd199146188bb3ce44f Mon Sep 17 00:00:00 2001
From: Rahul Sharma <rahul.sharma@samsung.com>
Date: Mon, 29 Oct 2012 21:51:51 +0900
Subject: [PATCH] --- yaml --- r: 342288 b: refs/heads/master c:
 cf3a97b4e4c4601d043ca1549c27e5fe18f55dde h: refs/heads/master v: v3

---
 [refs]                                     |  2 +-
 trunk/arch/arm/mach-exynos/clock-exynos5.c | 14 ++++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 3f4d14870596..f5060aebaf1d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 62a1f83f0cbbc9c2e2776b4ad91ccb2f500b6a0b
+refs/heads/master: cf3a97b4e4c4601d043ca1549c27e5fe18f55dde
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos5.c b/trunk/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1ee1b8d..a86f20fb05a1 100644
--- a/trunk/arch/arm/mach-exynos/clock-exynos5.c
+++ b/trunk/arch/arm/mach-exynos/clock-exynos5.c
@@ -196,6 +196,11 @@ static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 }
 
+static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -669,12 +674,17 @@ static struct clk exynos5_init_clocks_off[] = {
 		.ctrlbit	= (1 << 0),
 	}, {
 		.name		= "hdmi",
-		.devname	= "exynos4-hdmi",
+		.devname	= "exynos5-hdmi",
 		.enable		= exynos5_clk_ip_disp1_ctrl,
 		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "hdmiphy",
+		.devname	= "exynos5-hdmi",
+		.enable		= exynos5_clk_hdmiphy_ctrl,
+		.ctrlbit	= (1 << 0),
 	}, {
 		.name		= "mixer",
-		.devname	= "s5p-mixer",
+		.devname	= "exynos5-mixer",
 		.enable		= exynos5_clk_ip_disp1_ctrl,
 		.ctrlbit	= (1 << 5),
 	}, {