From a1101b0d5b43bd54a5a236bacc34650a9528d211 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 22 Jul 2009 12:54:59 -0700 Subject: [PATCH] --- yaml --- r: 156529 b: refs/heads/master c: f360132626b11d0dc60814033873ca0e3111677c h: refs/heads/master i: 156527: a0923eed9096dd6d22230fbd17930653e8534ba2 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 3252d57bbe96..8fc62a70ba97 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 67941da28d59cca6817d35823fcb1e3e4eed030e +refs/heads/master: f360132626b11d0dc60814033873ca0e3111677c diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index a9f1307d32d8..1da7b0b9ed31 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -2026,6 +2026,9 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane) size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - (dsparb & 0x1ff); size >>= 1; /* Convert to cachelines */ + } else if (IS_845G(dev)) { + size = dsparb & 0x7f; + size >>= 2; /* Convert to cachelines */ } else { size = dsparb & 0x7f; size >>= 1; /* Convert to cachelines */ @@ -2125,14 +2128,16 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int pixel_size) { struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; + uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; int planea_wm; i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0); planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, pixel_size, latency_ns); - fwater_lo = fwater_lo | planea_wm; + fwater_lo |= (3<<8) | planea_wm; + + DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm); I915_WRITE(FW_BLC, fwater_lo); }