diff --git a/[refs] b/[refs] index f7411d02084f..7bf90a7ac466 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3a8daaa49fb71d90e45d1e86d7f9f9e298bda05c +refs/heads/master: 210b94e864de9d50ed08603a1ff0834603f309e0 diff --git a/trunk/arch/arm/mach-ns9xxx/Kconfig b/trunk/arch/arm/mach-ns9xxx/Kconfig index 8584ed107991..83c0efa7399c 100644 --- a/trunk/arch/arm/mach-ns9xxx/Kconfig +++ b/trunk/arch/arm/mach-ns9xxx/Kconfig @@ -2,6 +2,9 @@ if ARCH_NS9XXX menu "NS9xxx Implementations" +config NS9XXX_HAVE_SERIAL8250 + bool + config MACH_CC9P9360DEV bool "ConnectCore 9P 9360 on an A9M9750 Devboard" select PROCESSOR_NS9360 @@ -23,6 +26,7 @@ config PROCESSOR_NS9360 config BOARD_A9M9750DEV bool + select NS9XXX_HAVE_SERIAL8250 config BOARD_JSCC9P9360 bool diff --git a/trunk/arch/arm/mach-ns9xxx/Makefile b/trunk/arch/arm/mach-ns9xxx/Makefile index 6fb82b855a55..ca2c68dede1d 100644 --- a/trunk/arch/arm/mach-ns9xxx/Makefile +++ b/trunk/arch/arm/mach-ns9xxx/Makefile @@ -5,3 +5,6 @@ obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o + +# platform devices +obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o diff --git a/trunk/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/trunk/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0f65177f9e5f..14a06da25ac2 100644 --- a/trunk/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/trunk/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -8,8 +8,6 @@ * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. */ -#include -#include #include #include @@ -126,59 +124,6 @@ void __init board_a9m9750dev_init_irq(void) a9m9750dev_fpga_demux_handler); } -static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = { - { - .iobase = FPGA_UARTA_BASE, - .membase = (unsigned char*)FPGA_UARTA_BASE, - .mapbase = FPGA_UARTA_BASE, - .irq = IRQ_FPGA_UARTA, - .iotype = UPIO_MEM, - .uartclk = 18432000, - .regshift = 0, - .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, - }, { - .iobase = FPGA_UARTB_BASE, - .membase = (unsigned char*)FPGA_UARTB_BASE, - .mapbase = FPGA_UARTB_BASE, - .irq = IRQ_FPGA_UARTB, - .iotype = UPIO_MEM, - .uartclk = 18432000, - .regshift = 0, - .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, - }, { - .iobase = FPGA_UARTC_BASE, - .membase = (unsigned char*)FPGA_UARTC_BASE, - .mapbase = FPGA_UARTC_BASE, - .irq = IRQ_FPGA_UARTC, - .iotype = UPIO_MEM, - .uartclk = 18432000, - .regshift = 0, - .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, - }, { - .iobase = FPGA_UARTD_BASE, - .membase = (unsigned char*)FPGA_UARTD_BASE, - .mapbase = FPGA_UARTD_BASE, - .irq = IRQ_FPGA_UARTD, - .iotype = UPIO_MEM, - .uartclk = 18432000, - .regshift = 0, - .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ, - }, { - /* end marker */ - }, -}; - -static struct platform_device board_a9m9750dev_serial_device = { - .name = "serial8250", - .dev = { - .platform_data = board_a9m9750dev_serial8250_port, - }, -}; - -static struct platform_device *board_a9m9750dev_devices[] __initdata = { - &board_a9m9750dev_serial_device, -}; - void __init board_a9m9750dev_init_machine(void) { u32 reg; @@ -210,7 +155,4 @@ void __init board_a9m9750dev_init_machine(void) __raw_writel(0x2, MEM_SMOED(0)); __raw_writel(0x6, MEM_SMRD(0)); __raw_writel(0x6, MEM_SMWD(0)); - - platform_add_devices(board_a9m9750dev_devices, - ARRAY_SIZE(board_a9m9750dev_devices)); } diff --git a/trunk/arch/arm/mach-ns9xxx/plat-serial8250.c b/trunk/arch/arm/mach-ns9xxx/plat-serial8250.c new file mode 100644 index 000000000000..5aa5d9baf8c8 --- /dev/null +++ b/trunk/arch/arm/mach-ns9xxx/plat-serial8250.c @@ -0,0 +1,69 @@ +/* + * arch/arm/mach-ns9xxx/plat-serial8250.c + * + * Copyright (C) 2008 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#include +#include + +#include +#include + +#define DRIVER_NAME "serial8250" + +static int __init ns9xxx_plat_serial8250_init(void) +{ + struct plat_serial8250_port *pdata; + struct platform_device *pdev; + int ret = -ENOMEM; + int i; + + if (!board_is_a9m9750dev()) + return -ENODEV; + + pdev = platform_device_alloc(DRIVER_NAME, 0); + if (!pdev) + goto err; + + pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); + if (!pdata) + goto err; + + pdev->dev.platform_data = pdata; + + pdata[0].iobase = FPGA_UARTA_BASE; + pdata[1].iobase = FPGA_UARTB_BASE; + pdata[2].iobase = FPGA_UARTC_BASE; + pdata[3].iobase = FPGA_UARTD_BASE; + + for (i = 0; i < 4; ++i) { + pdata[i].membase = (void __iomem *)pdata[i].iobase; + pdata[i].mapbase = pdata[i].iobase; + pdata[i].iotype = UPIO_MEM; + pdata[i].uartclk = 18432000; + pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + } + + pdata[0].irq = IRQ_FPGA_UARTA; + pdata[1].irq = IRQ_FPGA_UARTB; + pdata[2].irq = IRQ_FPGA_UARTC; + pdata[3].irq = IRQ_FPGA_UARTD; + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + + printk(KERN_WARNING "Could not add %s (errno=%d)\n", + DRIVER_NAME, ret); + } + + return 0; +} + +arch_initcall(ns9xxx_plat_serial8250_init); diff --git a/trunk/arch/arm/plat-mxc/Kconfig b/trunk/arch/arm/plat-mxc/Kconfig index bb6e12738fb3..03a65c0dfb60 100644 --- a/trunk/arch/arm/plat-mxc/Kconfig +++ b/trunk/arch/arm/plat-mxc/Kconfig @@ -4,7 +4,7 @@ menu "Freescale MXC Implementations" choice prompt "MXC/iMX System Type" - default ARCH_MX3 + default 0 config ARCH_MX3 bool "MX3-based" diff --git a/trunk/arch/arm/plat-mxc/Makefile b/trunk/arch/arm/plat-mxc/Makefile index f96dc0362068..66ad9c2b6d64 100644 --- a/trunk/arch/arm/plat-mxc/Makefile +++ b/trunk/arch/arm/plat-mxc/Makefile @@ -4,3 +4,7 @@ # Common support obj-y := irq.o + +obj-m := +obj-n := +obj- := diff --git a/trunk/arch/arm/plat-mxc/irq.c b/trunk/arch/arm/plat-mxc/irq.c index 2ad5a6917b3f..87d253bc3d3c 100644 --- a/trunk/arch/arm/plat-mxc/irq.c +++ b/trunk/arch/arm/plat-mxc/irq.c @@ -19,13 +19,21 @@ #include #include -/* Disable interrupt number "irq" in the AVIC */ +/*! + * Disable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ static void mxc_mask_irq(unsigned int irq) { __raw_writel(irq, AVIC_INTDISNUM); } -/* Enable interrupt number "irq" in the AVIC */ +/*! + * Enable interrupt number "irq" in the AVIC + * + * @param irq interrupt source number + */ static void mxc_unmask_irq(unsigned int irq) { __raw_writel(irq, AVIC_INTENNUM); @@ -37,7 +45,7 @@ static struct irq_chip mxc_avic_chip = { .unmask = mxc_unmask_irq, }; -/* +/*! * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. diff --git a/trunk/drivers/serial/imx.c b/trunk/drivers/serial/imx.c index cf29a2d0ba4c..56af1f566a4c 100644 --- a/trunk/drivers/serial/imx.c +++ b/trunk/drivers/serial/imx.c @@ -166,6 +166,15 @@ #define SERIAL_IMX_MAJOR 204 #define MINOR_START 41 +#define NR_PORTS 2 + +#define IMX_ISR_PASS_LIMIT 256 + +/* + * This is the size of our serial port register set. + */ +#define UART_PORT_SIZE 0x100 + /* * This determines how often we check the modem status signals * for any change. They generally aren't connected to an IRQ @@ -349,60 +358,66 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) struct tty_struct *tty = sport->port.info->tty; unsigned long flags, temp; + rx = readl(sport->port.membase + URXD0); spin_lock_irqsave(&sport->port.lock,flags); - while (readl(sport->port.membase + USR2) & USR2_RDR) { + do { flg = TTY_NORMAL; sport->port.icount.rx++; - rx = readl(sport->port.membase + URXD0); - temp = readl(sport->port.membase + USR2); - if (temp & USR2_BRCD) { + if( temp & USR2_BRCD ) { writel(temp | USR2_BRCD, sport->port.membase + USR2); - if (uart_handle_break(&sport->port)) - continue; + if(uart_handle_break(&sport->port)) + goto ignore_char; } if (uart_handle_sysrq_char (&sport->port, (unsigned char)rx)) - continue; - - if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) { - if (rx & URXD_PRERR) - sport->port.icount.parity++; - else if (rx & URXD_FRMERR) - sport->port.icount.frame++; - if (rx & URXD_OVRRUN) - sport->port.icount.overrun++; - - if (rx & sport->port.ignore_status_mask) { - if (++ignored > 100) - goto out; - continue; - } - - rx &= sport->port.read_status_mask; - - if (rx & URXD_PRERR) - flg = TTY_PARITY; - else if (rx & URXD_FRMERR) - flg = TTY_FRAME; - if (rx & URXD_OVRRUN) - flg = TTY_OVERRUN; + goto ignore_char; -#ifdef SUPPORT_SYSRQ - sport->port.sysrq = 0; -#endif - } + if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) + goto handle_error; + error_return: tty_insert_flip_char(tty, rx, flg); - } + + ignore_char: + rx = readl(sport->port.membase + URXD0); + } while(rx & URXD_CHARRDY); out: spin_unlock_irqrestore(&sport->port.lock,flags); tty_flip_buffer_push(tty); return IRQ_HANDLED; + +handle_error: + if (rx & URXD_PRERR) + sport->port.icount.parity++; + else if (rx & URXD_FRMERR) + sport->port.icount.frame++; + if (rx & URXD_OVRRUN) + sport->port.icount.overrun++; + + if (rx & sport->port.ignore_status_mask) { + if (++ignored > 100) + goto out; + goto ignore_char; + } + + rx &= sport->port.read_status_mask; + + if (rx & URXD_PRERR) + flg = TTY_PARITY; + else if (rx & URXD_FRMERR) + flg = TTY_FRAME; + if (rx & URXD_OVRRUN) + flg = TTY_OVERRUN; + +#ifdef SUPPORT_SYSRQ + sport->port.sysrq = 0; +#endif + goto error_return; } /* @@ -531,7 +546,7 @@ static int imx_startup(struct uart_port *port) writel(USR1_RTSD, sport->port.membase + USR1); temp = readl(sport->port.membase + UCR1); - temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; + temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); writel(temp, sport->port.membase + UCR1); temp = readl(sport->port.membase + UCR2); @@ -716,11 +731,9 @@ static const char *imx_type(struct uart_port *port) */ static void imx_release_port(struct uart_port *port) { - struct platform_device *pdev = to_platform_device(port->dev); - struct resource *mmres; + struct imx_port *sport = (struct imx_port *)port; - mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(mmres->start, mmres->end - mmres->start + 1); + release_mem_region(sport->port.mapbase, UART_PORT_SIZE); } /* @@ -728,18 +741,10 @@ static void imx_release_port(struct uart_port *port) */ static int imx_request_port(struct uart_port *port) { - struct platform_device *pdev = to_platform_device(port->dev); - struct resource *mmres; - void *ret; - - mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mmres) - return -ENODEV; - - ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, - "imx-uart"); + struct imx_port *sport = (struct imx_port *)port; - return ret ? 0 : -EBUSY; + return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, + "imx-uart") != NULL ? 0 : -EBUSY; } /* @@ -810,7 +815,7 @@ static struct imx_port imx_ports[] = { .type = PORT_IMX, .iotype = UPIO_MEM, .membase = (void *)IMX_UART1_BASE, - .mapbase = 0x00206000, + .mapbase = IMX_UART1_BASE, /* FIXME */ .irq = UART1_MINT_RX, .uartclk = 16000000, .fifosize = 32, @@ -826,7 +831,7 @@ static struct imx_port imx_ports[] = { .type = PORT_IMX, .iotype = UPIO_MEM, .membase = (void *)IMX_UART2_BASE, - .mapbase = 0x00207000, + .mapbase = IMX_UART2_BASE, /* FIXME */ .irq = UART2_MINT_RX, .uartclk = 16000000, .fifosize = 32, diff --git a/trunk/include/asm-arm/arch-mxc/board-mx31ads.h b/trunk/include/asm-arm/arch-mxc/board-mx31ads.h index 8590127760a8..be29b83ad4ae 100644 --- a/trunk/include/asm-arm/arch-mxc/board-mx31ads.h +++ b/trunk/include/asm-arm/arch-mxc/board-mx31ads.h @@ -11,77 +11,107 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ -/* Base address of PBC controller */ +/*! + * @name PBC Controller parameters + */ +/*! @{ */ +/*! + * Base address of PBC controller + */ #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) /* Offsets for the PBC Controller register */ - -/* PBC Board status register offset */ +/*! + * PBC Board status register offset + */ #define PBC_BSTAT 0x000002 - -/* PBC Board control register 1 set address */ +/*! + * PBC Board control register 1 set address. + */ #define PBC_BCTRL1_SET 0x000004 - -/* PBC Board control register 1 clear address */ +/*! + * PBC Board control register 1 clear address. + */ #define PBC_BCTRL1_CLEAR 0x000006 - -/* PBC Board control register 2 set address */ +/*! + * PBC Board control register 2 set address. + */ #define PBC_BCTRL2_SET 0x000008 - -/* PBC Board control register 2 clear address */ +/*! + * PBC Board control register 2 clear address. + */ #define PBC_BCTRL2_CLEAR 0x00000A - -/* PBC Board control register 3 set address */ +/*! + * PBC Board control register 3 set address. + */ #define PBC_BCTRL3_SET 0x00000C - -/* PBC Board control register 3 clear address */ +/*! + * PBC Board control register 3 clear address. + */ #define PBC_BCTRL3_CLEAR 0x00000E - -/* PBC Board control register 4 set address */ +/*! + * PBC Board control register 4 set address. + */ #define PBC_BCTRL4_SET 0x000010 - -/* PBC Board control register 4 clear address */ +/*! + * PBC Board control register 4 clear address. + */ #define PBC_BCTRL4_CLEAR 0x000012 - -/* PBC Board status register 1 */ +/*! + * PBC Board status register 1. + */ #define PBC_BSTAT1 0x000014 - -/* PBC Board interrupt status register */ +/*! + * PBC Board interrupt status register. + */ #define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ +/*! + * PBC Board interrupt current status register. + */ #define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ +/*! + * PBC Interrupt mask register set address. + */ #define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ +/*! + * PBC Interrupt mask register clear address. + */ #define PBC_INTMASK_CLEAR 0x00001C -/* External UART A */ +/*! + * External UART A. + */ #define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ +/*! + * External UART B. + */ #define PBC_SC16C652_UARTB 0x010010 - -/* Ethernet Controller IO base address */ +/*! + * Ethernet Controller IO base address. + */ #define PBC_CS8900A_IOBASE 0x020000 - -/* Ethernet Controller Memory base address */ +/*! + * Ethernet Controller Memory base address. + */ #define PBC_CS8900A_MEMBASE 0x021000 - -/* Ethernet Controller DMA base address */ +/*! + * Ethernet Controller DMA base address. + */ #define PBC_CS8900A_DMABASE 0x022000 - -/* External chip select 0 */ +/*! + * External chip select 0. + */ #define PBC_XCS0 0x040000 - -/* LCD Display enable */ +/*! + * LCD Display enable. + */ #define PBC_LCD_EN_B 0x060000 - -/* Code test debug enable */ +/*! + * Code test debug enable. + */ #define PBC_CODE_B 0x070000 - -/* PSRAM memory select */ +/*! + * PSRAM memory select. + */ #define PBC_PSRAM_B 0x5000000 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) @@ -109,4 +139,4 @@ #define MXC_MAX_EXP_IO_LINES 16 -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ +#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/dma.h b/trunk/include/asm-arm/arch-mxc/dma.h index c822d569a05e..65e639d51d2b 100644 --- a/trunk/include/asm-arm/arch-mxc/dma.h +++ b/trunk/include/asm-arm/arch-mxc/dma.h @@ -11,4 +11,11 @@ #ifndef __ASM_ARCH_MXC_DMA_H__ #define __ASM_ARCH_MXC_DMA_H__ +/*! + * @file dma.h + * @brief This file contains Unified DMA API for all MXC platforms. + * The API is platform independent. + * + * @ingroup SDMA + */ #endif diff --git a/trunk/include/asm-arm/arch-mxc/hardware.h b/trunk/include/asm-arm/arch-mxc/hardware.h index e87ff0679d5e..3c09b92fef0d 100644 --- a/trunk/include/asm-arm/arch-mxc/hardware.h +++ b/trunk/include/asm-arm/arch-mxc/hardware.h @@ -8,24 +8,45 @@ * published by the Free Software Foundation. */ +/*! + * @file hardware.h + * @brief This file contains the hardware definitions of the board. + * + * @ingroup System + */ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ #include -#ifdef CONFIG_ARCH_MX3 -# include -#endif +#include #include +#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) + /* * --------------------------------------------------------------------------- * Board specific defines * --------------------------------------------------------------------------- */ -#ifdef CONFIG_MACH_MX31ADS -# include +#define MXC_EXP_IO_BASE (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES) + +#include + +#ifndef MXC_MAX_EXP_IO_LINES +#define MXC_MAX_EXP_IO_LINES 0 #endif -#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ +#define MXC_MAX_VIRTUAL_INTS 16 +#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) +#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE +#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) +#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) + +#define MXC_MAX_INTS (MXC_MAX_INT_LINES + \ + MXC_MAX_GPIO_LINES + \ + MXC_MAX_EXP_IO_LINES + \ + MXC_MAX_VIRTUAL_INTS) + +#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/io.h b/trunk/include/asm-arm/arch-mxc/io.h index 65b6810124c1..cf6c83a4b9f7 100644 --- a/trunk/include/asm-arm/arch-mxc/io.h +++ b/trunk/include/asm-arm/arch-mxc/io.h @@ -8,13 +8,24 @@ * published by the Free Software Foundation. */ +/*! + * @file io.h + * @brief This file contains some memory mapping macros. + * @note There is no real ISA or PCI buses. But have to define these macros + * for some drivers to compile. + * + * @ingroup System + */ + #ifndef __ASM_ARCH_MXC_IO_H__ #define __ASM_ARCH_MXC_IO_H__ -/* Allow IO space to be anywhere in the memory */ +/*! Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -/* io address mapping macro */ +/*! + * io address mapping macro + */ #define __io(a) ((void __iomem *)(a)) #define __mem_pci(a) (a) diff --git a/trunk/include/asm-arm/arch-mxc/irqs.h b/trunk/include/asm-arm/arch-mxc/irqs.h index b2c5205e1962..e4686c6bc4bf 100644 --- a/trunk/include/asm-arm/arch-mxc/irqs.h +++ b/trunk/include/asm-arm/arch-mxc/irqs.h @@ -13,17 +13,26 @@ #include +/*! + * @file irqs.h + * @brief This file defines the number of normal interrupts and fast interrupts + * + * @ingroup Interrupt + */ + #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) #define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE) #define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x) -/* Number of normal interrupts */ -#define NR_IRQS (MXC_MAX_INT_LINES + \ - MXC_MAX_GPIO_LINES + \ - MXC_MAX_VIRTUAL_INTS) +/*! + * Number of normal interrupts + */ +#define NR_IRQS MXC_MAX_INTS -/* Number of fast interrupts */ +/*! + * Number of fast interrupts + */ #define NR_FIQS MXC_MAX_INTS -#endif /* __ASM_ARCH_MXC_IRQS_H__ */ +#endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/memory.h b/trunk/include/asm-arm/arch-mxc/memory.h index 059f83023a10..c89aac83a407 100644 --- a/trunk/include/asm-arm/arch-mxc/memory.h +++ b/trunk/include/asm-arm/arch-mxc/memory.h @@ -13,17 +13,24 @@ #include -/* +/*! + * @file memory.h + * @brief This file contains macros needed by the Linux kernel and drivers. + * + * @ingroup Memory + */ + +/*! * Virtual view <-> DMA view memory address translations * This macro is used to translate the virtual address to an address * suitable to be passed to set_dma_addr() */ #define __virt_to_bus(a) __virt_to_phys(a) -/* +/*! * Used to convert an address for DMA operations to an address that the * kernel can use. */ #define __bus_to_virt(a) __phys_to_virt(a) -#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ +#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/mx31.h b/trunk/include/asm-arm/arch-mxc/mx31.h index 36a1af495bb3..85c49c9e5d15 100644 --- a/trunk/include/asm-arm/arch-mxc/mx31.h +++ b/trunk/include/asm-arm/arch-mxc/mx31.h @@ -317,8 +317,6 @@ #define MXC_MAX_INT_LINES 64 #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES -#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) -#define MXC_MAX_VIRTUAL_INTS 16 /*! * Number of GPIO port as defined in the IC Spec @@ -331,33 +329,7 @@ #define PROD_SIGNATURE 0x1 /* For MX31 */ -/* silicon revisions specific to i.MX31 */ -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_1_2 0x12 -#define CHIP_REV_1_3 0x13 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_1 0x21 -#define CHIP_REV_2_2 0x22 -#define CHIP_REV_2_3 0x23 -#define CHIP_REV_3_0 0x30 -#define CHIP_REV_3_1 0x31 -#define CHIP_REV_3_2 0x32 - #define SYSTEM_REV_MIN CHIP_REV_1_0 #define SYSTEM_REV_NUM 3 -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) - -/* this is a i.MX31 CPU */ -#define cpu_is_mx31() (1) - -extern unsigned int system_rev; - -static inline int mx31_revision(void) -{ - return system_rev; -} -#endif - -#endif /* __ASM_ARCH_MXC_MX31_H__ */ +#endif /* __ASM_ARCH_MXC_MX31_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/mxc.h b/trunk/include/asm-arm/arch-mxc/mxc.h index 146d3f60951a..0837f1f9ca31 100644 --- a/trunk/include/asm-arm/arch-mxc/mxc.h +++ b/trunk/include/asm-arm/arch-mxc/mxc.h @@ -15,11 +15,6 @@ #error "Do not include directly." #endif -/* clean up all things that are not used */ -#ifndef CONFIG_ARCH_MX3 -# define cpu_is_mx31() (0) -#endif - /* ***************************************** * GPT Register definitions * @@ -36,7 +31,9 @@ #define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20) #define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24) -/* GPT Control register bit definitions */ +/*! + * GPT Control register bit definitions + */ #define GPTCR_FO3 (1 << 31) #define GPTCR_FO2 (1 << 30) #define GPTCR_FO1 (1 << 29) @@ -149,4 +146,4 @@ #define IIM_PROD_REV_SH 3 #define IIM_PROD_REV_LEN 5 -#endif /* __ASM_ARCH_MXC_H__ */ +#endif /* __ASM_ARCH_MXC_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/system.h b/trunk/include/asm-arm/arch-mxc/system.h index bbfc37465fc5..109956b41aca 100644 --- a/trunk/include/asm-arm/arch-mxc/system.h +++ b/trunk/include/asm-arm/arch-mxc/system.h @@ -21,14 +21,30 @@ #ifndef __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__ +/*! + * @file system.h + * @brief This file contains idle and reset functions. + * + * @ingroup System + */ + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ static inline void arch_idle(void) { cpu_do_idle(); } +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ static inline void arch_reset(char mode) { cpu_reset(0); } -#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ +#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/trunk/include/asm-arm/arch-mxc/vmalloc.h b/trunk/include/asm-arm/arch-mxc/vmalloc.h index 62d97623412f..83a73da895eb 100644 --- a/trunk/include/asm-arm/arch-mxc/vmalloc.h +++ b/trunk/include/asm-arm/arch-mxc/vmalloc.h @@ -20,7 +20,17 @@ #ifndef __ASM_ARCH_MXC_VMALLOC_H__ #define __ASM_ARCH_MXC_VMALLOC_H__ -/* vmalloc ending address */ +/*! + * @file vmalloc.h + * + * @brief This file contains platform specific macros for vmalloc. + * + * @ingroup System + */ + +/*! + * vmalloc ending address + */ #define VMALLOC_END 0xF4000000 -#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ +#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */