diff --git a/[refs] b/[refs] index 0dc01d1c7ba8..ced5471108c4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ccff9b1db693062b0a9c9070f4304deb47ef215c +refs/heads/master: f78570dd6ad9563fffd24cc5e1808e1a1242f16e diff --git a/trunk/Documentation/DocBook/media/v4l/compat.xml b/trunk/Documentation/DocBook/media/v4l/compat.xml index 4fdf6b562d1c..c6ae4c9d0e0c 100644 --- a/trunk/Documentation/DocBook/media/v4l/compat.xml +++ b/trunk/Documentation/DocBook/media/v4l/compat.xml @@ -2582,10 +2582,6 @@ ioctls. Support for frequency band enumeration: &VIDIOC-ENUM-FREQ-BANDS; ioctl. - - Vendor and device specific media bus pixel formats. - . - diff --git a/trunk/Documentation/DocBook/media/v4l/controls.xml b/trunk/Documentation/DocBook/media/v4l/controls.xml index 7fe5be1d3bbb..272a5f718509 100644 --- a/trunk/Documentation/DocBook/media/v4l/controls.xml +++ b/trunk/Documentation/DocBook/media/v4l/controls.xml @@ -1586,6 +1586,7 @@ frame counter of the frame that is currently displayed (decoded). This value is the decoder is started. + V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE  @@ -2268,14 +2269,6 @@ encoder or editing process may produce.". Applicable to the MPEG1, MPEG2, MPEG4 encoders. - - - V4L2_CID_MPEG_VIDEO_VBV_DELAY  - integer - Sets the initial delay in milliseconds for -VBV buffer control. - - V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE  @@ -2341,265 +2334,6 @@ Applicable to the MPEG4 decoder. vop_time_increment value for MPEG4. Applicable to the MPEG4 encoder. - - - V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING  - boolean - - Enable generation of frame packing supplemental enhancement information in the encoded bitstream. -The frame packing SEI message contains the arrangement of L and R planes for 3D viewing. Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0  - boolean - - Sets current frame as frame0 in frame packing SEI. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE  - enum v4l2_mpeg_video_h264_sei_fp_arrangement_type - - Frame packing arrangement type for H264 SEI. -Applicable to the H264 encoder. -Possible values are: - - - - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHEKERBOARD  - Pixels are alternatively from L and R. - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN  - L and R are interlaced by column. - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW  - L and R are interlaced by row. - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE  - L is on the left, R on the right. - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM  - L is on top, R on bottom. - - - V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL  - One view per frame. - - - - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO  - boolean - - Enables flexible macroblock ordering in the encoded bitstream. It is a technique -used for restructuring the ordering of macroblocks in pictures. Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE  - enum v4l2_mpeg_video_h264_fmo_map_type - - When using FMO, the map type divides the image in different scan patterns of macroblocks. -Applicable to the H264 encoder. -Possible values are: - - - - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES  - Slices are interleaved one after other with macroblocks in run length order. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES  - Scatters the macroblocks based on a mathematical function known to both encoder and decoder. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER  - Macroblocks arranged in rectangular areas or regions of interest. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT  - Slice groups grow in a cyclic way from centre to outwards. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN  - Slice groups grow in raster scan pattern from left to right. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN  - Slice groups grow in wipe scan pattern from top to bottom. - - - V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT  - User defined map type. - - - - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP  - integer - - Number of slice groups in FMO. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION  - enum v4l2_mpeg_video_h264_fmo_change_dir - - Specifies a direction of the slice group change for raster and wipe maps. -Applicable to the H264 encoder. -Possible values are: - - - - - - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT  - Raster scan or wipe right. - - - V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT  - Reverse raster scan or wipe left. - - - - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE  - integer - - Specifies the size of the first slice group for raster and wipe map. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH  - integer - - Specifies the number of consecutive macroblocks for the interleaved map. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_ASO  - boolean - - Enables arbitrary slice ordering in encoded bitstream. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER  - integer - Specifies the slice order in ASO. Applicable to the H264 encoder. -The supplied 32-bit integer is interpreted as follows (bit -0 = least significant bit): - - - - - - Bit 0:15 - Slice ID - - - Bit 16:32 - Slice position or order - - - - - - - - V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING  - boolean - - Enables H264 hierarchical coding. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE  - enum v4l2_mpeg_video_h264_hierarchical_coding_type - - Specifies the hierarchical coding type. -Applicable to the H264 encoder. -Possible values are: - - - - - - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B  - Hierarchical B coding. - - - V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P  - Hierarchical P coding. - - - - - - - - V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER  - integer - - Specifies the number of hierarchical coding layers. -Applicable to the H264 encoder. - - - - - V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP  - integer - Specifies a user defined QP for each layer. Applicable to the H264 encoder. -The supplied 32-bit integer is interpreted as follows (bit -0 = least significant bit): - - - - - - Bit 0:15 - QP value - - - Bit 16:32 - Layer number - - - - - @@ -4533,16 +4267,6 @@ interface and may change in the future. pixels / second. - - V4L2_CID_TEST_PATTERN - menu - - - Some capture/display/sensor devices have - the capability to generate test pattern images. These hardware - specific test patterns can be used to test if a device is working - properly. - diff --git a/trunk/Documentation/DocBook/media/v4l/io.xml b/trunk/Documentation/DocBook/media/v4l/io.xml index b5d1cbdc558b..97f785add841 100644 --- a/trunk/Documentation/DocBook/media/v4l/io.xml +++ b/trunk/Documentation/DocBook/media/v4l/io.xml @@ -677,10 +677,8 @@ memory, set by the application. See for details. length Size of the buffer (not the payload) in bytes for the - single-planar API. For the multi-planar API the application sets - this to the number of elements in the planes - array. The driver will fill in the actual number of valid elements in - that array. + single-planar API. For the multi-planar API should contain the + number of elements in the planes array. diff --git a/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml b/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml index a990b34d911a..5274c24d11e0 100644 --- a/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml +++ b/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml @@ -1,13 +1,11 @@ - + - V4L2_PIX_FMT_NV12M ('NM12'), V4L2_PIX_FMT_NV21M ('NM21'), V4L2_PIX_FMT_NV12MT_16X16 + V4L2_PIX_FMT_NV12M ('NM12') &manvol; - V4L2_PIX_FMT_NV12M - V4L2_PIX_FMT_NV21M - V4L2_PIX_FMT_NV12MT_16X16 - Variation of V4L2_PIX_FMT_NV12 and V4L2_PIX_FMT_NV21 with planes + V4L2_PIX_FMT_NV12M + Variation of V4L2_PIX_FMT_NV12 with planes non contiguous in memory. @@ -24,12 +22,7 @@ The CbCr plane is the same width, in bytes, as the Y plane (and of the image), but is half as tall in pixels. Each CbCr pair belongs to four pixels. For example, Cb0/Cr0 belongs to Y'00, Y'01, -Y'10, Y'11. -V4L2_PIX_FMT_NV12MT_16X16 is the tiled version of -V4L2_PIX_FMT_NV12M with 16x16 macroblock tiles. Here pixels -are arranged in 16x16 2D tiles and tiles are arranged in linear order in memory. -V4L2_PIX_FMT_NV21M is the same as V4L2_PIX_FMT_NV12M -except the Cb and Cr bytes are swapped, the CrCb plane starts with a Cr byte. +Y'10, Y'11. V4L2_PIX_FMT_NV12M is intended to be used only in drivers and applications that support the multi-planar API, diff --git a/trunk/Documentation/DocBook/media/v4l/pixfmt.xml b/trunk/Documentation/DocBook/media/v4l/pixfmt.xml index bf94f417592c..1ddbfabe3195 100644 --- a/trunk/Documentation/DocBook/media/v4l/pixfmt.xml +++ b/trunk/Documentation/DocBook/media/v4l/pixfmt.xml @@ -758,11 +758,6 @@ extended control V4L2_CID_MPEG_STREAM_TYPE, see 'AVC1' H264 video elementary stream without start codes. - - V4L2_PIX_FMT_H264_MVC - 'MVC' - H264 MVC video elementary stream. - V4L2_PIX_FMT_H263 'H263' @@ -798,11 +793,6 @@ extended control V4L2_CID_MPEG_STREAM_TYPE, see 'VC1L' VC1, SMPTE 421M Annex L compliant stream. - - V4L2_PIX_FMT_VP8 - 'VP8' - VP8 video elementary stream. - @@ -1006,34 +996,6 @@ the other bits are set to 0. Old 6-bit greyscale format. Only the most significant 6 bits of each byte are used, the other bits are set to 0. - - V4L2_PIX_FMT_S5C_UYVY_JPG - 'S5CI' - Two-planar format used by Samsung S5C73MX cameras. The -first plane contains interleaved JPEG and UYVY image data, followed by meta data -in form of an array of offsets to the UYVY data blocks. The actual pointer array -follows immediately the interleaved JPEG/UYVY data, the number of entries in -this array equals the height of the UYVY image. Each entry is a 4-byte unsigned -integer in big endian order and it's an offset to a single pixel line of the -UYVY image. The first plane can start either with JPEG or UYVY data chunk. The -size of a single UYVY block equals the UYVY image's width multiplied by 2. The -size of a JPEG chunk depends on the image and can vary with each line. -The second plane, at an offset of 4084 bytes, contains a 4-byte offset to -the pointer array in the first plane. This offset is followed by a 4-byte value -indicating size of the pointer array. All numbers in the second plane are also -in big endian order. Remaining data in the second plane is undefined. The -information in the second plane allows to easily find location of the pointer -array, which can be different for each frame. The size of the pointer array is -constant for given UYVY image height. -In order to extract UYVY and JPEG frames an application can initially set -a data pointer to the start of first plane and then add an offset from the first -entry of the pointers table. Such a pointer indicates start of an UYVY image -pixel line. Whole UYVY line can be copied to a separate buffer. These steps -should be repeated for each line, i.e. the number of entries in the pointer -array. Anything what's in between the UYVY lines is JPEG data and should be -concatenated to form the JPEG stream. - - diff --git a/trunk/Documentation/DocBook/media/v4l/subdev-formats.xml b/trunk/Documentation/DocBook/media/v4l/subdev-formats.xml index a0a936455fae..49c532ebbbbe 100644 --- a/trunk/Documentation/DocBook/media/v4l/subdev-formats.xml +++ b/trunk/Documentation/DocBook/media/v4l/subdev-formats.xml @@ -2565,49 +2565,5 @@ - -
- Vendor and Device Specific Formats - - - Experimental - This is an experimental -interface and may change in the future. - - - This section lists complex data formats that are either vendor or - device specific. - - - The following table lists the existing vendor and device specific - formats. - - - Vendor and device specific formats - - - - - - - Identifier - Code - Comments - - - - - V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8 - 0x5001 - - Interleaved raw UYVY and JPEG image format with embedded - meta-data used by Samsung S3C73MX camera sensors. - - - - -
-
- diff --git a/trunk/Documentation/DocBook/media/v4l/vidioc-qbuf.xml b/trunk/Documentation/DocBook/media/v4l/vidioc-qbuf.xml index 2d37abefce13..6a821a65a5ae 100644 --- a/trunk/Documentation/DocBook/media/v4l/vidioc-qbuf.xml +++ b/trunk/Documentation/DocBook/media/v4l/vidioc-qbuf.xml @@ -121,7 +121,8 @@ remaining fields or returns an error code. The driver may also set field. It indicates a non-critical (recoverable) streaming error. In such case the application may continue as normal, but should be aware that data in the dequeued buffer might be corrupted. When using the multi-planar API, the -planes array must be passed in as well. +planes array does not have to be passed; the m.planes +member must be set to NULL in that case. By default VIDIOC_DQBUF blocks when no buffer is in the outgoing queue. When the diff --git a/trunk/Documentation/DocBook/media/v4l/vidioc-querybuf.xml b/trunk/Documentation/DocBook/media/v4l/vidioc-querybuf.xml index a597155c052d..6e414d7b6df7 100644 --- a/trunk/Documentation/DocBook/media/v4l/vidioc-querybuf.xml +++ b/trunk/Documentation/DocBook/media/v4l/vidioc-querybuf.xml @@ -48,8 +48,8 @@ Description - This ioctl is part of the streaming - I/O method. It can be used to query the status of a + This ioctl is part of the memory +mapping I/O method. It can be used to query the status of a buffer at any time after buffers have been allocated with the &VIDIOC-REQBUFS; ioctl. @@ -71,7 +71,6 @@ the structure. In the flags field the V4L2_BUF_FLAG_MAPPED, -V4L2_BUF_FLAG_PREPARED, V4L2_BUF_FLAG_QUEUED and V4L2_BUF_FLAG_DONE flags will be valid. The memory field will be set to the current @@ -80,10 +79,8 @@ contains the offset of the buffer from the start of the device memory, the length field its size. For the multi-planar API, fields m.mem_offset and length in the m.planes -array elements will be used instead and the length -field of &v4l2-buffer; is set to the number of filled-in array elements. -The driver may or may not set the remaining fields and flags, they are -meaningless in this context. +array elements will be used instead. The driver may or may not set the remaining +fields and flags, they are meaningless in this context. The v4l2_buffer structure is specified in . diff --git a/trunk/Documentation/arm/Booting b/trunk/Documentation/arm/Booting index 0c1f475fdf36..a341d87d276e 100644 --- a/trunk/Documentation/arm/Booting +++ b/trunk/Documentation/arm/Booting @@ -154,33 +154,13 @@ In either case, the following conditions must be met: - CPU mode All forms of interrupts must be disabled (IRQs and FIQs) - - For CPUs which do not include the ARM virtualization extensions, the - CPU must be in SVC mode. (A special exception exists for Angel) - - CPUs which include support for the virtualization extensions can be - entered in HYP mode in order to enable the kernel to make full use of - these extensions. This is the recommended boot method for such CPUs, - unless the virtualisations are already in use by a pre-installed - hypervisor. - - If the kernel is not entered in HYP mode for any reason, it must be - entered in SVC mode. + The CPU must be in SVC mode. (A special exception exists for Angel) - Caches, MMUs The MMU must be off. Instruction cache may be on or off. Data cache must be off. - If the kernel is entered in HYP mode, the above requirements apply to - the HYP mode configuration in addition to the ordinary PL1 (privileged - kernel modes) configuration. In addition, all traps into the - hypervisor must be disabled, and PL1 access must be granted for all - peripherals and CPU resources for which this is architecturally - possible. Except for entering in HYP mode, the system configuration - should be such that a kernel which does not include support for the - virtualization extensions can boot correctly without extra help. - - The boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. diff --git a/trunk/Documentation/video4linux/v4l2-controls.txt b/trunk/Documentation/video4linux/v4l2-controls.txt index cfe52c798d74..54270df99d5c 100644 --- a/trunk/Documentation/video4linux/v4l2-controls.txt +++ b/trunk/Documentation/video4linux/v4l2-controls.txt @@ -136,25 +136,11 @@ Or alternatively for integer menu controls, by calling v4l2_ctrl_new_int_menu: const struct v4l2_ctrl_ops *ops, u32 id, s32 max, s32 def, const s64 *qmenu_int); -Standard menu controls with a driver specific menu are added by calling -v4l2_ctrl_new_std_menu_items: - - struct v4l2_ctrl *v4l2_ctrl_new_std_menu_items( - struct v4l2_ctrl_handler *hdl, - const struct v4l2_ctrl_ops *ops, u32 id, s32 max, - s32 skip_mask, s32 def, const char * const *qmenu); - These functions are typically called right after the v4l2_ctrl_handler_init: static const s64 exp_bias_qmenu[] = { -2, -1, 0, 1, 2 }; - static const char * const test_pattern[] = { - "Disabled", - "Vertical Bars", - "Solid Black", - "Solid White", - }; v4l2_ctrl_handler_init(&foo->ctrl_handler, nr_of_controls); v4l2_ctrl_new_std(&foo->ctrl_handler, &foo_ctrl_ops, @@ -170,9 +156,6 @@ These functions are typically called right after the v4l2_ctrl_handler_init: ARRAY_SIZE(exp_bias_qmenu) - 1, ARRAY_SIZE(exp_bias_qmenu) / 2 - 1, exp_bias_qmenu); - v4l2_ctrl_new_std_menu_items(&foo->ctrl_handler, &foo_ctrl_ops, - V4L2_CID_TEST_PATTERN, ARRAY_SIZE(test_pattern) - 1, 0, - 0, test_pattern); ... if (foo->ctrl_handler.error) { int err = foo->ctrl_handler.error; @@ -202,13 +185,6 @@ v4l2_ctrl_new_std_menu in that it doesn't have the mask argument and takes as the last argument an array of signed 64-bit integers that form an exact menu item list. -The v4l2_ctrl_new_std_menu_items function is very similar to -v4l2_ctrl_new_std_menu but takes an extra parameter qmenu, which is the driver -specific menu for an otherwise standard menu control. A good example for this -control is the test pattern control for capture/display/sensors devices that -have the capability to generate test patterns. These test patterns are hardware -specific, so the contents of the menu will vary from device to device. - Note that if something fails, the function will return NULL or an error and set ctrl_handler->error to the error code. If ctrl_handler->error was already set, then it will just return and do nothing. This is also true for diff --git a/trunk/arch/arm/boot/compressed/.gitignore b/trunk/arch/arm/boot/compressed/.gitignore index f79a08efe000..d0d441c429ae 100644 --- a/trunk/arch/arm/boot/compressed/.gitignore +++ b/trunk/arch/arm/boot/compressed/.gitignore @@ -1,7 +1,6 @@ ashldi3.S font.c lib1funcs.S -hyp-stub.S piggy.gzip piggy.lzo piggy.lzma diff --git a/trunk/arch/arm/boot/compressed/Makefile b/trunk/arch/arm/boot/compressed/Makefile index a517153a13ea..bb267562e7ed 100644 --- a/trunk/arch/arm/boot/compressed/Makefile +++ b/trunk/arch/arm/boot/compressed/Makefile @@ -30,10 +30,6 @@ FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c OBJS += string.o CFLAGS_string.o := -Os -ifeq ($(CONFIG_ARM_VIRT_EXT),y) -OBJS += hyp-stub.o -endif - # # Architecture dependencies # @@ -130,7 +126,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif ccflags-y := -fpic -fno-builtin -I$(obj) -asflags-y := -Wa,-march=all -DZIMAGE +asflags-y := -Wa,-march=all # Supply kernel BSS size to the decompressor via a linker symbol. KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ @@ -202,6 +198,3 @@ $(obj)/font.c: $(FONTC) $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile $(KCONFIG_CONFIG) @sed "$(SEDFLAGS)" < $< > $@ - -$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S - $(call cmd,shipped) diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S index 90275f036cd1..bc67cbff3944 100644 --- a/trunk/arch/arm/boot/compressed/head.S +++ b/trunk/arch/arm/boot/compressed/head.S @@ -9,7 +9,6 @@ * published by the Free Software Foundation. */ #include -#include /* * Debugging stuff @@ -133,12 +132,7 @@ start: .word start @ absolute load/run zImage address .word _edata @ zImage end address THUMB( .thumb ) -1: - mrs r9, cpsr -#ifdef CONFIG_ARM_VIRT_EXT - bl __hyp_stub_install @ get into SVC mode, reversibly -#endif - mov r7, r1 @ save architecture ID +1: mov r7, r1 @ save architecture ID mov r8, r2 @ save atags pointer #ifndef __ARM_ARCH_2__ @@ -154,9 +148,9 @@ start: ARM( swi 0x123456 ) @ angel_SWI_ARM THUMB( svc 0xab ) @ angel_SWI_THUMB not_angel: - safe_svcmode_maskall r0 - msr spsr_cxsf, r9 @ Save the CPU boot mode in - @ SPSR + mrs r2, cpsr @ turn off interrupts to + orr r2, r2, #0xc0 @ prevent angel from running + msr cpsr_c, r2 #else teqp pc, #0x0c000003 @ turn off interrupts #endif @@ -356,20 +350,6 @@ dtb_check_done: adr r5, restart bic r5, r5, #31 -/* Relocate the hyp vector base if necessary */ -#ifdef CONFIG_ARM_VIRT_EXT - mrs r0, spsr - and r0, r0, #MODE_MASK - cmp r0, #HYP_MODE - bne 1f - - bl __hyp_get_vectors - sub r0, r0, r5 - add r0, r0, r10 - bl __hyp_set_vectors -1: -#endif - sub r9, r6, r5 @ size to copy add r9, r9, #31 @ rounded up to a multiple bic r9, r9, #31 @ ... of 32 bytes @@ -478,29 +458,11 @@ not_relocated: mov r0, #0 bl decompress_kernel bl cache_clean_flush bl cache_off + mov r0, #0 @ must be zero mov r1, r7 @ restore architecture number mov r2, r8 @ restore atags pointer - -#ifdef CONFIG_ARM_VIRT_EXT - mrs r0, spsr @ Get saved CPU boot mode - and r0, r0, #MODE_MASK - cmp r0, #HYP_MODE @ if not booted in HYP mode... - bne __enter_kernel @ boot kernel directly - - adr r12, .L__hyp_reentry_vectors_offset - ldr r0, [r12] - add r0, r0, r12 - - bl __hyp_set_vectors - __HVC(0) @ otherwise bounce to hyp mode - - b . @ should never be reached - - .align 2 -.L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - . -#else - b __enter_kernel -#endif + ARM( mov pc, r4 ) @ call kernel + THUMB( bx r4 ) @ entry point is always ARM .align 2 .type LC0, #object @@ -1234,25 +1196,6 @@ memdump: mov r12, r0 #endif .ltorg - -#ifdef CONFIG_ARM_VIRT_EXT -.align 5 -__hyp_reentry_vectors: - W(b) . @ reset - W(b) . @ undef - W(b) . @ svc - W(b) . @ pabort - W(b) . @ dabort - W(b) __enter_kernel @ hyp - W(b) . @ irq - W(b) . @ fiq -#endif /* CONFIG_ARM_VIRT_EXT */ - -__enter_kernel: - mov r0, #0 @ must be 0 - ARM( mov pc, r4 ) @ call kernel - THUMB( bx r4 ) @ entry point is always ARM - reloc_code_end: .align diff --git a/trunk/arch/arm/include/asm/assembler.h b/trunk/arch/arm/include/asm/assembler.h index 2ef95813fce0..5c8b3bf4d825 100644 --- a/trunk/arch/arm/include/asm/assembler.h +++ b/trunk/arch/arm/include/asm/assembler.h @@ -22,7 +22,6 @@ #include #include -#include #define IOMEM(x) (x) @@ -240,34 +239,6 @@ .endm #endif -/* - * Helper macro to enter SVC mode cleanly and mask interrupts. reg is - * a scratch register for the macro to overwrite. - * - * This macro is intended for forcing the CPU into SVC mode at boot time. - * you cannot return to the original mode. - * - * Beware, it also clobers LR. - */ -.macro safe_svcmode_maskall reg:req - mrs \reg , cpsr - mov lr , \reg - and lr , lr , #MODE_MASK - cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT - bic \reg , \reg , #MODE_MASK - orr \reg , \reg , #SVC_MODE -THUMB( orr \reg , \reg , #PSR_T_BIT ) - bne 1f - orr \reg, \reg, #PSR_A_BIT - adr lr, BSYM(2f) - msr spsr_cxsf, \reg - __MSR_ELR_HYP(14) - __ERET -1: msr cpsr_c, \reg -2: -.endm - /* * STRT/LDRT access macros with ARM and Thumb-2 variants */ diff --git a/trunk/arch/arm/include/asm/cacheflush.h b/trunk/arch/arm/include/asm/cacheflush.h index e1489c54cd12..e4448e16046d 100644 --- a/trunk/arch/arm/include/asm/cacheflush.h +++ b/trunk/arch/arm/include/asm/cacheflush.h @@ -49,13 +49,6 @@ * * Unconditionally clean and invalidate the entire cache. * - * flush_kern_louis() - * - * Flush data cache levels up to the level of unification - * inner shareable and invalidate the I-cache. - * Only needed from v7 onwards, falls back to flush_cache_all() - * for all other processor versions. - * * flush_user_all() * * Clean and invalidate all user space cache entries @@ -104,7 +97,6 @@ struct cpu_cache_fns { void (*flush_icache_all)(void); void (*flush_kern_all)(void); - void (*flush_kern_louis)(void); void (*flush_user_all)(void); void (*flush_user_range)(unsigned long, unsigned long, unsigned int); @@ -127,7 +119,6 @@ extern struct cpu_cache_fns cpu_cache; #define __cpuc_flush_icache_all cpu_cache.flush_icache_all #define __cpuc_flush_kern_all cpu_cache.flush_kern_all -#define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis #define __cpuc_flush_user_all cpu_cache.flush_user_all #define __cpuc_flush_user_range cpu_cache.flush_user_range #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range @@ -148,7 +139,6 @@ extern struct cpu_cache_fns cpu_cache; extern void __cpuc_flush_icache_all(void); extern void __cpuc_flush_kern_all(void); -extern void __cpuc_flush_kern_louis(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); @@ -214,11 +204,6 @@ static inline void __flush_icache_all(void) __flush_icache_preferred(); } -/* - * Flush caches up to Level of Unification Inner Shareable - */ -#define flush_cache_louis() __cpuc_flush_kern_louis() - #define flush_cache_all() __cpuc_flush_kern_all() static inline void vivt_flush_cache_mm(struct mm_struct *mm) diff --git a/trunk/arch/arm/include/asm/glue-cache.h b/trunk/arch/arm/include/asm/glue-cache.h index cca9f15704ed..4f8d2c0dc441 100644 --- a/trunk/arch/arm/include/asm/glue-cache.h +++ b/trunk/arch/arm/include/asm/glue-cache.h @@ -132,7 +132,6 @@ #ifndef MULTI_CACHE #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) -#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis) #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) diff --git a/trunk/arch/arm/include/asm/opcodes-virt.h b/trunk/arch/arm/include/asm/opcodes-virt.h index efcfdf92d9d5..b85665a96f8e 100644 --- a/trunk/arch/arm/include/asm/opcodes-virt.h +++ b/trunk/arch/arm/include/asm/opcodes-virt.h @@ -26,14 +26,4 @@ 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \ ) -#define __ERET __inst_arm_thumb32( \ - 0xE160006E, \ - 0xF3DE8F00 \ -) - -#define __MSR_ELR_HYP(regnum) __inst_arm_thumb32( \ - 0xE12EF300 | regnum, \ - 0xF3808E30 | (regnum << 16) \ -) - #endif /* ! __ASM_ARM_OPCODES_VIRT_H */ diff --git a/trunk/arch/arm/include/asm/ptrace.h b/trunk/arch/arm/include/asm/ptrace.h index 142d6ae41231..44fe998269d9 100644 --- a/trunk/arch/arm/include/asm/ptrace.h +++ b/trunk/arch/arm/include/asm/ptrace.h @@ -44,7 +44,6 @@ #define IRQ_MODE 0x00000012 #define SVC_MODE 0x00000013 #define ABT_MODE 0x00000017 -#define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b #define SYSTEM_MODE 0x0000001f #define MODE32_BIT 0x00000010 diff --git a/trunk/arch/arm/include/asm/vfpmacros.h b/trunk/arch/arm/include/asm/vfpmacros.h index 6a6f1e485f41..a7aadbd9a6dd 100644 --- a/trunk/arch/arm/include/asm/vfpmacros.h +++ b/trunk/arch/arm/include/asm/vfpmacros.h @@ -28,7 +28,7 @@ ldr \tmp, =elf_hwcap @ may not have MVFR regs ldr \tmp, [\tmp, #0] tst \tmp, #HWCAP_VFPv3D16 - ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} + ldceq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 @@ -52,7 +52,7 @@ ldr \tmp, =elf_hwcap @ may not have MVFR regs ldr \tmp, [\tmp, #0] tst \tmp, #HWCAP_VFPv3D16 - stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} + stceq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} addne \base, \base, #32*4 @ step over unused register space #else VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 diff --git a/trunk/arch/arm/include/asm/virt.h b/trunk/arch/arm/include/asm/virt.h deleted file mode 100644 index 86164df86cb4..000000000000 --- a/trunk/arch/arm/include/asm/virt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2012 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef VIRT_H -#define VIRT_H - -#include - -/* - * Flag indicating that the kernel was not entered in the same mode on every - * CPU. The zImage loader stashes this value in an SPSR, so we need an - * architecturally defined flag bit here (the N flag, as it happens) - */ -#define BOOT_CPU_MODE_MISMATCH (1<<31) - -#ifndef __ASSEMBLY__ - -#ifdef CONFIG_ARM_VIRT_EXT -/* - * __boot_cpu_mode records what mode the primary CPU was booted in. - * A correctly-implemented bootloader must start all CPUs in the same mode: - * if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate - * that some CPU(s) were booted in a different mode. - * - * This allows the kernel to flag an error when the secondaries have come up. - */ -extern int __boot_cpu_mode; - -void __hyp_set_vectors(unsigned long phys_vector_base); -unsigned long __hyp_get_vectors(void); -#else -#define __boot_cpu_mode (SVC_MODE) -#endif - -#ifndef ZIMAGE -void hyp_mode_check(void); - -/* Reports the availability of HYP mode */ -static inline bool is_hyp_mode_available(void) -{ - return ((__boot_cpu_mode & MODE_MASK) == HYP_MODE && - !(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH)); -} - -/* Check if the bootloader has booted CPUs in different modes */ -static inline bool is_hyp_mode_mismatched(void) -{ - return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH); -} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* ! VIRT_H */ diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index 5bbec7b8183e..5dfef9d97ed9 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -81,6 +81,4 @@ head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o - extra-y := $(head-y) vmlinux.lds diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index 4eee351f4668..9874d0741191 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -83,12 +83,8 @@ ENTRY(stext) THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) -#ifdef CONFIG_ARM_VIRT_EXT - bl __hyp_stub_install -#endif - @ ensure svc mode and all interrupts masked - safe_svcmode_maskall r9 - + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode + @ and irqs disabled mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? @@ -330,11 +326,7 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ -#ifdef CONFIG_ARM_VIRT_EXT - bl __hyp_stub_install -#endif - safe_svcmode_maskall r9 - + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? diff --git a/trunk/arch/arm/kernel/hyp-stub.S b/trunk/arch/arm/kernel/hyp-stub.S deleted file mode 100644 index 65b2417aebce..000000000000 --- a/trunk/arch/arm/kernel/hyp-stub.S +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2012 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include -#include -#include -#include - -#ifndef ZIMAGE -/* - * For the kernel proper, we need to find out the CPU boot mode long after - * boot, so we need to store it in a writable variable. - * - * This is not in .bss, because we set it sufficiently early that the boot-time - * zeroing of .bss would clobber it. - */ -.data -ENTRY(__boot_cpu_mode) - .long 0 -.text - - /* - * Save the primary CPU boot mode. Requires 3 scratch registers. - */ - .macro store_primary_cpu_mode reg1, reg2, reg3 - mrs \reg1, cpsr - and \reg1, \reg1, #MODE_MASK - adr \reg2, .L__boot_cpu_mode_offset - ldr \reg3, [\reg2] - str \reg1, [\reg2, \reg3] - .endm - - /* - * Compare the current mode with the one saved on the primary CPU. - * If they don't match, record that fact. The Z bit indicates - * if there's a match or not. - * Requires 3 additionnal scratch registers. - */ - .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 - adr \reg2, .L__boot_cpu_mode_offset - ldr \reg3, [\reg2] - ldr \reg1, [\reg2, \reg3] - cmp \mode, \reg1 @ matches primary CPU boot mode? - orrne r7, r7, #BOOT_CPU_MODE_MISMATCH - strne r7, [r5, r6] @ record what happened and give up - .endm - -#else /* ZIMAGE */ - - .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req - .endm - -/* - * The zImage loader only runs on one CPU, so we don't bother with mult-CPU - * consistency checking: - */ - .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 - cmp \mode, \mode - .endm - -#endif /* ZIMAGE */ - -/* - * Hypervisor stub installation functions. - * - * These must be called with the MMU and D-cache off. - * They are not ABI compliant and are only intended to be called from the kernel - * entry points in head.S. - */ -@ Call this from the primary CPU -ENTRY(__hyp_stub_install) - store_primary_cpu_mode r4, r5, r6 -ENDPROC(__hyp_stub_install) - - @ fall through... - -@ Secondary CPUs should call here -ENTRY(__hyp_stub_install_secondary) - mrs r4, cpsr - and r4, r4, #MODE_MASK - - /* - * If the secondary has booted with a different mode, give up - * immediately. - */ - compare_cpu_mode_with_primary r4, r5, r6, r7 - bxne lr - - /* - * Once we have given up on one CPU, we do not try to install the - * stub hypervisor on the remaining ones: because the saved boot mode - * is modified, it can't compare equal to the CPSR mode field any - * more. - * - * Otherwise... - */ - - cmp r4, #HYP_MODE - bxne lr @ give up if the CPU is not in HYP mode - -/* - * Configure HSCTLR to set correct exception endianness/instruction set - * state etc. - * Turn off all traps - * Eventually, CPU-specific code might be needed -- assume not for now - * - * This code relies on the "eret" instruction to synchronize the - * various coprocessor accesses. - */ - @ Now install the hypervisor stub: - adr r7, __hyp_stub_vectors - mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) - - @ Disable all traps, so we don't get any nasty surprise - mov r7, #0 - mcr p15, 4, r7, c1, c1, 0 @ HCR - mcr p15, 4, r7, c1, c1, 2 @ HCPTR - mcr p15, 4, r7, c1, c1, 3 @ HSTR - -THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE -#ifdef CONFIG_CPU_BIG_ENDIAN - orr r7, #(1 << 9) @ HSCTLR.EE -#endif - mcr p15, 4, r7, c1, c0, 0 @ HSCTLR - - mrc p15, 4, r7, c1, c1, 1 @ HDCR - and r7, #0x1f @ Preserve HPMN - mcr p15, 4, r7, c1, c1, 1 @ HDCR - -#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER) - @ make CNTP_* and CNTPCT accessible from PL1 - mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 - lsr r7, #16 - and r7, #0xf - cmp r7, #1 - bne 1f - mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL - orr r7, r7, #3 @ PL1PCEN | PL1PCTEN - mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL -1: -#endif - - bic r7, r4, #MODE_MASK - orr r7, r7, #SVC_MODE -THUMB( orr r7, r7, #PSR_T_BIT ) - msr spsr_cxsf, r7 @ This is SPSR_hyp. - - __MSR_ELR_HYP(14) @ msr elr_hyp, lr - __ERET @ return, switching to SVC mode - @ The boot CPU mode is left in r4. -ENDPROC(__hyp_stub_install_secondary) - -__hyp_stub_do_trap: - cmp r0, #-1 - mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR - mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR - __ERET -ENDPROC(__hyp_stub_do_trap) - -/* - * __hyp_set_vectors: Call this after boot to set the initial hypervisor - * vectors as part of hypervisor installation. On an SMP system, this should - * be called on each CPU. - * - * r0 must be the physical address of the new vector table (which must lie in - * the bottom 4GB of physical address space. - * - * r0 must be 32-byte aligned. - * - * Before calling this, you must check that the stub hypervisor is installed - * everywhere, by waiting for any secondary CPUs to be brought up and then - * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true. - * - * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or - * something else went wrong... in such cases, trying to install a new - * hypervisor is unlikely to work as desired. - * - * When you call into your shiny new hypervisor, sp_hyp will contain junk, - * so you will need to set that to something sensible at the new hypervisor's - * initialisation entry point. - */ -ENTRY(__hyp_get_vectors) - mov r0, #-1 -ENDPROC(__hyp_get_vectors) - @ fall through -ENTRY(__hyp_set_vectors) - __HVC(0) - bx lr -ENDPROC(__hyp_set_vectors) - -#ifndef ZIMAGE -.align 2 -.L__boot_cpu_mode_offset: - .long __boot_cpu_mode - . -#endif - -.align 5 -__hyp_stub_vectors: -__hyp_stub_reset: W(b) . -__hyp_stub_und: W(b) . -__hyp_stub_svc: W(b) . -__hyp_stub_pabort: W(b) . -__hyp_stub_dabort: W(b) . -__hyp_stub_trap: W(b) __hyp_stub_do_trap -__hyp_stub_irq: W(b) . -__hyp_stub_fiq: W(b) . -ENDPROC(__hyp_stub_vectors) - diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index da1d1aa20ad9..febafa0f552d 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -53,7 +53,6 @@ #include #include #include -#include #include "atags.h" #include "tcm.h" @@ -704,21 +703,6 @@ static int __init meminfo_cmp(const void *_a, const void *_b) return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; } -void __init hyp_mode_check(void) -{ -#ifdef CONFIG_ARM_VIRT_EXT - if (is_hyp_mode_available()) { - pr_info("CPU: All CPU(s) started in HYP mode.\n"); - pr_info("CPU: Virtualization extensions available.\n"); - } else if (is_hyp_mode_mismatched()) { - pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n", - __boot_cpu_mode & MODE_MASK); - pr_warn("CPU: This may indicate a broken bootloader or firmware.\n"); - } else - pr_info("CPU: All CPU(s) started in SVC mode.\n"); -#endif -} - void __init setup_arch(char **cmdline_p) { struct machine_desc *mdesc; @@ -764,10 +748,6 @@ void __init setup_arch(char **cmdline_p) smp_init_cpus(); } #endif - - if (!is_smp()) - hyp_mode_check(); - reserve_crashkernel(); tcm_init(); diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 8e20754dd31d..d100eacdb798 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -43,7 +43,6 @@ #include #include #include -#include #include /* @@ -203,11 +202,8 @@ int __cpuinit __cpu_disable(void) /* * Flush user cache and TLB mappings, and then remove this CPU * from the vm mask set of all processes. - * - * Caches are flushed to the Level of Unification Inner Shareable - * to write-back dirty lines to unified caches shared by all CPUs. */ - flush_cache_louis(); + flush_cache_all(); local_flush_tlb_all(); clear_tasks_mm_cpumask(cpu); @@ -359,8 +355,6 @@ void __init smp_cpus_done(unsigned int max_cpus) num_online_cpus(), bogosum / (500000/HZ), (bogosum / (5000/HZ)) % 100); - - hyp_mode_check(); } void __init smp_prepare_boot_cpu(void) diff --git a/trunk/arch/arm/kernel/suspend.c b/trunk/arch/arm/kernel/suspend.c index 358bca3a995e..1794cc3b0f18 100644 --- a/trunk/arch/arm/kernel/suspend.c +++ b/trunk/arch/arm/kernel/suspend.c @@ -17,8 +17,6 @@ extern void cpu_resume_mmu(void); */ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) { - u32 *ctx = ptr; - *save_ptr = virt_to_phys(ptr); /* This must correspond to the LDM in cpu_resume() assembly */ @@ -28,20 +26,7 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) cpu_do_suspend(ptr); - flush_cache_louis(); - - /* - * flush_cache_louis does not guarantee that - * save_ptr and ptr are cleaned to main memory, - * just up to the Level of Unification Inner Shareable. - * Since the context pointer and context itself - * are to be retrieved with the MMU off that - * data must be cleaned from all cache levels - * to main memory using "area" cache primitives. - */ - __cpuc_flush_dcache_area(ctx, ptrsz); - __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr)); - + flush_cache_all(); outer_clean_range(*save_ptr, *save_ptr + ptrsz); outer_clean_range(virt_to_phys(save_ptr), virt_to_phys(save_ptr) + sizeof(*save_ptr)); diff --git a/trunk/arch/arm/mach-davinci/Kconfig b/trunk/arch/arm/mach-davinci/Kconfig index 026b4b277ae5..ab99c3c3b752 100644 --- a/trunk/arch/arm/mach-davinci/Kconfig +++ b/trunk/arch/arm/mach-davinci/Kconfig @@ -186,13 +186,6 @@ config DA850_UI_RMII NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. -config DA850_UI_SD_VIDEO_PORT - bool "Video Port Interface" - help - Say Y if you want to use Video Port Interface (VPIF) on the - DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the - UI daughter card that is supplied with the EVM. - endchoice config DA850_WL12XX diff --git a/trunk/arch/arm/mach-davinci/board-da850-evm.c b/trunk/arch/arm/mach-davinci/board-da850-evm.c index 32ee3f895967..1295e616ceee 100644 --- a/trunk/arch/arm/mach-davinci/board-da850-evm.c +++ b/trunk/arch/arm/mach-davinci/board-da850-evm.c @@ -45,9 +45,6 @@ #include #include -#include -#include - #define DA850_EVM_PHY_ID "davinci_mdio-0:00" #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) @@ -455,15 +452,6 @@ static void da850_evm_ui_keys_init(unsigned gpio) } } -#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT -static inline void da850_evm_setup_video_port(int video_sel) -{ - gpio_set_value_cansleep(video_sel, 0); -} -#else -static inline void da850_evm_setup_video_port(int video_sel) { } -#endif - static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, unsigned ngpio, void *c) { @@ -509,8 +497,6 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, da850_evm_setup_emac_rmii(sel_a); - da850_evm_setup_video_port(sel_c); - return 0; exp_setup_keys_fail: @@ -1163,169 +1149,6 @@ static __init int da850_evm_init_cpufreq(void) static __init int da850_evm_init_cpufreq(void) { return 0; } #endif -#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT) - -#define TVP5147_CH0 "tvp514x-0" -#define TVP5147_CH1 "tvp514x-1" - -/* VPIF capture configuration */ -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1, -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -static const struct vpif_input da850_ch0_inputs[] = { - { - .input = { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH0, - }, -}; - -static const struct vpif_input da850_ch1_inputs[] = { - { - .input = { - .index = 0, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH1, - }, -}; - -static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { - { - .name = TVP5147_CH0, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, - { - .name = TVP5147_CH1, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5c), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpif_capture_config da850_vpif_capture_config = { - .subdev_info = da850_vpif_capture_sdev_info, - .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), - .chan_config[0] = { - .inputs = da850_ch0_inputs, - .input_count = ARRAY_SIZE(da850_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .chan_config[1] = { - .inputs = da850_ch1_inputs, - .input_count = ARRAY_SIZE(da850_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .card_name = "DA850/OMAP-L138 Video Capture", -}; - -/* VPIF display configuration */ -static struct vpif_subdev_info da850_vpif_subdev[] = { - { - .name = "adv7343", - .board_info = { - I2C_BOARD_INFO("adv7343", 0x2a), - }, - }, -}; - -static const struct vpif_output da850_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, -}; - -static struct vpif_display_config da850_vpif_display_config = { - .subdevinfo = da850_vpif_subdev, - .subdev_count = ARRAY_SIZE(da850_vpif_subdev), - .chan_config[0] = { - .outputs = da850_ch0_outputs, - .output_count = ARRAY_SIZE(da850_ch0_outputs), - }, - .card_name = "DA850/OMAP-L138 Video Display", -}; - -static __init void da850_vpif_init(void) -{ - int ret; - - ret = da850_register_vpif(); - if (ret) - pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_capture_pins); - if (ret) - pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_capture(&da850_vpif_capture_config); - if (ret) - pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_display_pins); - if (ret) - pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_display(&da850_vpif_display_config); - if (ret) - pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret); -} - -#else -static __init void da850_vpif_init(void) {} -#endif - #ifdef CONFIG_DA850_WL12XX static void wl12xx_set_power(int index, bool power_on) @@ -1552,8 +1375,6 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: suspend registration failed: %d\n", ret); - da850_vpif_init(); - ret = da8xx_register_spi(1, da850evm_spi_info, ARRAY_SIZE(da850evm_spi_info)); if (ret) diff --git a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c index f22572cee49d..ca72fc4b8cca 100644 --- a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -621,7 +620,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { { .name = "ntsc", .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_525_60, + .timings = {V4L2_STD_525_60}, .interlaced = 1, .xres = 720, .yres = 480, @@ -633,7 +632,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { { .name = "pal", .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_625_50, + .timings = {V4L2_STD_625_50}, .interlaced = 1, .xres = 720, .yres = 576, @@ -648,8 +647,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = { static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { { .name = "480p59_94", - .timings_type = VPBE_ENC_CUSTOM_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, + .timings_type = VPBE_ENC_DV_PRESET, + .timings = {V4L2_DV_480P59_94}, .interlaced = 0, .xres = 720, .yres = 480, @@ -660,8 +659,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = { }, { .name = "576p50", - .timings_type = VPBE_ENC_CUSTOM_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X576P50, + .timings_type = VPBE_ENC_DV_PRESET, + .timings = {V4L2_DV_576P50}, .interlaced = 0, .xres = 720, .yres = 576, @@ -699,7 +698,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = { .index = 1, .name = "Component", .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, + .capabilities = V4L2_OUT_CAP_PRESETS, }, .subdev_name = VPBE_VENC_SUBDEV_NAME, .default_mode = "480p59_94", diff --git a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c b/trunk/arch/arm/mach-davinci/board-dm646x-evm.c index 1dbf85beed1b..9944367b4931 100644 --- a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/trunk/arch/arm/mach-davinci/board-dm646x-evm.c @@ -26,7 +26,6 @@ #include #include -#include #include #include @@ -497,49 +496,18 @@ static struct vpif_subdev_info dm646x_vpif_subdev[] = { }, }; -static const struct vpif_output dm6467_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPONENT_ID, - }, - { - .output = { - .index = 2, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, +static const char *output[] = { + "Composite", + "Component", + "S-Video", }; static struct vpif_display_config dm646x_vpif_display_config = { .set_clock = set_vpif_clock, .subdevinfo = dm646x_vpif_subdev, .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev), - .chan_config[0] = { - .outputs = dm6467_ch0_outputs, - .output_count = ARRAY_SIZE(dm6467_ch0_outputs), - }, + .output = output, + .output_count = ARRAY_SIZE(output), .card_name = "DM646x EVM", }; @@ -633,6 +601,15 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = { I2C_BOARD_INFO("tvp5146", 0x5d), .platform_data = &tvp5146_pdata, }, + .input = INPUT_CVBS_VI2B, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, }, { .name = TVP5147_CH1, @@ -640,6 +617,15 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = { I2C_BOARD_INFO("tvp5146", 0x5c), .platform_data = &tvp5146_pdata, }, + .input = INPUT_SVIDEO_VI2C_VI1C, + .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, + .can_route = 1, + .vpif_if = { + .if_type = VPIF_IF_BT656, + .hd_pol = 1, + .vd_pol = 1, + .fid_pol = 0, + }, }, }; @@ -649,12 +635,9 @@ static const struct vpif_input dm6467_ch0_inputs[] = { .index = 0, .name = "Composite", .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, .std = TVP514X_STD_ALL, }, .subdev_name = TVP5147_CH0, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, }, }; @@ -664,12 +647,9 @@ static const struct vpif_input dm6467_ch1_inputs[] = { .index = 0, .name = "S-Video", .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, .std = TVP514X_STD_ALL, }, .subdev_name = TVP5147_CH1, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, }, }; @@ -681,22 +661,10 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = { .chan_config[0] = { .inputs = dm6467_ch0_inputs, .input_count = ARRAY_SIZE(dm6467_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, }, .chan_config[1] = { .inputs = dm6467_ch1_inputs, .input_count = ARRAY_SIZE(dm6467_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, }, }; diff --git a/trunk/arch/arm/mach-davinci/da850.c b/trunk/arch/arm/mach-davinci/da850.c index b90c172d5541..e517e1036b09 100644 --- a/trunk/arch/arm/mach-davinci/da850.c +++ b/trunk/arch/arm/mach-davinci/da850.c @@ -347,13 +347,6 @@ static struct clk spi1_clk = { .flags = DA850_CLK_ASYNC3, }; -static struct clk vpif_clk = { - .name = "vpif", - .parent = &pll0_sysclk2, - .lpsc = DA850_LPSC1_VPIF, - .gpsc = 1, -}; - static struct clk sata_clk = { .name = "sata", .parent = &pll0_sysclk2, @@ -404,7 +397,6 @@ static struct clk_lookup da850_clks[] = { CLK(NULL, "usb20", &usb20_clk), CLK("spi_davinci.0", NULL, &spi0_clk), CLK("spi_davinci.1", NULL, &spi1_clk), - CLK("vpif", NULL, &vpif_clk), CLK("ahci", NULL, &sata_clk), CLK(NULL, NULL, NULL), }; @@ -581,46 +573,6 @@ static const struct mux_config da850_pins[] = { MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) - /* VPIF Capture */ - MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false) - MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false) - /* VPIF Display */ - MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false) - MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false) - MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false) #endif }; @@ -643,26 +595,6 @@ const short da850_lcdcntl_pins[] __initconst = { -1 }; -const short da850_vpif_capture_pins[] __initdata = { - DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, - DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, - DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, - DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - -1 -}; - -const short da850_vpif_display_pins[] __initdata = { - DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, - -1 -}; - /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_COMMTX] = 7, @@ -1132,90 +1064,6 @@ int __init da850_register_pm(struct platform_device *pdev) return ret; } -/* VPIF resource, platform data */ -static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); - -static struct resource da850_vpif_resource[] = { - { - .start = DA8XX_VPIF_BASE, - .end = DA8XX_VPIF_BASE + 0xfff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device da850_vpif_dev = { - .name = "vpif", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_resource, - .num_resources = ARRAY_SIZE(da850_vpif_resource), -}; - -static struct resource da850_vpif_display_resource[] = { - { - .start = IRQ_DA850_VPIFINT, - .end = IRQ_DA850_VPIFINT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da850_vpif_display_dev = { - .name = "vpif_display", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_display_resource, - .num_resources = ARRAY_SIZE(da850_vpif_display_resource), -}; - -static struct resource da850_vpif_capture_resource[] = { - { - .start = IRQ_DA850_VPIFINT, - .end = IRQ_DA850_VPIFINT, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_DA850_VPIFINT, - .end = IRQ_DA850_VPIFINT, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device da850_vpif_capture_dev = { - .name = "vpif_capture", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_capture_resource, - .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), -}; - -int __init da850_register_vpif(void) -{ - return platform_device_register(&da850_vpif_dev); -} - -int __init da850_register_vpif_display(struct vpif_display_config - *display_config) -{ - da850_vpif_display_dev.dev.platform_data = display_config; - return platform_device_register(&da850_vpif_display_dev); -} - -int __init da850_register_vpif_capture(struct vpif_capture_config - *capture_config) -{ - da850_vpif_capture_dev.dev.platform_data = capture_config; - return platform_device_register(&da850_vpif_capture_dev); -} - static struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), diff --git a/trunk/arch/arm/mach-davinci/dm644x.c b/trunk/arch/arm/mach-davinci/dm644x.c index cd0c8b1e1ecf..0755d466221a 100644 --- a/trunk/arch/arm/mach-davinci/dm644x.c +++ b/trunk/arch/arm/mach-davinci/dm644x.c @@ -701,7 +701,7 @@ static struct resource dm644x_venc_resources[] = { #define DM644X_VPSS_DACCLKEN BIT(4) static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, - unsigned int pclock) + unsigned int mode) { int ret = 0; u32 v = DM644X_VPSS_VENCLKEN; @@ -711,18 +711,27 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, v |= DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); break; - case VPBE_ENC_CUSTOM_TIMINGS: - if (pclock <= 27000000) { + case VPBE_ENC_DV_PRESET: + switch (mode) { + case V4L2_DV_480P59_94: + case V4L2_DV_576P50: v |= DM644X_VPSS_MUXSEL_PLL2_MODE | DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); - } else { + break; + case V4L2_DV_720P60: + case V4L2_DV_1080I60: + case V4L2_DV_1080P30: /* * For HD, use external clock source since * HD requires higher clock rate */ v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); + break; + default: + ret = -EINVAL; + break; } break; default: diff --git a/trunk/arch/arm/mach-davinci/include/mach/da8xx.h b/trunk/arch/arm/mach-davinci/include/mach/da8xx.h index aaccdc4528fc..c9ee723c56f3 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/trunk/arch/arm/mach-davinci/include/mach/da8xx.h @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -27,8 +26,6 @@ #include #include -#include - extern void __iomem *da8xx_syscfg0_base; extern void __iomem *da8xx_syscfg1_base; @@ -66,7 +63,6 @@ extern unsigned int da850_max_speed; #define DA8XX_PLL0_BASE 0x01c11000 #define DA8XX_TIMER64P0_BASE 0x01c20000 #define DA8XX_TIMER64P1_BASE 0x01c21000 -#define DA8XX_VPIF_BASE 0x01e17000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 @@ -96,11 +92,6 @@ int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); int __init da850_register_sata(unsigned long refclkpn); -int __init da850_register_vpif(void); -int __init da850_register_vpif_display - (struct vpif_display_config *display_config); -int __init da850_register_vpif_capture - (struct vpif_capture_config *capture_config); void da8xx_restart(char mode, const char *cmd); extern struct platform_device da8xx_serial_device; @@ -135,8 +126,6 @@ extern const short da830_ecap1_pins[]; extern const short da830_ecap2_pins[]; extern const short da830_eqep0_pins[]; extern const short da830_eqep1_pins[]; -extern const short da850_vpif_capture_pins[]; -extern const short da850_vpif_display_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; diff --git a/trunk/arch/arm/mach-davinci/include/mach/mux.h b/trunk/arch/arm/mach-davinci/include/mach/mux.h index 9e95b8a1edb6..a7e92fca32e6 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/mux.h +++ b/trunk/arch/arm/mach-davinci/include/mach/mux.h @@ -928,48 +928,6 @@ enum davinci_da850_index { DA850_GPIO6_10, DA850_GPIO6_13, DA850_RTC_ALARM, - - /* VPIF Capture */ - DA850_VPIF_DIN0, - DA850_VPIF_DIN1, - DA850_VPIF_DIN2, - DA850_VPIF_DIN3, - DA850_VPIF_DIN4, - DA850_VPIF_DIN5, - DA850_VPIF_DIN6, - DA850_VPIF_DIN7, - DA850_VPIF_DIN8, - DA850_VPIF_DIN9, - DA850_VPIF_DIN10, - DA850_VPIF_DIN11, - DA850_VPIF_DIN12, - DA850_VPIF_DIN13, - DA850_VPIF_DIN14, - DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, - DA850_VPIF_CLKIN1, - DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - - /* VPIF Display */ - DA850_VPIF_DOUT0, - DA850_VPIF_DOUT1, - DA850_VPIF_DOUT2, - DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, - DA850_VPIF_DOUT5, - DA850_VPIF_DOUT6, - DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, - DA850_VPIF_DOUT9, - DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, - DA850_VPIF_DOUT12, - DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, - DA850_VPIF_DOUT15, - DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, }; enum davinci_tnetv107x_index { diff --git a/trunk/arch/arm/mach-davinci/include/mach/psc.h b/trunk/arch/arm/mach-davinci/include/mach/psc.h index 40a0027838e8..405318e35bf6 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/psc.h +++ b/trunk/arch/arm/mach-davinci/include/mach/psc.h @@ -166,7 +166,6 @@ #define DA830_LPSC1_McASP1 8 #define DA850_LPSC1_SATA 8 #define DA830_LPSC1_McASP2 9 -#define DA850_LPSC1_VPIF 9 #define DA8XX_LPSC1_SPI1 10 #define DA8XX_LPSC1_I2C 11 #define DA8XX_LPSC1_UART1 12 diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index c05d7aa84031..85fc2feb0af0 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -378,10 +378,10 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = { }; static struct regulator_consumer_supply __initdata max8997_ldo3_[] = { REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */ - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata max8997_ldo4_[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata max8997_ldo5_[] = { REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */ @@ -1180,7 +1180,9 @@ static struct platform_device cam_8m_12v_fixed_rdev = { static struct s5p_platform_mipi_csis mipi_csis_platdata = { .clk_rate = 166000000UL, .lanes = 2, + .alignment = 32, .hs_settle = 12, + .phy_enable = s5p_csis_phy_enable, }; #define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */ @@ -1224,6 +1226,7 @@ static struct s5p_fimc_isp_info nuri_camera_sensors[] = { .bus_type = FIMC_MIPI_CSI2, .board_info = &m5mols_board_info, .clk_frequency = 24000000UL, + .csi_data_align = 32, }, }; diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 9adf491674ea..c11a62e23dcc 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -97,12 +97,12 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { }; static struct regulator_consumer_supply __initdata ldo3_consumer[] = { - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */ REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */ }; static struct regulator_consumer_supply __initdata ldo6_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */ + REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ }; static struct regulator_consumer_supply __initdata ldo7_consumer[] = { REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c index ebc9dd339a38..08b81fd99505 100644 --- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c +++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c @@ -209,7 +209,7 @@ static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), - REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), + REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), }; static struct regulator_init_data lp3974_ldo3_data = { @@ -273,7 +273,7 @@ static struct regulator_init_data lp3974_ldo6_data = { }; static struct regulator_consumer_supply lp3974_ldo7_consumer[] = { - REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), + REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), }; static struct regulator_init_data lp3974_ldo7_data = { @@ -942,7 +942,9 @@ static struct platform_device cam_s_if_fixed_reg_dev = { static struct s5p_platform_mipi_csis mipi_csis_platdata = { .clk_rate = 166000000UL, .lanes = 2, + .alignment = 32, .hs_settle = 12, + .phy_enable = s5p_csis_phy_enable, }; #define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) @@ -1006,6 +1008,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = { .board_info = &m5mols_board_info, .i2c_bus_num = 0, .clk_frequency = 24000000UL, + .csi_data_align = 32, }, }; diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig index c9a4963b5c3d..101b9681c08c 100644 --- a/trunk/arch/arm/mm/Kconfig +++ b/trunk/arch/arm/mm/Kconfig @@ -624,23 +624,6 @@ config ARM_THUMBEE Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE. -config ARM_VIRT_EXT - bool "Native support for the ARM Virtualization Extensions" - depends on MMU && CPU_V7 - help - Enable the kernel to make use of the ARM Virtualization - Extensions to install hypervisors without run-time firmware - assistance. - - A compliant bootloader is required in order to make maximum - use of this feature. Refer to Documentation/arm/Booting for - details. - - It is safe to enable this option even if the kernel may not be - booted in HYP mode, may not have support for the - virtualization extensions, or may be booted with a - non-compliant bootloader. - config SWP_EMULATE bool "Emulate SWP/SWPB instructions" depends on !CPU_USE_DOMAINS && CPU_V7 diff --git a/trunk/arch/arm/mm/cache-fa.S b/trunk/arch/arm/mm/cache-fa.S index e505befe51b5..072016371093 100644 --- a/trunk/arch/arm/mm/cache-fa.S +++ b/trunk/arch/arm/mm/cache-fa.S @@ -240,9 +240,6 @@ ENTRY(fa_dma_unmap_area) mov pc, lr ENDPROC(fa_dma_unmap_area) - .globl fa_flush_kern_cache_louis - .equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v3.S b/trunk/arch/arm/mm/cache-v3.S index 8a3fadece8d3..52e35f32eefb 100644 --- a/trunk/arch/arm/mm/cache-v3.S +++ b/trunk/arch/arm/mm/cache-v3.S @@ -128,9 +128,6 @@ ENTRY(v3_dma_map_area) ENDPROC(v3_dma_unmap_area) ENDPROC(v3_dma_map_area) - .globl v3_flush_kern_cache_louis - .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v4.S b/trunk/arch/arm/mm/cache-v4.S index 43e5d77be677..022135d2b7e4 100644 --- a/trunk/arch/arm/mm/cache-v4.S +++ b/trunk/arch/arm/mm/cache-v4.S @@ -140,9 +140,6 @@ ENTRY(v4_dma_map_area) ENDPROC(v4_dma_unmap_area) ENDPROC(v4_dma_map_area) - .globl v4_flush_kern_cache_louis - .equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v4wb.S b/trunk/arch/arm/mm/cache-v4wb.S index cd4945321407..8f1eeae340c8 100644 --- a/trunk/arch/arm/mm/cache-v4wb.S +++ b/trunk/arch/arm/mm/cache-v4wb.S @@ -251,9 +251,6 @@ ENTRY(v4wb_dma_unmap_area) mov pc, lr ENDPROC(v4wb_dma_unmap_area) - .globl v4wb_flush_kern_cache_louis - .equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v4wt.S b/trunk/arch/arm/mm/cache-v4wt.S index 11e5e5838bc5..b34a5f908a82 100644 --- a/trunk/arch/arm/mm/cache-v4wt.S +++ b/trunk/arch/arm/mm/cache-v4wt.S @@ -196,9 +196,6 @@ ENTRY(v4wt_dma_map_area) ENDPROC(v4wt_dma_unmap_area) ENDPROC(v4wt_dma_map_area) - .globl v4wt_flush_kern_cache_louis - .equ v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v6.S b/trunk/arch/arm/mm/cache-v6.S index d8fd4d4bd3d4..4b10760c56d6 100644 --- a/trunk/arch/arm/mm/cache-v6.S +++ b/trunk/arch/arm/mm/cache-v6.S @@ -326,9 +326,6 @@ ENTRY(v6_dma_unmap_area) mov pc, lr ENDPROC(v6_dma_unmap_area) - .globl v6_flush_kern_cache_louis - .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all - __INITDATA @ define struct cpu_cache_fns (see and proc-macros.S) diff --git a/trunk/arch/arm/mm/cache-v7.S b/trunk/arch/arm/mm/cache-v7.S index cd956647c21a..3b172275262e 100644 --- a/trunk/arch/arm/mm/cache-v7.S +++ b/trunk/arch/arm/mm/cache-v7.S @@ -33,24 +33,6 @@ ENTRY(v7_flush_icache_all) mov pc, lr ENDPROC(v7_flush_icache_all) - /* - * v7_flush_dcache_louis() - * - * Flush the D-cache up to the Level of Unification Inner Shareable - * - * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) - */ - -ENTRY(v7_flush_dcache_louis) - dmb @ ensure ordering with previous memory accesses - mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr - mov r3, r3, lsr #20 @ r3 = LoUIS * 2 - moveq pc, lr @ return if level == 0 - mov r10, #0 @ r10 (starting level) = 0 - b flush_levels @ start flushing cache levels -ENDPROC(v7_flush_dcache_louis) - /* * v7_flush_dcache_all() * @@ -67,7 +49,7 @@ ENTRY(v7_flush_dcache_all) mov r3, r3, lsr #23 @ left align loc bit field beq finished @ if loc is 0, then no need to clean mov r10, #0 @ start clean at cache level 0 -flush_levels: +loop1: add r2, r10, r10, lsr #1 @ work out 3x current cache level mov r1, r0, lsr r2 @ extract cache type bits from clidr and r1, r1, #7 @ mask of the bits for current cache only @@ -89,9 +71,9 @@ flush_levels: clz r5, r4 @ find bit position of way size increment ldr r7, =0x7fff ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop1: - mov r9, r4 @ create working copy of max way size loop2: + mov r9, r4 @ create working copy of max way size +loop3: ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 THUMB( lsl r6, r9, r5 ) THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 @@ -100,13 +82,13 @@ loop2: THUMB( orr r11, r11, r6 ) @ factor index number into r11 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way subs r9, r9, #1 @ decrement the way - bge loop2 + bge loop3 subs r7, r7, #1 @ decrement the index - bge loop1 + bge loop2 skip: add r10, r10, #2 @ increment cache number cmp r3, r10 - bgt flush_levels + bgt loop1 finished: mov r10, #0 @ swith back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr @@ -138,24 +120,6 @@ ENTRY(v7_flush_kern_cache_all) mov pc, lr ENDPROC(v7_flush_kern_cache_all) - /* - * v7_flush_kern_cache_louis(void) - * - * Flush the data cache up to Level of Unification Inner Shareable. - * Invalidate the I-cache to the point of unification. - */ -ENTRY(v7_flush_kern_cache_louis) - ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) - bl v7_flush_dcache_louis - mov r0, #0 - ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable - ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate - ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) - mov pc, lr -ENDPROC(v7_flush_kern_cache_louis) - /* * v7_flush_cache_all() * diff --git a/trunk/arch/arm/mm/proc-arm1020.S b/trunk/arch/arm/mm/proc-arm1020.S index 2bb61e703d6c..0650bb87c1e3 100644 --- a/trunk/arch/arm/mm/proc-arm1020.S +++ b/trunk/arch/arm/mm/proc-arm1020.S @@ -368,9 +368,6 @@ ENTRY(arm1020_dma_unmap_area) mov pc, lr ENDPROC(arm1020_dma_unmap_area) - .globl arm1020_flush_kern_cache_louis - .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm1020 diff --git a/trunk/arch/arm/mm/proc-arm1020e.S b/trunk/arch/arm/mm/proc-arm1020e.S index 8f96aa40f510..4188478325a6 100644 --- a/trunk/arch/arm/mm/proc-arm1020e.S +++ b/trunk/arch/arm/mm/proc-arm1020e.S @@ -354,9 +354,6 @@ ENTRY(arm1020e_dma_unmap_area) mov pc, lr ENDPROC(arm1020e_dma_unmap_area) - .globl arm1020e_flush_kern_cache_louis - .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm1020e diff --git a/trunk/arch/arm/mm/proc-arm1022.S b/trunk/arch/arm/mm/proc-arm1022.S index 8ebe4a469a22..33c68824bff0 100644 --- a/trunk/arch/arm/mm/proc-arm1022.S +++ b/trunk/arch/arm/mm/proc-arm1022.S @@ -343,9 +343,6 @@ ENTRY(arm1022_dma_unmap_area) mov pc, lr ENDPROC(arm1022_dma_unmap_area) - .globl arm1022_flush_kern_cache_louis - .equ arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm1022 diff --git a/trunk/arch/arm/mm/proc-arm1026.S b/trunk/arch/arm/mm/proc-arm1026.S index 093fc7e520c3..fbc1d5fc24dc 100644 --- a/trunk/arch/arm/mm/proc-arm1026.S +++ b/trunk/arch/arm/mm/proc-arm1026.S @@ -337,9 +337,6 @@ ENTRY(arm1026_dma_unmap_area) mov pc, lr ENDPROC(arm1026_dma_unmap_area) - .globl arm1026_flush_kern_cache_louis - .equ arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm1026 diff --git a/trunk/arch/arm/mm/proc-arm920.S b/trunk/arch/arm/mm/proc-arm920.S index 2c3b9421ab5e..1a8c138eb897 100644 --- a/trunk/arch/arm/mm/proc-arm920.S +++ b/trunk/arch/arm/mm/proc-arm920.S @@ -319,9 +319,6 @@ ENTRY(arm920_dma_unmap_area) mov pc, lr ENDPROC(arm920_dma_unmap_area) - .globl arm920_flush_kern_cache_louis - .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm920 #endif diff --git a/trunk/arch/arm/mm/proc-arm922.S b/trunk/arch/arm/mm/proc-arm922.S index 4464c49d7449..4c44d7e1c3ca 100644 --- a/trunk/arch/arm/mm/proc-arm922.S +++ b/trunk/arch/arm/mm/proc-arm922.S @@ -321,9 +321,6 @@ ENTRY(arm922_dma_unmap_area) mov pc, lr ENDPROC(arm922_dma_unmap_area) - .globl arm922_flush_kern_cache_louis - .equ arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm922 #endif diff --git a/trunk/arch/arm/mm/proc-arm925.S b/trunk/arch/arm/mm/proc-arm925.S index 281eb9b9c1d6..ec5b1180994f 100644 --- a/trunk/arch/arm/mm/proc-arm925.S +++ b/trunk/arch/arm/mm/proc-arm925.S @@ -376,9 +376,6 @@ ENTRY(arm925_dma_unmap_area) mov pc, lr ENDPROC(arm925_dma_unmap_area) - .globl arm925_flush_kern_cache_louis - .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm925 diff --git a/trunk/arch/arm/mm/proc-arm926.S b/trunk/arch/arm/mm/proc-arm926.S index f1803f7e2972..c31e62c606c0 100644 --- a/trunk/arch/arm/mm/proc-arm926.S +++ b/trunk/arch/arm/mm/proc-arm926.S @@ -339,9 +339,6 @@ ENTRY(arm926_dma_unmap_area) mov pc, lr ENDPROC(arm926_dma_unmap_area) - .globl arm926_flush_kern_cache_louis - .equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm926 diff --git a/trunk/arch/arm/mm/proc-arm940.S b/trunk/arch/arm/mm/proc-arm940.S index 8da189d4a402..a613a7dd7146 100644 --- a/trunk/arch/arm/mm/proc-arm940.S +++ b/trunk/arch/arm/mm/proc-arm940.S @@ -267,9 +267,6 @@ ENTRY(arm940_dma_unmap_area) mov pc, lr ENDPROC(arm940_dma_unmap_area) - .globl arm940_flush_kern_cache_louis - .equ arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm940 diff --git a/trunk/arch/arm/mm/proc-arm946.S b/trunk/arch/arm/mm/proc-arm946.S index f666cf34075a..9f4f2999fdd0 100644 --- a/trunk/arch/arm/mm/proc-arm946.S +++ b/trunk/arch/arm/mm/proc-arm946.S @@ -310,9 +310,6 @@ ENTRY(arm946_dma_unmap_area) mov pc, lr ENDPROC(arm946_dma_unmap_area) - .globl arm946_flush_kern_cache_louis - .equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions arm946 diff --git a/trunk/arch/arm/mm/proc-feroceon.S b/trunk/arch/arm/mm/proc-feroceon.S index 4106b09e0c29..23a8e4c7f2bd 100644 --- a/trunk/arch/arm/mm/proc-feroceon.S +++ b/trunk/arch/arm/mm/proc-feroceon.S @@ -415,9 +415,6 @@ ENTRY(feroceon_dma_unmap_area) mov pc, lr ENDPROC(feroceon_dma_unmap_area) - .globl feroceon_flush_kern_cache_louis - .equ feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions feroceon @@ -434,7 +431,6 @@ ENDPROC(feroceon_dma_unmap_area) range_alias flush_icache_all range_alias flush_user_cache_all range_alias flush_kern_cache_all - range_alias flush_kern_cache_louis range_alias flush_user_cache_range range_alias coherent_kern_range range_alias coherent_user_range diff --git a/trunk/arch/arm/mm/proc-macros.S b/trunk/arch/arm/mm/proc-macros.S index b29a2265af01..2d8ff3ad86d3 100644 --- a/trunk/arch/arm/mm/proc-macros.S +++ b/trunk/arch/arm/mm/proc-macros.S @@ -299,7 +299,6 @@ ENTRY(\name\()_processor_functions) ENTRY(\name\()_cache_fns) .long \name\()_flush_icache_all .long \name\()_flush_kern_cache_all - .long \name\()_flush_kern_cache_louis .long \name\()_flush_user_cache_all .long \name\()_flush_user_cache_range .long \name\()_coherent_kern_range diff --git a/trunk/arch/arm/mm/proc-mohawk.S b/trunk/arch/arm/mm/proc-mohawk.S index 82f9cdc751d6..fbb2124a547d 100644 --- a/trunk/arch/arm/mm/proc-mohawk.S +++ b/trunk/arch/arm/mm/proc-mohawk.S @@ -303,9 +303,6 @@ ENTRY(mohawk_dma_unmap_area) mov pc, lr ENDPROC(mohawk_dma_unmap_area) - .globl mohawk_flush_kern_cache_louis - .equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions mohawk diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index 846d279f3176..c2e2b66f72b5 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -172,7 +172,7 @@ __v7_ca15mp_setup: __v7_setup: adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} - bl v7_flush_dcache_louis + bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} mrc p15, 0, r0, c0, c0, 0 @ read main ID register diff --git a/trunk/arch/arm/mm/proc-xsc3.S b/trunk/arch/arm/mm/proc-xsc3.S index eb93d6487f35..b0d57869da2d 100644 --- a/trunk/arch/arm/mm/proc-xsc3.S +++ b/trunk/arch/arm/mm/proc-xsc3.S @@ -337,9 +337,6 @@ ENTRY(xsc3_dma_unmap_area) mov pc, lr ENDPROC(xsc3_dma_unmap_area) - .globl xsc3_flush_kern_cache_louis - .equ xsc3_flush_kern_cache_louis, xsc3_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions xsc3 diff --git a/trunk/arch/arm/mm/proc-xscale.S b/trunk/arch/arm/mm/proc-xscale.S index 25510361aa18..4ffebaa595ee 100644 --- a/trunk/arch/arm/mm/proc-xscale.S +++ b/trunk/arch/arm/mm/proc-xscale.S @@ -410,9 +410,6 @@ ENTRY(xscale_dma_unmap_area) mov pc, lr ENDPROC(xscale_dma_unmap_area) - .globl xscale_flush_kern_cache_louis - .equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all - @ define struct cpu_cache_fns (see and proc-macros.S) define_cache_functions xscale @@ -442,7 +439,6 @@ ENDPROC(xscale_dma_unmap_area) a0_alias flush_icache_all a0_alias flush_user_cache_all a0_alias flush_kern_cache_all - a0_alias flush_kern_cache_louis a0_alias flush_user_cache_range a0_alias coherent_kern_range a0_alias coherent_user_range diff --git a/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h index c08a54d9d889..826de74bfdd1 100644 --- a/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h +++ b/trunk/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h @@ -45,12 +45,6 @@ #define NMK_GPIO_ALT_B 2 #define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) -#define NMK_GPIO_ALT_CX_SHIFT 2 -#define NMK_GPIO_ALT_C1 ((1< #include -static int __s5p_mipi_phy_control(int id, bool on, u32 reset) +static int __s5p_mipi_phy_control(struct platform_device *pdev, + bool on, u32 reset) { static DEFINE_SPINLOCK(lock); void __iomem *addr; unsigned long flags; + int pid; u32 cfg; - id = max(0, id); - if (id > 1) + if (!pdev) return -EINVAL; - addr = S5P_MIPI_DPHY_CONTROL(id); + pid = (pdev->id == -1) ? 0 : pdev->id; + + if (pid != 0 && pid != 1) + return -EINVAL; + + addr = S5P_MIPI_DPHY_CONTROL(pid); spin_lock_irqsave(&lock, flags); @@ -46,12 +52,12 @@ static int __s5p_mipi_phy_control(int id, bool on, u32 reset) return 0; } -int s5p_csis_phy_enable(int id, bool on) +int s5p_csis_phy_enable(struct platform_device *pdev, bool on) { - return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); + return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN); } int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) { - return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); + return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN); } diff --git a/trunk/arch/ia64/Kconfig b/trunk/arch/ia64/Kconfig index 4c10e607c908..3c720ef6c32d 100644 --- a/trunk/arch/ia64/Kconfig +++ b/trunk/arch/ia64/Kconfig @@ -39,7 +39,7 @@ config IA64 select ARCH_TASK_STRUCT_ALLOCATOR select ARCH_THREAD_INFO_ALLOCATOR select ARCH_CLOCKSOURCE_DATA - select GENERIC_TIME_VSYSCALL_OLD + select GENERIC_TIME_VSYSCALL default y help The Itanium Processor Family is Intel's 64-bit successor to diff --git a/trunk/arch/ia64/kernel/time.c b/trunk/arch/ia64/kernel/time.c index f6388216080d..80ff9acc5edf 100644 --- a/trunk/arch/ia64/kernel/time.c +++ b/trunk/arch/ia64/kernel/time.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include @@ -454,7 +454,7 @@ void update_vsyscall_tz(void) { } -void update_vsyscall_old(struct timespec *wall, struct timespec *wtm, +void update_vsyscall(struct timespec *wall, struct timespec *wtm, struct clocksource *c, u32 mult) { write_seqcount_begin(&fsyscall_gtod_data.seq); diff --git a/trunk/arch/powerpc/Kconfig b/trunk/arch/powerpc/Kconfig index 969f3d9ded91..78d6588b6e86 100644 --- a/trunk/arch/powerpc/Kconfig +++ b/trunk/arch/powerpc/Kconfig @@ -137,7 +137,7 @@ config PPC select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_SMP_IDLE_THREAD select GENERIC_CMOS_UPDATE - select GENERIC_TIME_VSYSCALL_OLD + select GENERIC_TIME_VSYSCALL select GENERIC_CLOCKEVENTS select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER diff --git a/trunk/arch/powerpc/kernel/time.c b/trunk/arch/powerpc/kernel/time.c index ce4cb772dc78..c9986fd400d8 100644 --- a/trunk/arch/powerpc/kernel/time.c +++ b/trunk/arch/powerpc/kernel/time.c @@ -73,7 +73,7 @@ /* powerpc clocksource/clockevent code */ #include -#include +#include static cycle_t rtc_read(struct clocksource *); static struct clocksource clocksource_rtc = { @@ -727,7 +727,7 @@ static cycle_t timebase_read(struct clocksource *cs) return (cycle_t)get_tb(); } -void update_vsyscall_old(struct timespec *wall_time, struct timespec *wtm, +void update_vsyscall(struct timespec *wall_time, struct timespec *wtm, struct clocksource *clock, u32 mult) { u64 new_tb_to_xs, new_stamp_xsec; diff --git a/trunk/arch/s390/Kconfig b/trunk/arch/s390/Kconfig index e5dac1236185..99d2d790d152 100644 --- a/trunk/arch/s390/Kconfig +++ b/trunk/arch/s390/Kconfig @@ -131,7 +131,7 @@ config S390 select HAVE_UID16 if 32BIT select ARCH_WANT_IPC_PARSE_VERSION select GENERIC_SMP_IDLE_THREAD - select GENERIC_TIME_VSYSCALL_OLD + select GENERIC_TIME_VSYSCALL select GENERIC_CLOCKEVENTS select KTIME_SCALAR if 32BIT select HAVE_ARCH_SECCOMP_FILTER diff --git a/trunk/arch/s390/kernel/time.c b/trunk/arch/s390/kernel/time.c index 7fcd690d42c7..2db1011b8b19 100644 --- a/trunk/arch/s390/kernel/time.c +++ b/trunk/arch/s390/kernel/time.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include @@ -219,7 +219,7 @@ struct clocksource * __init clocksource_default_clock(void) return &clocksource_tod; } -void update_vsyscall_old(struct timespec *wall_time, struct timespec *wtm, +void update_vsyscall(struct timespec *wall_time, struct timespec *wtm, struct clocksource *clock, u32 mult) { if (clock != &clocksource_tod) diff --git a/trunk/arch/x86/include/asm/vgtod.h b/trunk/arch/x86/include/asm/vgtod.h index 46e24d36b7da..8b38be2de9e1 100644 --- a/trunk/arch/x86/include/asm/vgtod.h +++ b/trunk/arch/x86/include/asm/vgtod.h @@ -17,8 +17,8 @@ struct vsyscall_gtod_data { /* open coded 'struct timespec' */ time_t wall_time_sec; - u64 wall_time_snsec; - u64 monotonic_time_snsec; + u32 wall_time_nsec; + u32 monotonic_time_nsec; time_t monotonic_time_sec; struct timezone sys_tz; diff --git a/trunk/arch/x86/kernel/setup.c b/trunk/arch/x86/kernel/setup.c index a2bb18e02839..d609be046b57 100644 --- a/trunk/arch/x86/kernel/setup.c +++ b/trunk/arch/x86/kernel/setup.c @@ -68,7 +68,6 @@ #include #include #include -#include #include