From a3ea6d6e28e9d70a6d56fbf2b0af39b5a114c997 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Thu, 24 Apr 2008 20:58:33 +0100 Subject: [PATCH] --- yaml --- r: 94950 b: refs/heads/master c: 136eb955773dc99f82e6e754038eb1c530e03fdf h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-at91/pm.c | 14 +++++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 80db506cd1cc..350f25ae0d4b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fe6cfde60012d4891470828a391274d94e0ea3a0 +refs/heads/master: 136eb955773dc99f82e6e754038eb1c530e03fdf diff --git a/trunk/arch/arm/mach-at91/pm.c b/trunk/arch/arm/mach-at91/pm.c index 39733b6992aa..aa863c157708 100644 --- a/trunk/arch/arm/mach-at91/pm.c +++ b/trunk/arch/arm/mach-at91/pm.c @@ -61,6 +61,15 @@ static inline void sdram_selfrefresh_enable(void) #else #include +#ifdef CONFIG_ARCH_AT91SAM9263 +/* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; + * handle those cases both here and in the Suspend-To-RAM support. + */ +#define AT91_SDRAMC AT91_SDRAMC0 +#warning Assuming EB1 SDRAM controller is *NOT* used +#endif + static u32 saved_lpr; static inline void sdram_selfrefresh_enable(void) @@ -75,11 +84,6 @@ static inline void sdram_selfrefresh_enable(void) #define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -/* - * FIXME: The AT91SAM9263 has a second EBI controller which may have - * additional SDRAM. pm_slowclock.S will require a similar fix. - */ - #endif