From a44b2798407d2471bea77303be0befb1b351ca15 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Mon, 1 Oct 2012 02:47:28 +0530 Subject: [PATCH] --- yaml --- r: 339619 b: refs/heads/master c: 3852ccd66a9bcb2aa6f46bce5442b6d8d08e5b5d h: refs/heads/master i: 339617: e1b7bf770e34b5145da8f0eb97570877e0e9f473 339615: 7d8bdd0d06cdc3e5eb85baf5a13dd48147904d43 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/gpmc-nand.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e1e46b9d5ad8..6fb0f0eefdd6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 47f88af4ed80ac9ca593543e21ebf86a31d7e8ba +refs/heads/master: 3852ccd66a9bcb2aa6f46bce5442b6d8d08e5b5d diff --git a/trunk/arch/arm/mach-omap2/gpmc-nand.c b/trunk/arch/arm/mach-omap2/gpmc-nand.c index abdb78a95a94..e89a36c8143b 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-nand.c +++ b/trunk/arch/arm/mach-omap2/gpmc-nand.c @@ -90,6 +90,27 @@ static int omap2_nand_gpmc_retime( return 0; } +static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) +{ + /* support only OMAP3 class */ + if (!cpu_is_omap34xx()) { + pr_err("BCH ecc is not supported on this CPU\n"); + return 0; + } + + /* + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. + * Other chips may be added if confirmed to work. + */ + if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + pr_err("BCH 4-bit mode is not supported on this CPU\n"); + return 0; + } + + return 1; +} + int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -128,6 +149,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); + if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) + return -EINVAL; + err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n");