From a4b09b86dc64d81d274eeb570a7e37987c2f723b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 27 Oct 2009 12:11:09 -0400
Subject: [PATCH] --- yaml --- r: 168475 b: refs/heads/master c:
 d56ef9c8fd34ed29ffae27598a864b4a9a82521b h: refs/heads/master i:   168473:
 9ca1d52661581de9333e39575765a921c248b1b7   168471:
 cfd9525498b63c324e8735775c30e1e8aec0bc94 v: v3

---
 [refs]                                       |  2 +-
 trunk/drivers/gpu/drm/radeon/atombios_crtc.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 4868d88ee188..c42080b9a499 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8f552a66a40bcc6e903e91310f42fe140e0342c4
+refs/heads/master: d56ef9c8fd34ed29ffae27598a864b4a9a82521b
diff --git a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
index e5a3c301b7a9..8516e1b2329a 100644
--- a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -483,8 +483,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 		atom_execute_table(rdev->mode_info.atom_context,
 				   index, (uint32_t *)&adjust_pll_args);
 		adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
-	} else
-		adjusted_clock = mode->clock;
+	} else {
+		/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
+		if (ASIC_IS_AVIVO(rdev) &&
+		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
+			adjusted_clock = mode->clock * 2;
+		else
+			adjusted_clock = mode->clock;
+	}
 
 	if (radeon_crtc->crtc_id == 0)
 		pll = &rdev->clock.p1pll;