diff --git a/[refs] b/[refs]
index f33d9ca03fb9..e240ded5ab75 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a06f5466c4576dcbf838a50a87903b0082774da7
+refs/heads/master: 217874feed0d3a6543a6b7127782f4a08bffd731
diff --git a/trunk/arch/arm/mm/cache-v6.S b/trunk/arch/arm/mm/cache-v6.S
index 85c10a71e7c6..72966d90e956 100644
--- a/trunk/arch/arm/mm/cache-v6.S
+++ b/trunk/arch/arm/mm/cache-v6.S
@@ -18,6 +18,7 @@
 #define HARVARD_CACHE
 #define CACHE_LINE_SIZE		32
 #define D_CACHE_LINE_SIZE	32
+#define BTB_FLUSH_SIZE		8
 
 /*
  *	v6_flush_cache_all()
@@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range)
 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I line
 #endif
 	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
-	add	r0, r0, #CACHE_LINE_SIZE
+	add	r0, r0, #BTB_FLUSH_SIZE
+	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
+	add	r0, r0, #BTB_FLUSH_SIZE
+	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
+	add	r0, r0, #BTB_FLUSH_SIZE
+	mcr	p15, 0, r0, c7, c5, 7		@ invalidate BTB entry
+	add	r0, r0, #BTB_FLUSH_SIZE
 	cmp	r0, r1
 	blo	1b
 #ifdef HARVARD_CACHE