From a6f8e6f90f15d6935ea5d90485f5ab2c1997ac5c Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Thu, 27 May 2010 10:26:43 +0800 Subject: [PATCH] --- yaml --- r: 199615 b: refs/heads/master c: a1786bd270b08834a735e06c3d5430eeb0baf017 h: refs/heads/master i: 199613: 9f4779ab9468bbd0ce003b40991ed205b89664ab 199611: 7cf2aa5d8b44b44cf016682e588fff6748ca3534 199607: b6af910e7f56d733eb5892f96d50df9315af58ed 199599: cc5a86fe9b9385f9a1289c574c41c83e6f0677ec 199583: 7a6c98ef28e3dd7a1dbe19e4b92a5f816a8bc89b 199551: b1317a4a6941c93a68a5ea2a722d94793bd60af9 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index d97a81dd98c4..f720eb4b0010 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ca76482e0f4b64942c704fa11c620ffd1bdd8475 +refs/heads/master: a1786bd270b08834a735e06c3d5430eeb0baf017 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index af7b10853e33..64b0a3afd92b 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -369,6 +369,25 @@ #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ +/* GEN6 interrupt control */ +#define GEN6_RENDER_HWSTAM 0x2098 +#define GEN6_RENDER_IMR 0x20a8 +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0) + +#define GEN6_BLITTER_HWSTAM 0x22098 +#define GEN6_BLITTER_IMR 0x220a8 +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) /* * BSD (bit stream decoder instruction and interrupt control register defines * (G4X and Ironlake only)