From a74d8c18aa00eecf7797d16aad2d208241e6ba9d Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 23 Jun 2011 14:48:54 -0500 Subject: [PATCH] --- yaml --- r: 259112 b: refs/heads/master c: 7b93eccf2876ba3b1c10dae22ca864a0eb08de4f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/powerpc/platforms/85xx/p1022_ds.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 0d80f8a297bb..6f8bc8d04f4b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ebf714ff37561331eb39963945d80bfc2a59e00f +refs/heads/master: 7b93eccf2876ba3b1c10dae22ca864a0eb08de4f diff --git a/trunk/arch/powerpc/platforms/85xx/p1022_ds.c b/trunk/arch/powerpc/platforms/85xx/p1022_ds.c index e083e1f4a6f4..266b3aadfe5e 100644 --- a/trunk/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/trunk/arch/powerpc/platforms/85xx/p1022_ds.c @@ -195,8 +195,13 @@ void p1022ds_set_pixel_clock(unsigned int pixclock) do_div(temp, pixclock); freq = temp; - /* pixclk is the ratio of the platform clock to the pixel clock */ + /* + * 'pxclk' is the ratio of the platform clock to the pixel clock. + * This number is programmed into the CLKDVDR register, and the valid + * range of values is 2-255. + */ pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); + pxclk = clamp_t(u32, pxclk, 2, 255); /* Disable the pixel clock, and set it to non-inverted and no delay */ clrbits32(&guts->clkdvdr,