From a820dee5b9b353582142419d39c0929f2bc43ef5 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Fri, 4 Feb 2011 15:24:11 +0100
Subject: [PATCH] --- yaml --- r: 233151 b: refs/heads/master c:
 0eb6aaf52965c14ba3ea245448c4806cfcd1d18c h: refs/heads/master i:   233149:
 1c11df6458aa0fc27a49781332007de9429e718f   233147:
 33b55f057aba1439d06d4c996bde210b8b71153d   233143:
 a8afba692f742ac8d7bf4ca56b54d0844c7e51ec   233135:
 5cae0d93fe318d4da215e711c06628e75cac4af7   233119:
 d54cf07fd62ef63b4561e9fdfe0b520e069799a2   233087:
 c1ce728dead9be1cb4429a950cdd4e8dbc040e68 v: v3

---
 [refs]                               |  2 +-
 trunk/arch/microblaze/kernel/head.S  | 15 +++++++--------
 trunk/arch/microblaze/kernel/setup.c |  4 ++--
 3 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/[refs] b/[refs]
index 34c0f3efe376..272433571926 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1f80a67da2da4180355bc36b2691f16684b194fd
+refs/heads/master: 0eb6aaf52965c14ba3ea245448c4806cfcd1d18c
diff --git a/trunk/arch/microblaze/kernel/head.S b/trunk/arch/microblaze/kernel/head.S
index 0db20b5abb54..778a5ce2e4fc 100644
--- a/trunk/arch/microblaze/kernel/head.S
+++ b/trunk/arch/microblaze/kernel/head.S
@@ -62,15 +62,14 @@ real_start:
 	andi	r1, r1, ~2
 	mts	rmsr, r1
 /*
- * Here is checking mechanism which check if Microblaze has msr instructions
- * We load msr and compare it with previous r1 value - if is the same,
- * msr instructions works if not - cpu don't have them.
+ * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
+ * if the msrclr instruction is not enabled. We use this to detect
+ * if the opcode is available, by issuing msrclr and then testing the result.
+ * r8 == 0 - msr instructions are implemented
+ * r8 != 0 - msr instructions are not implemented
  */
-	/* r8=0 - I have msr instr, 1 - I don't have them */
-	rsubi	r0, r0, 1	/* set the carry bit */
-	msrclr	r0, 0x4		/* try to clear it */
-	/* read the carry bit, r8 will be '0' if msrclr exists */
-	addik	r8, r0, 0
+	msrclr	r8, 0 /* clear nothing - just read msr for test */
+	cmpu	r8, r8, r1 /* r1 must contain msr reg content */
 
 /* r7 may point to an FDT, or there may be one linked in.
    if it's in r7, we've got to save it away ASAP.
diff --git a/trunk/arch/microblaze/kernel/setup.c b/trunk/arch/microblaze/kernel/setup.c
index bb1558e4b283..9312fbb37efd 100644
--- a/trunk/arch/microblaze/kernel/setup.c
+++ b/trunk/arch/microblaze/kernel/setup.c
@@ -161,11 +161,11 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
 	if (msr)
 		eprintk("!!!Your kernel has setup MSR instruction but "
-				"CPU don't have it %d\n", msr);
+				"CPU don't have it %x\n", msr);
 #else
 	if (!msr)
 		eprintk("!!!Your kernel not setup MSR instruction but "
-				"CPU have it %d\n", msr);
+				"CPU have it %x\n", msr);
 #endif
 
 	for (src = __ivt_start; src < __ivt_end; src++, dst++)