From a8e44a79850a1fd2db81dadbe665e2cc5698c489 Mon Sep 17 00:00:00 2001
From: Hong Liu <hong.liu@intel.com>
Date: Mon, 26 Jul 2010 10:05:52 +0100
Subject: [PATCH] --- yaml --- r: 202513 b: refs/heads/master c:
 215c330fe92be8d9f74bc292ea085dbe2ace6bf5 h: refs/heads/master i:   202511:
 5f9bd8e0f693439bcc438ba9d514181b220bc8f1 v: v3

---
 [refs]                                     |  2 +-
 trunk/drivers/platform/x86/intel_scu_ipc.c | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/[refs] b/[refs]
index 94a1d49c6865..ffb244e18b21 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6c8d0fdbe88e8bb1a07fa9a2830767cc180f7d1b
+refs/heads/master: 215c330fe92be8d9f74bc292ea085dbe2ace6bf5
diff --git a/trunk/drivers/platform/x86/intel_scu_ipc.c b/trunk/drivers/platform/x86/intel_scu_ipc.c
index 5055c523c5e2..84a2d4bfdec8 100644
--- a/trunk/drivers/platform/x86/intel_scu_ipc.c
+++ b/trunk/drivers/platform/x86/intel_scu_ipc.c
@@ -154,7 +154,7 @@ static inline int busy_loop(void) /* Wait till scu status is busy */
 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
 {
-	int i, nc, bytes;
+	int i, nc, bytes, d;
 	u32 offset = 0;
 	u32 err = 0;
 	u8 cbuf[IPC_WWBUF_SIZE] = { };
@@ -171,15 +171,16 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
 
 	if (platform != MRST_CPU_CHIP_PENWELL) {
 		bytes = 0;
-		for(i=0; i<count; i++) {
+		d = 0;
+		for (i = 0; i < count; i++) {
 			cbuf[bytes++] = addr[i];
 			cbuf[bytes++] = addr[i] >> 8;
 			if (id != IPC_CMD_PCNTRL_R)
-				cbuf[bytes++] = data[i];
+				cbuf[bytes++] = data[d++];
 			if (id == IPC_CMD_PCNTRL_M)
-				cbuf[bytes++] = data[i + 1];
+				cbuf[bytes++] = data[d++];
 		}
-		for(i=0; i<bytes; i+=4)
+		for (i = 0; i < bytes; i += 4)
 			ipc_data_writel(wbuf[i/4], i);
 		ipc_command(bytes << 16 |  id << 12 | 0 << 8 | op);
 	} else {