From a8fc4568a6d381dfdf6d544d77b22ded98718e39 Mon Sep 17 00:00:00 2001
From: "David S. Miller" <davem@davemloft.net>
Date: Mon, 4 Jan 2010 23:16:03 -0800
Subject: [PATCH] --- yaml --- r: 178775 b: refs/heads/master c:
 e04ed38d4e0cd32141f723560efcc8252b0241e2 h: refs/heads/master i:   178773:
 37bae89f0d189fa7e3b73120d003eca240b754d9   178771:
 878b03376ad27b6cd7eeb936d0474148e1315b26   178767:
 bfc60bffc40fc98f3f2d49318fe5ad6144d90a3f v: v3

---
 [refs]                               |  2 +-
 trunk/arch/sparc/kernel/perf_event.c | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 382f5277280d..64dbe6c38a37 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8183e2b38480672a1f61d416812ac078ce94b67b
+refs/heads/master: e04ed38d4e0cd32141f723560efcc8252b0241e2
diff --git a/trunk/arch/sparc/kernel/perf_event.c b/trunk/arch/sparc/kernel/perf_event.c
index fa5936e1c3b9..198fb4e79ba2 100644
--- a/trunk/arch/sparc/kernel/perf_event.c
+++ b/trunk/arch/sparc/kernel/perf_event.c
@@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
 	data.addr = 0;
 
 	cpuc = &__get_cpu_var(cpu_hw_events);
+
+	/* If the PMU has the TOE IRQ enable bits, we need to do a
+	 * dummy write to the %pcr to clear the overflow bits and thus
+	 * the interrupt.
+	 *
+	 * Do this before we peek at the counters to determine
+	 * overflow so we don't lose any events.
+	 */
+	if (sparc_pmu->irq_bit)
+		pcr_ops->write(cpuc->pcr);
+
 	for (idx = 0; idx < MAX_HWEVENTS; idx++) {
 		struct perf_event *event = cpuc->events[idx];
 		struct hw_perf_event *hwc;