From a92a17ef55e517b3bcdfab58b30f76fd3e1c60a0 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 10 May 2012 14:17:22 +0530 Subject: [PATCH] --- yaml --- r: 313416 b: refs/heads/master c: b009366f285d03e69aeea5f8cc466782dd6f0004 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/counter_32k.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 9ece63f19317..99693fedc329 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e799840a09c7e4b7e94d08a7b8c3ec4ba81611f9 +refs/heads/master: b009366f285d03e69aeea5f8cc466782dd6f0004 diff --git a/trunk/arch/arm/plat-omap/counter_32k.c b/trunk/arch/arm/plat-omap/counter_32k.c index 2132c4f389e1..dbf1e03029a5 100644 --- a/trunk/arch/arm/plat-omap/counter_32k.c +++ b/trunk/arch/arm/plat-omap/counter_32k.c @@ -29,7 +29,10 @@ #include /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ -#define OMAP2_32KSYNCNT_CR_OFF 0x10 +#define OMAP2_32KSYNCNT_REV_OFF 0x0 +#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) +#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 +#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 /* * 32KHz clocksource ... always available, on pretty most chips except @@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) int ret; /* - * 32k sync Counter register offset is at 0x10 + * 32k sync Counter IP register offsets vary between the + * highlander version and the legacy ones. + * The 'SCHEME' bits(30-31) of the revision register is used + * to identify the version. */ - sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF; + if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & + OMAP2_32KSYNCNT_REV_SCHEME) + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; + else + sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; /* * 120000 rough estimate from the calculations in