From aa0e89d51745d5c12ec6657a9cdf586a286282fb Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 6 Feb 2008 01:38:11 -0800 Subject: [PATCH] --- yaml --- r: 83490 b: refs/heads/master c: 1eed29df472a33bba013d5a2ea2f9e32f4414397 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/spi/atmel_spi.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 9920030279f5..40812701f370 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3c72426f0539c1abce17918d1456f7a6a5a11f90 +refs/heads/master: 1eed29df472a33bba013d5a2ea2f9e32f4414397 diff --git a/trunk/drivers/spi/atmel_spi.c b/trunk/drivers/spi/atmel_spi.c index ff10808183a3..b09d33678dd8 100644 --- a/trunk/drivers/spi/atmel_spi.c +++ b/trunk/drivers/spi/atmel_spi.c @@ -490,9 +490,14 @@ static int atmel_spi_setup(struct spi_device *spi) if (!(spi->mode & SPI_CPHA)) csr |= SPI_BIT(NCPHA); - /* TODO: DLYBS and DLYBCT */ - csr |= SPI_BF(DLYBS, 10); - csr |= SPI_BF(DLYBCT, 10); + /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. + * + * DLYBCT would add delays between words, slowing down transfers. + * It could potentially be useful to cope with DMA bottlenecks, but + * in those cases it's probably best to just use a lower bitrate. + */ + csr |= SPI_BF(DLYBS, 0); + csr |= SPI_BF(DLYBCT, 0); /* chipselect must have been muxed as GPIO (e.g. in board setup) */ npcs_pin = (unsigned int)spi->controller_data;