From aa2390658ecdb02ac75f548cf39b45ad3ba9dde5 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Mon, 10 Sep 2012 17:02:45 -0600
Subject: [PATCH] --- yaml --- r: 326648 b: refs/heads/master c:
 7a74a4436b20980f8e19138e857bc7e39db5ad4b h: refs/heads/master v: v3

---
 [refs]                                     | 2 +-
 trunk/arch/arm/mach-tegra/tegra20_clocks.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 63f297ac1644..c7a5764a90df 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fa67ccb61d10fbd55d1c3b5b6b537e4d74da1e4b
+refs/heads/master: 7a74a4436b20980f8e19138e857bc7e39db5ad4b
diff --git a/trunk/arch/arm/mach-tegra/tegra20_clocks.c b/trunk/arch/arm/mach-tegra/tegra20_clocks.c
index b9124afcca11..d9ce0087f6a6 100644
--- a/trunk/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/trunk/arch/arm/mach-tegra/tegra20_clocks.c
@@ -789,7 +789,7 @@ static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct clk_tegra *c = to_clk_tegra(hw);
 	const struct clk_pll_freq_table *sel;
 	unsigned long input_rate = *prate;
-	unsigned long output_rate = *prate;
+	u64 output_rate = *prate;
 	int mul;
 	int div;