From aa65c7e3a047d9e51c53c6a49fd86be224de55ac Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Sat, 30 May 2009 14:00:16 +0100
Subject: [PATCH] --- yaml --- r: 149311 b: refs/heads/master c:
 23d1c515d8fc6d74bea442a4b687c3b5b8627ec4 h: refs/heads/master i:   149309:
 8ebf1fdd2dc3d5052fb6af7c1f02d71f8ee47242   149307:
 0d85cdeb2e9cad20c7d97bd96e9632f4f02cc471   149303:
 3d5d311b8bfa47f3fb283928e271b9a7affb315e   149295:
 ef127b3a9cd477e6f4e273b6cc477589f5e5fff3   149279:
 8e0a5ea0482bb5a90a1ec758deb0245ccce5a824   149247:
 234735ab26cf1f3c80233fc18d062a1c756018da v: v3

---
 [refs]                      |  2 +-
 trunk/arch/arm/mm/proc-v7.S | 32 ++++++++++++++++++++++++++++++--
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 96e79986ed44..b74edeb91774 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 213fb2a8ee81ec106b9b370a07ccad575e9d3748
+refs/heads/master: 23d1c515d8fc6d74bea442a4b687c3b5b8627ec4
diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S
index 095b69f5a833..0a8ffd3c03fd 100644
--- a/trunk/arch/arm/mm/proc-v7.S
+++ b/trunk/arch/arm/mm/proc-v7.S
@@ -219,8 +219,36 @@ __v7_setup:
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
 #endif
-	ldr	r5, =0xff0aa1a8
-	ldr	r6, =0x40e040e0
+	/*
+	 * Memory region attributes with SCTLR.TRE=1
+	 *
+	 *   n = TEX[0],C,B
+	 *   TR = PRRR[2n+1:2n]		- memory type
+	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
+	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
+	 *
+	 *			n	TR	IR	OR
+	 *   UNCACHED		000	00
+	 *   BUFFERABLE		001	10	00	00
+	 *   WRITETHROUGH	010	10	10	10
+	 *   WRITEBACK		011	10	11	11
+	 *   reserved		110
+	 *   WRITEALLOC		111	10	01	01
+	 *   DEV_SHARED		100	01
+	 *   DEV_NONSHARED	100	01
+	 *   DEV_WC		001	10
+	 *   DEV_CACHED		011	10
+	 *
+	 * Other attributes:
+	 *
+	 *   DS0 = PRRR[16] = 0		- device shareable property
+	 *   DS1 = PRRR[17] = 1		- device shareable property
+	 *   NS0 = PRRR[18] = 0		- normal shareable property
+	 *   NS1 = PRRR[19] = 1		- normal shareable property
+	 *   NOS = PRRR[24+n] = 1	- not outer shareable
+	 */
+	ldr	r5, =0xff0a81a8			@ PRRR
+	ldr	r6, =0x40e040e0			@ NMRR
 	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
 	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
 	adr	r5, v7_crval