From ab2c9c62b171b736591c80dae0c5342e623e5fcc Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 21 Jun 2007 00:22:34 +0100 Subject: [PATCH] --- yaml --- r: 58236 b: refs/heads/master c: 4b3e975e4a06f1710693c5aa51b8f98facfa9863 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/kernel/cpu-probe.c | 15 +++++++++++++-- trunk/include/asm-mips/mipsregs.h | 2 ++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 597b7c23a74f..16e07a021299 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fde97822a295da9dffa4af643b49a58ffc4516ad +refs/heads/master: 4b3e975e4a06f1710693c5aa51b8f98facfa9863 diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index 0fc90ba16ae1..b12eeee0e974 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -137,13 +137,24 @@ static inline void check_wait(void) case CPU_4KEC: case CPU_4KSC: case CPU_5KC: - case CPU_24K: case CPU_25KF: + case CPU_PR4450: + cpu_wait = r4k_wait; + break; + + case CPU_24K: case CPU_34K: + cpu_wait = r4k_wait; + if (read_c0_config7() & MIPS_CONF7_WII) + cpu_wait = r4k_wait_irqoff; + break; + case CPU_74K: - case CPU_PR4450: cpu_wait = r4k_wait; + if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) + cpu_wait = r4k_wait_irqoff; break; + case CPU_TX49XX: cpu_wait = r4k_wait_irqoff; break; diff --git a/trunk/include/asm-mips/mipsregs.h b/trunk/include/asm-mips/mipsregs.h index 9985cb7c16e7..89c81922d47c 100644 --- a/trunk/include/asm-mips/mipsregs.h +++ b/trunk/include/asm-mips/mipsregs.h @@ -534,6 +534,8 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */