From ac055a4c1591dfc8da05bfcc0bc136b25bdbc437 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 6 Mar 2013 15:54:11 +0200 Subject: [PATCH] --- yaml --- r: 371357 b: refs/heads/master c: 7b3926b3b9d11d0fbb613ae747f44200142e1c98 h: refs/heads/master i: 371355: 0ba9048424cd54c06f2db37655ee6794c3bebc48 v: v3 --- [refs] | 2 +- trunk/drivers/video/omap2/dss/dispc.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index e9ec97fa3517..02846809b1e5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f8ad984ce0372f43006f5c700310c2d6f301085d +refs/heads/master: 7b3926b3b9d11d0fbb613ae747f44200142e1c98 diff --git a/trunk/drivers/video/omap2/dss/dispc.c b/trunk/drivers/video/omap2/dss/dispc.c index 05ff2b91d9e8..f564955ddd9e 100644 --- a/trunk/drivers/video/omap2/dss/dispc.c +++ b/trunk/drivers/video/omap2/dss/dispc.c @@ -97,6 +97,8 @@ static struct { int irq; + unsigned long core_clk_rate; + u32 fifo_size[DISPC_MAX_NR_FIFOS]; /* maps which plane is using a fifo. fifo-id -> plane-id */ int fifo_assignment[DISPC_MAX_NR_FIFOS]; @@ -2951,6 +2953,10 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, dispc_write_reg(DISPC_DIVISORo(channel), FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); + + if (dss_has_feature(FEAT_CORE_CLK_DIV) == false && + channel == OMAP_DSS_CHANNEL_LCD) + dispc.core_clk_rate = dispc_fclk_rate() / lck_div; } static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, @@ -3056,15 +3062,7 @@ unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) unsigned long dispc_core_clk_rate(void) { - int lcd; - unsigned long fclk = dispc_fclk_rate(); - - if (dss_has_feature(FEAT_CORE_CLK_DIV)) - lcd = REG_GET(DISPC_DIVISOR, 23, 16); - else - lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16); - - return fclk / lcd; + return dispc.core_clk_rate; } static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) @@ -3451,6 +3449,8 @@ static void _omap_dispc_initial_config(void) l = FLD_MOD(l, 1, 0, 0); l = FLD_MOD(l, 1, 23, 16); dispc_write_reg(DISPC_DIVISOR, l); + + dispc.core_clk_rate = dispc_fclk_rate(); } /* FUNCGATED */