From ad02712b8d8253bba70fc9b278cb3795fe8f3dbd Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Wed, 22 Aug 2012 12:00:28 +0000 Subject: [PATCH] --- yaml --- r: 329302 b: refs/heads/master c: f76c0dde78fbe021801fe904fb5999f3154d4e5d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/gma500/cdv_intel_display.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 60df31579881..b79bc2e9bc0f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4d46259f00c6dd04d53e74cdfa8f8b6ec35c0140 +refs/heads/master: f76c0dde78fbe021801fe904fb5999f3154d4e5d diff --git a/trunk/drivers/gpu/drm/gma500/cdv_intel_display.c b/trunk/drivers/gpu/drm/gma500/cdv_intel_display.c index bfb056561777..55db356d102c 100644 --- a/trunk/drivers/gpu/drm/gma500/cdv_intel_display.c +++ b/trunk/drivers/gpu/drm/gma500/cdv_intel_display.c @@ -1127,8 +1127,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, } /* dpll |= PLL_REF_INPUT_DREFCLK; */ - if (is_dp) { -/*FIXME cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); */ + if (is_dp || is_edp) { + cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); } else { REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);