From ada31510abbc031b696b69e225e598d30d6eb4b8 Mon Sep 17 00:00:00 2001
From: Olaf Rempel <razzor@kopf-tisch.de>
Date: Tue, 8 Jun 2010 22:32:38 +0200
Subject: [PATCH] --- yaml --- r: 201515 b: refs/heads/master c:
 21f0ba90a447090153edeaf2f14f9f7e8bd9bc80 h: refs/heads/master i:   201513:
 be2ad50c1bf075f47385e49ee650602dcdcc528a   201511:
 856e03ad0a05d96c6469f979be6a4274e77a4159 v: v3

---
 [refs]                           |  2 +-
 trunk/arch/arm/plat-orion/pcie.c | 34 ++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 7d3a20153501..81b66fdb5619 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6f2b186a0f1e70be411ca260d4577f1ed35d58e0
+refs/heads/master: 21f0ba90a447090153edeaf2f14f9f7e8bd9bc80
diff --git a/trunk/arch/arm/plat-orion/pcie.c b/trunk/arch/arm/plat-orion/pcie.c
index 54c84a492a0f..779553a1595e 100644
--- a/trunk/arch/arm/plat-orion/pcie.c
+++ b/trunk/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <linux/delay.h>
 
 /*
  * PCIe unit register offsets.
@@ -46,6 +47,8 @@
 #define  PCIE_STAT_BUS_OFFS		8
 #define  PCIE_STAT_BUS_MASK		0xff
 #define  PCIE_STAT_LINK_DOWN		1
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET		(1<<20)
 
 
 u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
 	writel(stat, base + PCIE_STAT_OFF);
 }
 
+void __init orion_pcie_reset(void __iomem *base)
+{
+	u32 reg;
+	int i;
+
+	/*
+	 * MV-S104860-U0, Rev. C:
+	 * PCI Express Unit Soft Reset
+	 * When set, generates an internal reset in the PCI Express unit.
+	 * This bit should be cleared after the link is re-established.
+	 */
+	reg = readl(base + PCIE_DEBUG_CTRL);
+	reg |= PCIE_DEBUG_SOFT_RESET;
+	writel(reg, base + PCIE_DEBUG_CTRL);
+
+	for (i = 0; i < 20; i++) {
+		mdelay(10);
+
+		if (orion_pcie_link_up(base))
+			break;
+	}
+
+	reg &= ~(PCIE_DEBUG_SOFT_RESET);
+	writel(reg, base + PCIE_DEBUG_CTRL);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -152,6 +181,11 @@ void __init orion_pcie_setup(void __iomem *base,
 	u16 cmd;
 	u32 mask;
 
+	/*
+	 * soft reset PCIe unit
+	 */
+	orion_pcie_reset(base);
+
 	/*
 	 * Point PCIe unit MBUS decode windows to DRAM space.
 	 */