From ae888ea4a982f1c4ae8f75d13945fdde8036924b Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat, 4 Dec 2010 17:22:41 +0000
Subject: [PATCH] --- yaml --- r: 228777 b: refs/heads/master c:
 f684f5b48cd27a031928c137531aace728d765a6 h: refs/heads/master i:   228775:
 f4acefe163bb6a361834735dedb6a9c638bedec0 v: v3

---
 [refs]                                     | 2 +-
 trunk/drivers/gpu/drm/i915/intel_display.c | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 32830e83b22a..95e053595ca9 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c1858123dba4a9e40355363ac7a153ea23a5315d
+refs/heads/master: f684f5b48cd27a031928c137531aace728d765a6
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index f2aa76bd72c0..3063edd2456f 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -5864,7 +5864,6 @@ void intel_init_clock_gating(struct drm_device *dev)
 				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
 				   _3D_CHICKEN2_WM_READ_PIPELINED);
 		}
-		return;
 	} else if (IS_G4X(dev)) {
 		uint32_t dspclk_gate;
 		I915_WRITE(RENCLK_GATE_D1, 0);