From aeeab6b9b4d226fc38cfaaeebb081f93dc56704f Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Thu, 3 Sep 2009 20:13:58 +0300 Subject: [PATCH] --- yaml --- r: 163151 b: refs/heads/master c: 11b66383aa722a3321d2aeec09808c5b140ad396 h: refs/heads/master i: 163149: 96d36be6a882c9121aaba86fcf17fa31257a1db4 163147: ff1fab5d72f18bb086260fe7b61e05f4f1e13b6c 163143: d4c6b856cc2f1b7330bf6117720d8fd3005d7b33 163135: b87cc041a1b4b26ab641c21da8057d59d1e9381a v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/clock34xx.c | 17 +++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 3533c474d825..25e864db09ee 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6dda2d4b1306c19e39496e9bb305424d1d547013 +refs/heads/master: 11b66383aa722a3321d2aeec09808c5b140ad396 diff --git a/trunk/arch/arm/mach-omap2/clock34xx.c b/trunk/arch/arm/mach-omap2/clock34xx.c index cd7819cc0c9e..fafcd32e6907 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx.c +++ b/trunk/arch/arm/mach-omap2/clock34xx.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void) return -EINVAL; /* REVISIT: not yet ready for 343x */ -#if 0 - if (clk_set_rate(&virt_prcm_set, mpurate)) - printk(KERN_ERR "Could not find matching MPU rate\n"); -#endif + if (clk_set_rate(&dpll1_ck, mpurate)) + printk(KERN_ERR "*** Unable to set MPU rate\n"); recalculate_root_clocks(); - printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): " + printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " "%ld.%01ld/%ld/%ld MHz\n", - (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; + (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), + (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; + + calibrate_delay(); return 0; } @@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void) recalculate_root_clocks(); - printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " + printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, (core_ck.rate / 1000000), (arm_fck.rate / 1000000));