From af07fc3d555185ba521cfb43e443f4e820f69ac9 Mon Sep 17 00:00:00 2001 From: Mike Travis Date: Thu, 15 Jan 2009 09:19:32 -0800 Subject: [PATCH] --- yaml --- r: 136472 b: refs/heads/master c: f2a082711905312dc7b6675e913fee0c4689f7ae h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/clock.c | 2 +- trunk/arch/arm/mach-imx/generic.c | 6 +- .../arch/arm/mach-imx/include/mach/imx-regs.h | 106 + trunk/arch/arm/mach-w90x900/mach-w90p910evb.c | 1 - trunk/arch/arm/mach-w90x900/time.c | 1 + trunk/arch/arm/mm/proc-syms.c | 1 - trunk/arch/ia64/kernel/irq_ia64.c | 12 +- trunk/arch/m68k/amiga/amiints.c | 12 +- trunk/arch/m68k/amiga/cia.c | 4 +- trunk/arch/m68k/amiga/config.c | 3 +- trunk/arch/m68k/apollo/config.c | 7 +- trunk/arch/m68k/atari/atakeyb.c | 10 +- trunk/arch/m68k/atari/stdma.c | 5 +- trunk/arch/m68k/atari/time.c | 5 +- trunk/arch/m68k/bvme6000/config.c | 1 + trunk/arch/m68k/hp300/time.c | 3 +- trunk/arch/m68k/kernel/.gitignore | 1 - trunk/arch/m68k/kernel/entry.S | 2 +- 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.../arch/mips/alchemy/common/au1xxx_irqmap.c | 205 ++ trunk/arch/mips/alchemy/common/clocks.c | 65 +- trunk/arch/mips/alchemy/common/cputable.c | 52 + trunk/arch/mips/alchemy/common/dbdma.c | 65 - trunk/arch/mips/alchemy/common/irq.c | 745 +++--- trunk/arch/mips/alchemy/common/power.c | 406 +++- trunk/arch/mips/alchemy/common/reset.c | 2 + trunk/arch/mips/alchemy/common/setup.c | 71 +- trunk/arch/mips/alchemy/common/sleeper.S | 118 +- trunk/arch/mips/alchemy/common/time.c | 311 ++- .../alchemy/{devboards => }/db1x00/Makefile | 2 +- .../{devboards => }/db1x00/board_setup.c | 37 - trunk/arch/mips/alchemy/db1x00/init.c | 62 + .../alchemy/{devboards => }/db1x00/irqmap.c | 24 +- trunk/arch/mips/alchemy/devboards/Makefile | 18 - trunk/arch/mips/alchemy/devboards/pm.c | 229 -- trunk/arch/mips/alchemy/mtx-1/board_setup.c | 12 - trunk/arch/mips/alchemy/mtx-1/init.c | 2 +- trunk/arch/mips/alchemy/mtx-1/irqmap.c | 18 +- .../alchemy/{devboards => }/pb1000/Makefile | 2 +- .../{devboards => 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trunk/arch/mips/alchemy/xxs1500/init.c | 2 +- trunk/arch/mips/alchemy/xxs1500/irqmap.c | 31 +- trunk/arch/mips/cavium-octeon/Kconfig | 85 - trunk/arch/mips/cavium-octeon/Makefile | 16 - trunk/arch/mips/cavium-octeon/csrc-octeon.c | 58 - trunk/arch/mips/cavium-octeon/dma-octeon.c | 32 - .../mips/cavium-octeon/executive/Makefile | 13 - .../cavium-octeon/executive/cvmx-bootmem.c | 586 ----- .../mips/cavium-octeon/executive/cvmx-l2c.c | 734 ------ .../cavium-octeon/executive/cvmx-sysinfo.c | 116 - .../cavium-octeon/executive/octeon-model.c | 358 --- trunk/arch/mips/cavium-octeon/flash_setup.c | 84 - trunk/arch/mips/cavium-octeon/octeon-irq.c | 497 ---- trunk/arch/mips/cavium-octeon/octeon-memcpy.S | 521 ----- trunk/arch/mips/cavium-octeon/serial.c | 136 -- trunk/arch/mips/cavium-octeon/setup.c | 929 -------- trunk/arch/mips/cavium-octeon/smp.c | 211 -- .../arch/mips/configs/cavium-octeon_defconfig | 943 -------- trunk/arch/mips/include/asm/cpu-features.h | 3 - trunk/arch/mips/include/asm/cpu.h | 14 - trunk/arch/mips/include/asm/hazards.h | 4 +- trunk/arch/mips/include/asm/io.h | 14 - .../mips/include/asm/mach-au1x00/au1000.h | 89 +- .../include/asm/mach-au1x00/au1xxx_dbdma.h | 5 - .../cpu-feature-overrides.h | 78 - .../asm/mach-cavium-octeon/dma-coherence.h | 64 - .../mips/include/asm/mach-cavium-octeon/irq.h | 244 -- .../mach-cavium-octeon/kernel-entry-init.h | 131 -- .../mips/include/asm/mach-cavium-octeon/war.h | 26 - .../include/asm/mach-generic/dma-coherence.h | 26 +- .../include/asm/mach-ip27/dma-coherence.h | 26 +- .../include/asm/mach-ip32/dma-coherence.h | 26 +- .../include/asm/mach-jazz/dma-coherence.h | 26 +- .../include/asm/mach-lemote/dma-coherence.h | 26 +- trunk/arch/mips/include/asm/mipsregs.h | 22 - trunk/arch/mips/include/asm/module.h | 2 - trunk/arch/mips/include/asm/octeon/cvmx-asm.h | 128 -- .../mips/include/asm/octeon/cvmx-bootinfo.h | 262 --- .../mips/include/asm/octeon/cvmx-bootmem.h | 288 --- .../mips/include/asm/octeon/cvmx-ciu-defs.h | 1616 ------------- .../mips/include/asm/octeon/cvmx-gpio-defs.h | 219 -- .../mips/include/asm/octeon/cvmx-iob-defs.h | 530 ----- .../mips/include/asm/octeon/cvmx-ipd-defs.h | 877 -------- .../mips/include/asm/octeon/cvmx-l2c-defs.h | 963 -------- trunk/arch/mips/include/asm/octeon/cvmx-l2c.h | 325 --- .../mips/include/asm/octeon/cvmx-l2d-defs.h | 369 --- .../mips/include/asm/octeon/cvmx-l2t-defs.h | 141 -- .../mips/include/asm/octeon/cvmx-led-defs.h | 240 -- .../mips/include/asm/octeon/cvmx-mio-defs.h | 2004 ----------------- .../mips/include/asm/octeon/cvmx-packet.h | 61 - .../mips/include/asm/octeon/cvmx-pow-defs.h | 698 ------ .../mips/include/asm/octeon/cvmx-spinlock.h | 232 -- .../mips/include/asm/octeon/cvmx-sysinfo.h | 152 -- trunk/arch/mips/include/asm/octeon/cvmx.h | 505 ----- .../mips/include/asm/octeon/octeon-feature.h | 119 - .../mips/include/asm/octeon/octeon-model.h | 321 --- trunk/arch/mips/include/asm/octeon/octeon.h | 248 -- trunk/arch/mips/include/asm/processor.h | 69 - trunk/arch/mips/include/asm/ptrace.h | 4 - trunk/arch/mips/include/asm/smp.h | 3 - trunk/arch/mips/include/asm/stackframe.h | 17 - trunk/arch/mips/include/asm/time.h | 24 +- trunk/arch/mips/kernel/Makefile | 5 +- trunk/arch/mips/kernel/asm-offsets.c | 31 - trunk/arch/mips/kernel/branch.c | 33 - trunk/arch/mips/kernel/cevt-r4k.c | 2 +- trunk/arch/mips/kernel/cpu-probe.c | 31 +- trunk/arch/mips/kernel/csrc-r4k.c | 2 +- trunk/arch/mips/kernel/genex.S | 4 - trunk/arch/mips/kernel/irq.c | 1 - trunk/arch/mips/kernel/octeon_switch.S | 506 ----- trunk/arch/mips/kernel/ptrace32.c | 64 +- trunk/arch/mips/kernel/smtc.c | 4 +- trunk/arch/mips/kernel/traps.c | 21 - trunk/arch/mips/lib/Makefile | 1 - trunk/arch/mips/mm/Makefile | 1 - trunk/arch/mips/mm/c-octeon.c | 307 --- trunk/arch/mips/mm/cache.c | 6 - trunk/arch/mips/mm/cex-oct.S | 70 - trunk/arch/mips/mm/dma-default.c | 25 +- trunk/arch/mips/mm/tlb-r4k.c | 5 +- trunk/arch/mips/mm/tlbex.c | 1 - trunk/arch/mips/sgi-ip22/ip22-int.c | 2 +- trunk/arch/mips/sgi-ip22/ip22-time.c | 2 +- trunk/arch/mips/sibyte/bcm1480/smp.c | 3 +- trunk/arch/mips/sibyte/sb1250/smp.c | 3 +- trunk/arch/mn10300/kernel/mn10300-watchdog.c | 3 +- trunk/arch/powerpc/boot/dts/gef_sbc610.dts | 15 - .../powerpc/configs/86xx/gef_sbc610_defconfig | 1 - .../arch/powerpc/platforms/cell/cbe_cpufreq.c | 2 +- .../platforms/cell/cpufreq_spudemand.c | 4 +- trunk/arch/powerpc/platforms/pasemi/cpufreq.c | 2 +- .../powerpc/platforms/powermac/cpufreq_64.c | 2 +- trunk/arch/sparc/configs/sparc32_defconfig | 290 +-- trunk/arch/sparc/include/asm/oplib_32.h | 11 + trunk/arch/sparc/include/asm/oplib_64.h | 10 + trunk/arch/sparc/include/asm/signal.h | 4 - trunk/arch/sparc/include/asm/topology_64.h | 4 - trunk/arch/sparc/kernel/auxio_32.c | 3 +- trunk/arch/sparc/kernel/auxio_64.c | 2 - trunk/arch/sparc/kernel/cpu.c | 2 - trunk/arch/sparc/kernel/idprom.c | 3 - trunk/arch/sparc/kernel/ioport.c | 15 - trunk/arch/sparc/kernel/irq_32.c | 1 - trunk/arch/sparc/kernel/pci.c | 1 - trunk/arch/sparc/kernel/pcic.c | 6 - trunk/arch/sparc/kernel/process_32.c | 2 - trunk/arch/sparc/kernel/process_64.c | 2 - trunk/arch/sparc/kernel/psycho_common.c | 60 +- trunk/arch/sparc/kernel/sbus.c | 1 - trunk/arch/sparc/kernel/setup_32.c | 3 - trunk/arch/sparc/kernel/setup_64.c | 3 - trunk/arch/sparc/kernel/sparc_ksyms_32.c | 225 +- trunk/arch/sparc/kernel/sparc_ksyms_64.c | 243 +- trunk/arch/sparc/kernel/sun4d_smp.c | 4 +- trunk/arch/sparc/kernel/sys_sparc_64.c | 2 - trunk/arch/sparc/kernel/time_32.c | 2 - trunk/arch/sparc/kernel/time_64.c | 4 +- trunk/arch/sparc/kernel/traps_32.c | 1 - trunk/arch/sparc/kernel/traps_64.c | 2 - trunk/arch/sparc/kernel/unaligned_64.c | 8 +- trunk/arch/sparc/lib/Makefile | 1 - trunk/arch/sparc/lib/PeeCeeI.c | 8 - trunk/arch/sparc/lib/ksyms.c | 196 -- trunk/arch/sparc/lib/user_fixup.c | 5 - trunk/arch/sparc/mm/generic_32.c | 1 - trunk/arch/sparc/mm/generic_64.c | 1 - trunk/arch/sparc/mm/highmem.c | 2 - trunk/arch/sparc/mm/init_32.c | 6 - trunk/arch/sparc/mm/init_64.c | 4 - trunk/arch/sparc/prom/init_32.c | 4 - trunk/arch/sparc/prom/misc_32.c | 3 - trunk/arch/sparc/prom/misc_64.c | 3 - trunk/arch/sparc/prom/ranges.c | 3 - trunk/arch/sparc/prom/tree_32.c | 17 +- trunk/arch/sparc/prom/tree_64.c | 18 +- .../include/asm/mach-default/mach_wakecpu.h | 6 - trunk/arch/x86/include/asm/mtrr.h | 10 +- trunk/arch/x86/include/asm/pgtable.h | 19 - trunk/arch/x86/include/asm/topology.h | 17 +- trunk/arch/x86/kernel/apic.c | 1 - .../x86/kernel/cpu/cpufreq/acpi-cpufreq.c | 38 +- trunk/arch/x86/kernel/entry_32.S | 2 + trunk/arch/x86/kernel/mpparse.c | 1 - trunk/arch/x86/kernel/tlb_64.c | 3 +- trunk/arch/x86/mm/fault.c | 2 +- trunk/arch/x86/mm/pageattr.c | 10 +- trunk/arch/x86/mm/pat.c | 90 +- trunk/arch/x86/pci/i386.c | 12 +- trunk/drivers/ata/libata-sff.c | 9 +- trunk/drivers/ata/pata_it821x.c | 17 +- trunk/drivers/block/amiflop.c | 40 +- trunk/drivers/char/amiserial.c | 36 +- trunk/drivers/char/pty.c | 4 +- trunk/drivers/char/ser_a2232.c | 12 +- trunk/drivers/char/vme_scc.c | 166 +- trunk/drivers/dio/dio-sysfs.c | 19 +- trunk/drivers/dio/dio.c | 18 +- trunk/drivers/infiniband/hw/ehca/ehca_main.c | 2 +- trunk/drivers/infiniband/hw/mlx4/main.c | 13 +- trunk/drivers/infiniband/hw/nes/nes_cm.c | 12 +- trunk/drivers/infiniband/hw/nes/nes_utils.c | 4 +- .../drivers/infiniband/ulp/ipoib/ipoib_main.c | 38 +- .../infiniband/ulp/ipoib/ipoib_multicast.c | 3 - trunk/drivers/infiniband/ulp/iser/Kconfig | 2 +- trunk/drivers/input/misc/Kconfig | 7 - trunk/drivers/input/misc/Makefile | 1 - trunk/drivers/input/misc/pcf50633-input.c | 132 -- trunk/drivers/isdn/hardware/mISDN/hfcmulti.c | 3 +- trunk/drivers/isdn/hardware/mISDN/hfcpci.c | 2 +- trunk/drivers/isdn/mISDN/dsp_cmx.c | 5 +- trunk/drivers/isdn/mISDN/dsp_pipeline.c | 4 +- trunk/drivers/mfd/Kconfig | 23 - trunk/drivers/mfd/Makefile | 4 - trunk/drivers/mfd/dm355evm_msp.c | 10 - trunk/drivers/mfd/pcf50633-adc.c | 277 --- trunk/drivers/mfd/pcf50633-core.c | 710 ------ trunk/drivers/mfd/pcf50633-gpio.c | 118 - trunk/drivers/mfd/sm501.c | 30 +- trunk/drivers/mfd/twl4030-core.c | 11 +- trunk/drivers/net/3c503.c | 1 - trunk/drivers/net/3c59x.c | 2 - trunk/drivers/net/8139cp.c | 2 - trunk/drivers/net/8139too.c | 2 +- trunk/drivers/net/8390.c | 1 - trunk/drivers/net/8390p.c | 1 - trunk/drivers/net/Kconfig | 2 +- trunk/drivers/net/acenic.c | 1 - trunk/drivers/net/arm/etherh.c | 1 - trunk/drivers/net/arm/ks8695net.c | 1 - trunk/drivers/net/b44.c | 13 +- trunk/drivers/net/cxgb3/adapter.h | 7 +- trunk/drivers/net/cxgb3/cxgb3_main.c | 22 +- trunk/drivers/net/cxgb3/sge.c | 2 +- trunk/drivers/net/e1000e/ich8lan.c | 19 +- trunk/drivers/net/e2100.c | 1 - trunk/drivers/net/enic/enic_main.c | 1 - trunk/drivers/net/forcedeth.c | 22 +- trunk/drivers/net/gianfar.c | 15 - trunk/drivers/net/hamachi.c | 1 - trunk/drivers/net/hamradio/6pack.c | 3 +- trunk/drivers/net/hp-plus.c | 1 - trunk/drivers/net/hydra.c | 1 - trunk/drivers/net/irda/au1k_ir.c | 2 +- trunk/drivers/net/irda/donauboe.c | 8 +- trunk/drivers/net/mac8390.c | 1 - trunk/drivers/net/mlx4/en_netdev.c | 1 - trunk/drivers/net/mlx4/main.c | 4 +- trunk/drivers/net/ne-h8300.c | 1 - trunk/drivers/net/ne2k-pci.c | 1 - trunk/drivers/net/ns83820.c | 1 - trunk/drivers/net/qlge/qlge.h | 61 +- trunk/drivers/net/qlge/qlge_dbg.c | 62 +- trunk/drivers/net/qlge/qlge_main.c | 80 +- trunk/drivers/net/r6040.c | 43 +- trunk/drivers/net/sc92031.c | 1 - trunk/drivers/net/sfc/tenxpress.c | 5 +- trunk/drivers/net/sis900.c | 1 - trunk/drivers/net/smc-mca.c | 1 - trunk/drivers/net/smc-ultra.c | 1 - trunk/drivers/net/smsc911x.c | 4 +- trunk/drivers/net/smsc9420.c | 1 - trunk/drivers/net/ucc_geth.c | 128 +- trunk/drivers/net/ucc_geth.h | 114 +- trunk/drivers/net/via-rhine.c | 1 - trunk/drivers/net/via-velocity.c | 1 - trunk/drivers/net/wd.c | 1 - trunk/drivers/net/wireless/libertas/main.c | 7 +- trunk/drivers/net/yellowfin.c | 1 - trunk/drivers/net/zorro8390.c | 1 - trunk/drivers/parisc/superio.c | 1 + trunk/drivers/pci/intel-iommu.c | 3 +- trunk/drivers/power/Kconfig | 6 - trunk/drivers/power/Makefile | 1 - trunk/drivers/power/pcf50633-charger.c | 358 --- trunk/drivers/regulator/Kconfig | 7 - trunk/drivers/regulator/Makefile | 1 - trunk/drivers/regulator/pcf50633-regulator.c | 329 --- trunk/drivers/rtc/Kconfig | 7 - trunk/drivers/rtc/Makefile | 1 - trunk/drivers/rtc/rtc-pcf50633.c | 344 --- trunk/drivers/s390/net/qeth_l2_main.c | 2 +- trunk/drivers/s390/net/qeth_l3_main.c | 24 +- trunk/drivers/serial/8250.c | 2 - trunk/drivers/serial/jsm/jsm_neo.c | 3 + trunk/drivers/usb/serial/ti_usb_3410_5052.c | 73 +- trunk/drivers/usb/serial/ti_usb_3410_5052.h | 8 - trunk/drivers/usb/serial/usb-serial.c | 3 + trunk/drivers/video/Makefile | 4 +- trunk/drivers/video/amifb.c | 6 +- trunk/drivers/video/atafb.c | 112 +- trunk/drivers/video/c2p.c | 232 ++ trunk/drivers/video/c2p.h | 11 +- trunk/drivers/video/c2p_core.h | 153 -- trunk/drivers/video/c2p_iplan2.c | 153 -- trunk/drivers/video/c2p_planar.c | 156 -- trunk/drivers/video/console/fbcon.c | 38 + trunk/drivers/watchdog/Kconfig | 14 - trunk/drivers/watchdog/Makefile | 2 - trunk/drivers/watchdog/gef_wdt.c | 330 --- trunk/drivers/watchdog/pika_wdt.c | 301 --- trunk/drivers/watchdog/wm8350_wdt.c | 6 +- trunk/drivers/zorro/.gitignore | 2 - trunk/drivers/zorro/zorro-sysfs.c | 20 +- trunk/drivers/zorro/zorro.c | 23 +- trunk/drivers/zorro/zorro.h | 2 +- trunk/firmware/Makefile | 3 +- trunk/firmware/WHENCE | 16 +- trunk/firmware/mts_cdma.fw.ihex | 867 ------- trunk/firmware/mts_edge.fw.ihex | 881 -------- trunk/firmware/mts_gsm.fw.ihex | 867 ------- trunk/fs/dlm/debug_fs.c | 696 +++--- trunk/fs/dlm/dlm_internal.h | 2 +- trunk/fs/dlm/lock.c | 26 +- trunk/fs/dlm/lockspace.c | 2 +- trunk/fs/dlm/recover.c | 10 +- trunk/fs/select.c | 2 +- trunk/include/asm-generic/pgtable.h | 4 +- trunk/include/asm-m68k/unistd.h | 4 +- trunk/include/linux/dio.h | 2 +- trunk/include/linux/dmaengine.h | 10 - trunk/include/linux/mISDNif.h | 5 +- trunk/include/linux/mfd/pcf50633/adc.h | 72 - trunk/include/linux/mfd/pcf50633/core.h | 218 -- trunk/include/linux/mfd/pcf50633/gpio.h | 52 - trunk/include/linux/mfd/pcf50633/mbc.h | 134 -- trunk/include/linux/mfd/pcf50633/pmic.h | 67 - trunk/include/linux/smp.h | 13 +- trunk/include/net/wimax.h | 4 +- trunk/include/sound/soc-dapm.h | 2 +- trunk/include/sound/soc.h | 15 +- trunk/kernel/Makefile | 6 +- trunk/kernel/async.c | 21 +- trunk/kernel/rcutorture.c | 113 +- trunk/kernel/sched.c | 13 +- trunk/kernel/sched_debug.c | 21 +- trunk/kernel/up.c | 21 - trunk/mm/memory.c | 24 +- trunk/net/bridge/netfilter/ebtables.c | 3 +- trunk/net/core/dev.c | 13 +- trunk/net/dccp/ccids/Kconfig | 2 +- trunk/net/dccp/ccids/lib/tfrc.c | 2 +- trunk/net/tipc/bcast.h | 2 +- trunk/net/xfrm/xfrm_ipcomp.c | 1 + trunk/scripts/markup_oops.pl | 59 +- trunk/sound/oss/dmasound/dmasound_atari.c | 5 +- trunk/sound/oss/dmasound/dmasound_q40.c | 16 +- trunk/sound/pci/hda/hda_beep.c | 1 + trunk/sound/pci/hda/hda_codec.c | 48 +- trunk/sound/pci/hda/hda_codec.h | 2 - trunk/sound/pci/hda/hda_intel.c | 6 +- trunk/sound/pci/hda/patch_analog.c | 5 +- trunk/sound/pci/hda/patch_nvhdmi.c | 2 - trunk/sound/pci/hda/patch_realtek.c | 18 +- trunk/sound/soc/codecs/twl4030.c | 12 +- trunk/sound/soc/soc-core.c | 37 +- trunk/sound/soc/soc-dapm.c | 80 +- trunk/sound/usb/caiaq/caiaq-device.c | 2 +- trunk/sound/usb/caiaq/caiaq-device.h | 1 - trunk/sound/usb/caiaq/caiaq-midi.c | 32 +- 406 files changed, 4480 insertions(+), 27998 deletions(-) delete mode 100644 trunk/arch/m68k/kernel/.gitignore create mode 100644 trunk/arch/mips/alchemy/common/au1xxx_irqmap.c create mode 100644 trunk/arch/mips/alchemy/common/cputable.c rename trunk/arch/mips/alchemy/{devboards => }/db1x00/Makefile (81%) rename trunk/arch/mips/alchemy/{devboards => }/db1x00/board_setup.c (80%) create mode 100644 trunk/arch/mips/alchemy/db1x00/init.c rename trunk/arch/mips/alchemy/{devboards => }/db1x00/irqmap.c (77%) delete mode 100644 trunk/arch/mips/alchemy/devboards/Makefile delete mode 100644 trunk/arch/mips/alchemy/devboards/pm.c rename trunk/arch/mips/alchemy/{devboards => }/pb1000/Makefile (81%) rename trunk/arch/mips/alchemy/{devboards => }/pb1000/board_setup.c (90%) create mode 100644 trunk/arch/mips/alchemy/pb1000/init.c create mode 100644 trunk/arch/mips/alchemy/pb1000/irqmap.c rename trunk/arch/mips/alchemy/{devboards => }/pb1100/Makefile (81%) rename trunk/arch/mips/alchemy/{devboards => }/pb1100/board_setup.c (76%) create mode 100644 trunk/arch/mips/alchemy/pb1100/init.c create mode 100644 trunk/arch/mips/alchemy/pb1100/irqmap.c rename trunk/arch/mips/alchemy/{devboards => }/pb1200/Makefile (61%) rename trunk/arch/mips/alchemy/{devboards => }/pb1200/board_setup.c (93%) rename trunk/arch/mips/alchemy/{devboards/prom.c => pb1200/init.c} (71%) rename trunk/arch/mips/alchemy/{devboards => }/pb1200/irqmap.c (64%) rename trunk/arch/mips/alchemy/{devboards => }/pb1200/platform.c (100%) rename trunk/arch/mips/alchemy/{devboards => }/pb1500/Makefile (81%) rename trunk/arch/mips/alchemy/{devboards => }/pb1500/board_setup.c (79%) create mode 100644 trunk/arch/mips/alchemy/pb1500/init.c create mode 100644 trunk/arch/mips/alchemy/pb1500/irqmap.c rename trunk/arch/mips/alchemy/{devboards => }/pb1550/Makefile (81%) rename trunk/arch/mips/alchemy/{devboards => }/pb1550/board_setup.c (72%) create mode 100644 trunk/arch/mips/alchemy/pb1550/init.c create mode 100644 trunk/arch/mips/alchemy/pb1550/irqmap.c delete mode 100644 trunk/arch/mips/cavium-octeon/Kconfig delete mode 100644 trunk/arch/mips/cavium-octeon/Makefile delete mode 100644 trunk/arch/mips/cavium-octeon/csrc-octeon.c delete mode 100644 trunk/arch/mips/cavium-octeon/dma-octeon.c delete mode 100644 trunk/arch/mips/cavium-octeon/executive/Makefile delete mode 100644 trunk/arch/mips/cavium-octeon/executive/cvmx-bootmem.c delete mode 100644 trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c delete mode 100644 trunk/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c delete mode 100644 trunk/arch/mips/cavium-octeon/executive/octeon-model.c delete mode 100644 trunk/arch/mips/cavium-octeon/flash_setup.c delete mode 100644 trunk/arch/mips/cavium-octeon/octeon-irq.c delete mode 100644 trunk/arch/mips/cavium-octeon/octeon-memcpy.S delete mode 100644 trunk/arch/mips/cavium-octeon/serial.c delete mode 100644 trunk/arch/mips/cavium-octeon/setup.c delete mode 100644 trunk/arch/mips/cavium-octeon/smp.c delete mode 100644 trunk/arch/mips/configs/cavium-octeon_defconfig delete mode 100644 trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h delete mode 100644 trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h delete mode 100644 trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h delete mode 100644 trunk/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h delete mode 100644 trunk/arch/mips/include/asm/mach-cavium-octeon/war.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-asm.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-bootinfo.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-bootmem.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-l2c.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-packet.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-spinlock.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-sysinfo.h delete mode 100644 trunk/arch/mips/include/asm/octeon/cvmx.h delete mode 100644 trunk/arch/mips/include/asm/octeon/octeon-feature.h delete mode 100644 trunk/arch/mips/include/asm/octeon/octeon-model.h delete mode 100644 trunk/arch/mips/include/asm/octeon/octeon.h delete mode 100644 trunk/arch/mips/kernel/octeon_switch.S delete mode 100644 trunk/arch/mips/mm/c-octeon.c delete mode 100644 trunk/arch/mips/mm/cex-oct.S delete mode 100644 trunk/arch/sparc/lib/ksyms.c delete mode 100644 trunk/drivers/input/misc/pcf50633-input.c delete mode 100644 trunk/drivers/mfd/pcf50633-adc.c delete mode 100644 trunk/drivers/mfd/pcf50633-core.c delete mode 100644 trunk/drivers/mfd/pcf50633-gpio.c delete mode 100644 trunk/drivers/power/pcf50633-charger.c delete mode 100644 trunk/drivers/regulator/pcf50633-regulator.c delete mode 100644 trunk/drivers/rtc/rtc-pcf50633.c create mode 100644 trunk/drivers/video/c2p.c delete mode 100644 trunk/drivers/video/c2p_core.h delete mode 100644 trunk/drivers/video/c2p_iplan2.c delete mode 100644 trunk/drivers/video/c2p_planar.c delete mode 100644 trunk/drivers/watchdog/gef_wdt.c delete mode 100644 trunk/drivers/watchdog/pika_wdt.c delete mode 100644 trunk/drivers/zorro/.gitignore delete mode 100644 trunk/firmware/mts_cdma.fw.ihex delete mode 100644 trunk/firmware/mts_edge.fw.ihex delete mode 100644 trunk/firmware/mts_gsm.fw.ihex delete mode 100644 trunk/include/linux/mfd/pcf50633/adc.h delete mode 100644 trunk/include/linux/mfd/pcf50633/core.h delete mode 100644 trunk/include/linux/mfd/pcf50633/gpio.h delete mode 100644 trunk/include/linux/mfd/pcf50633/mbc.h delete mode 100644 trunk/include/linux/mfd/pcf50633/pmic.h delete mode 100644 trunk/kernel/up.c diff --git a/[refs] b/[refs] index 218ac2fa5907..e1a1e539d280 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5cd7376200be7b8bab085557ff5876b04bd84191 +refs/heads/master: f2a082711905312dc7b6675e913fee0c4689f7ae diff --git a/trunk/arch/arm/mach-imx/clock.c b/trunk/arch/arm/mach-imx/clock.c index cf332aeb942e..7ec60fc91565 100644 --- a/trunk/arch/arm/mach-imx/clock.c +++ b/trunk/arch/arm/mach-imx/clock.c @@ -23,7 +23,7 @@ #include #include -#include +#include /* * Very simple approach: We can't disable clocks, so we do diff --git a/trunk/arch/arm/mach-imx/generic.c b/trunk/arch/arm/mach-imx/generic.c index 887cb21f75b0..fa72174dd95c 100644 --- a/trunk/arch/arm/mach-imx/generic.c +++ b/trunk/arch/arm/mach-imx/generic.c @@ -245,11 +245,11 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info) imx_mmc_device.dev.platform_data = info; } -static struct imx_fb_platform_data imx_fb_info; +static struct imxfb_mach_info imx_fb_info; -void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info) +void __init set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info) { - memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data)); + memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imxfb_mach_info)); } static struct resource imxfb_resources[] = { diff --git a/trunk/arch/arm/mach-imx/include/mach/imx-regs.h b/trunk/arch/arm/mach-imx/include/mach/imx-regs.h index 490297fc0e38..fb9de2733879 100644 --- a/trunk/arch/arm/mach-imx/include/mach/imx-regs.h +++ b/trunk/arch/arm/mach-imx/include/mach/imx-regs.h @@ -373,4 +373,110 @@ #define TSTAT_CAPT (1<<1) #define TSTAT_COMP (1<<0) +/* + * LCD Controller + */ + +#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) + +#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) +#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) +#define SIZE_YMAX(y) ( (y) & 0x1ff ) + +#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) +#define VPW_VPW(x) ( (x) & 0x3ff ) + +#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) +#define CPOS_CC1 (1<<31) +#define CPOS_CC0 (1<<30) +#define CPOS_OP (1<<28) +#define CPOS_CXP(x) (((x) & 3ff) << 16) +#define CPOS_CYP(y) ((y) & 0x1ff) + +#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) +#define LCWHB_BK_EN (1<<31) +#define LCWHB_CW(w) (((w) & 0x1f) << 24) +#define LCWHB_CH(h) (((h) & 0x1f) << 16) +#define LCWHB_BD(x) ((x) & 0xff) + +#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) +#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) +#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) +#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) + +#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) +#define PCR_TFT (1<<31) +#define PCR_COLOR (1<<30) +#define PCR_PBSIZ_1 (0<<28) +#define PCR_PBSIZ_2 (1<<28) +#define PCR_PBSIZ_4 (2<<28) +#define PCR_PBSIZ_8 (3<<28) +#define PCR_BPIX_1 (0<<25) +#define PCR_BPIX_2 (1<<25) +#define PCR_BPIX_4 (2<<25) +#define PCR_BPIX_8 (3<<25) +#define PCR_BPIX_12 (4<<25) +#define PCR_BPIX_16 (4<<25) +#define PCR_PIXPOL (1<<24) +#define PCR_FLMPOL (1<<23) +#define PCR_LPPOL (1<<22) +#define PCR_CLKPOL (1<<21) +#define PCR_OEPOL (1<<20) +#define PCR_SCLKIDLE (1<<19) +#define PCR_END_SEL (1<<18) +#define PCR_END_BYTE_SWAP (1<<17) +#define PCR_REV_VS (1<<16) +#define PCR_ACD_SEL (1<<15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1<<7) +#define PCR_SHARP (1<<6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) +#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) +#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) +#define HCR_H_WAIT_2(x) ((x) & 0xff) + +#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) +#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) +#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) +#define VCR_V_WAIT_2(x) ((x) & 0xff) + +#define LCDC_POS __REG(IMX_LCDC_BASE+0x24) +#define POS_POS(x) ((x) & 1f) + +#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) + +#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1<<15) +#define PWMR_SCR1 (1<<10) +#define PWMR_SCR0 (1<<9) +#define PWMR_CC_EN (1<<8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) +#define DMACR_BURST (1<<31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) &0xf) + +#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) +#define RMCR_LCDC_EN (1<<1) +#define RMCR_SELF_REF (1<<0) + +#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) +#define LCDICR_INT_SYN (1<<2) +#define LCDICR_INT_CON (1) + +#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) +#define LCDISR_UDR_ERR (1<<3) +#define LCDISR_ERR_RES (1<<2) +#define LCDISR_EOF (1<<1) +#define LCDISR_BOF (1<<0) + #endif // _IMX_REGS_H diff --git a/trunk/arch/arm/mach-w90x900/mach-w90p910evb.c b/trunk/arch/arm/mach-w90x900/mach-w90p910evb.c index 9ebc93f48530..9307a2475438 100644 --- a/trunk/arch/arm/mach-w90x900/mach-w90p910evb.c +++ b/trunk/arch/arm/mach-w90x900/mach-w90p910evb.c @@ -29,7 +29,6 @@ #include #include -#include #include "cpu.h" diff --git a/trunk/arch/arm/mach-w90x900/time.c b/trunk/arch/arm/mach-w90x900/time.c index bcc838f6b393..3a69e381f316 100644 --- a/trunk/arch/arm/mach-w90x900/time.c +++ b/trunk/arch/arm/mach-w90x900/time.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mm/proc-syms.c b/trunk/arch/arm/mm/proc-syms.c index 195e48edd8c2..4ad3bf291ad3 100644 --- a/trunk/arch/arm/mm/proc-syms.c +++ b/trunk/arch/arm/mm/proc-syms.c @@ -27,7 +27,6 @@ EXPORT_SYMBOL(__cpuc_flush_kern_all); EXPORT_SYMBOL(__cpuc_flush_user_all); EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); -EXPORT_SYMBOL(dmac_inv_range); /* because of flush_ioremap_region() */ #else EXPORT_SYMBOL(cpu_cache); #endif diff --git a/trunk/arch/ia64/kernel/irq_ia64.c b/trunk/arch/ia64/kernel/irq_ia64.c index 927ad027820c..28d3d483db92 100644 --- a/trunk/arch/ia64/kernel/irq_ia64.c +++ b/trunk/arch/ia64/kernel/irq_ia64.c @@ -493,13 +493,11 @@ ia64_handle_irq (ia64_vector vector, struct pt_regs *regs) saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); ia64_srlz_d(); while (vector != IA64_SPURIOUS_INT_VECTOR) { - struct irq_desc *desc = irq_to_desc(vector); - if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { smp_local_flush_tlb(); - kstat_incr_irqs_this_cpu(vector, desc); + kstat_this_cpu.irqs[vector]++; } else if (unlikely(IS_RESCHEDULE(vector))) - kstat_incr_irqs_this_cpu(vector, desc); + kstat_this_cpu.irqs[vector]++; else { int irq = local_vector_to_irq(vector); @@ -553,13 +551,11 @@ void ia64_process_pending_intr(void) * Perform normal interrupt style processing */ while (vector != IA64_SPURIOUS_INT_VECTOR) { - struct irq_desc *desc = irq_to_desc(vector); - if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { smp_local_flush_tlb(); - kstat_incr_irqs_this_cpu(vector, desc); + kstat_this_cpu.irqs[vector]++; } else if (unlikely(IS_RESCHEDULE(vector))) - kstat_incr_irqs_this_cpu(vector, desc); + kstat_this_cpu.irqs[vector]++; else { struct pt_regs *old_regs = set_irq_regs(NULL); int irq = local_vector_to_irq(vector); diff --git a/trunk/arch/m68k/amiga/amiints.c b/trunk/arch/m68k/amiga/amiints.c index c5b5212cc3f9..907a5533c845 100644 --- a/trunk/arch/m68k/amiga/amiints.c +++ b/trunk/arch/m68k/amiga/amiints.c @@ -72,14 +72,10 @@ static struct irq_controller amiga_irq_controller = { void __init amiga_init_IRQ(void) { - if (request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL)) - pr_err("Couldn't register int%d\n", 1); - if (request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL)) - pr_err("Couldn't register int%d\n", 3); - if (request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL)) - pr_err("Couldn't register int%d\n", 4); - if (request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL)) - pr_err("Couldn't register int%d\n", 5); + request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL); + request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL); + request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL); + request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL); m68k_setup_irq_controller(&amiga_irq_controller, IRQ_USER, AMI_STD_IRQS); diff --git a/trunk/arch/m68k/amiga/cia.c b/trunk/arch/m68k/amiga/cia.c index ecd0f7ca6f0e..343fab49bd9a 100644 --- a/trunk/arch/m68k/amiga/cia.c +++ b/trunk/arch/m68k/amiga/cia.c @@ -176,7 +176,5 @@ void __init cia_init_IRQ(struct ciabase *base) /* override auto int and install CIA handler */ m68k_setup_irq_controller(&auto_irq_controller, base->handler_irq, 1); m68k_irq_startup(base->handler_irq); - if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED, - base->name, base)) - pr_err("Couldn't register %s interrupt\n", base->name); + request_irq(base->handler_irq, cia_handler, IRQF_SHARED, base->name, base); } diff --git a/trunk/arch/m68k/amiga/config.c b/trunk/arch/m68k/amiga/config.c index 6e562751ad51..ab9862c3a136 100644 --- a/trunk/arch/m68k/amiga/config.c +++ b/trunk/arch/m68k/amiga/config.c @@ -493,8 +493,7 @@ static void __init amiga_sched_init(irq_handler_t timer_routine) * Please don't change this to use ciaa, as it interferes with the * SCSI code. We'll have to take a look at this later */ - if (request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL)) - pr_err("Couldn't register timer interrupt\n"); + request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL); /* start timer */ ciab.cra |= 0x11; } diff --git a/trunk/arch/m68k/apollo/config.c b/trunk/arch/m68k/apollo/config.c index 8d3eafab1ffe..78df98f2029a 100644 --- a/trunk/arch/m68k/apollo/config.c +++ b/trunk/arch/m68k/apollo/config.c @@ -31,6 +31,10 @@ extern unsigned long dn_gettimeoffset(void); extern int dn_dummy_hwclk(int, struct rtc_time *); extern int dn_dummy_set_clock_mmss(unsigned long); extern void dn_dummy_reset(void); +extern void dn_dummy_waitbut(void); +extern struct fb_info *dn_fb_init(long *); +extern void dn_dummy_debug_init(void); +extern irqreturn_t dn_process_int(int irq, struct pt_regs *fp); #ifdef CONFIG_HEARTBEAT static void dn_heartbeat(int on); #endif @@ -200,8 +204,7 @@ void dn_sched_init(irq_handler_t timer_routine) printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3)); #endif - if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine)) - pr_err("Couldn't register timer interrupt\n"); + request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine); } unsigned long dn_gettimeoffset(void) { diff --git a/trunk/arch/m68k/atari/atakeyb.c b/trunk/arch/m68k/atari/atakeyb.c index a5f33c059979..c038b7c7eff0 100644 --- a/trunk/arch/m68k/atari/atakeyb.c +++ b/trunk/arch/m68k/atari/atakeyb.c @@ -33,6 +33,7 @@ #include #include +extern unsigned int keymap_count; /* Hook for MIDI serial driver */ void (*atari_MIDI_interrupt_hook) (void); @@ -566,19 +567,14 @@ static int atari_keyb_done = 0; int atari_keyb_init(void) { - int error; - if (atari_keyb_done) return 0; kb_state.state = KEYBOARD; kb_state.len = 0; - error = request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, - IRQ_TYPE_SLOW, "keyboard/mouse/MIDI", - atari_keyboard_interrupt); - if (error) - return error; + request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, IRQ_TYPE_SLOW, + "keyboard/mouse/MIDI", atari_keyboard_interrupt); atari_turnoff_irq(IRQ_MFP_ACIA); do { diff --git a/trunk/arch/m68k/atari/stdma.c b/trunk/arch/m68k/atari/stdma.c index 604329fafbb8..d1bd029a34ac 100644 --- a/trunk/arch/m68k/atari/stdma.c +++ b/trunk/arch/m68k/atari/stdma.c @@ -179,9 +179,8 @@ EXPORT_SYMBOL(stdma_islocked); void __init stdma_init(void) { stdma_isr = NULL; - if (request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED, - "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int)) - pr_err("Couldn't register ST-DMA interrupt\n"); + request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED, + "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int); } diff --git a/trunk/arch/m68k/atari/time.c b/trunk/arch/m68k/atari/time.c index d076ff8d1b39..1edde27fa32d 100644 --- a/trunk/arch/m68k/atari/time.c +++ b/trunk/arch/m68k/atari/time.c @@ -31,9 +31,8 @@ atari_sched_init(irq_handler_t timer_routine) /* start timer C, div = 1:100 */ mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60; /* install interrupt service routine for MFP Timer C */ - if (request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, - "timer", timer_routine)) - pr_err("Couldn't register timer interrupt\n"); + request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, + "timer", timer_routine); } /* ++andreas: gettimeoffset fixed to check for pending interrupt */ diff --git a/trunk/arch/m68k/bvme6000/config.c b/trunk/arch/m68k/bvme6000/config.c index 9fe6fefb5e14..c072595928c0 100644 --- a/trunk/arch/m68k/bvme6000/config.c +++ b/trunk/arch/m68k/bvme6000/config.c @@ -43,6 +43,7 @@ extern unsigned long bvme6000_gettimeoffset (void); extern int bvme6000_hwclk (int, struct rtc_time *); extern int bvme6000_set_clock_mmss (unsigned long); extern void bvme6000_reset (void); +extern void bvme6000_waitbut(void); void bvme6000_set_vectors (void); /* Save tick handler routine pointer, will point to do_timer() in diff --git a/trunk/arch/m68k/hp300/time.c b/trunk/arch/m68k/hp300/time.c index f6312c7d8727..dd7c8a2583d3 100644 --- a/trunk/arch/m68k/hp300/time.c +++ b/trunk/arch/m68k/hp300/time.c @@ -70,8 +70,7 @@ void __init hp300_sched_init(irq_handler_t vector) asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE)); - if (request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector)) - pr_err("Couldn't register timer interrupt\n"); + request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector); out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ diff --git a/trunk/arch/m68k/kernel/.gitignore b/trunk/arch/m68k/kernel/.gitignore deleted file mode 100644 index c5f676c3c224..000000000000 --- a/trunk/arch/m68k/kernel/.gitignore +++ /dev/null @@ -1 +0,0 @@ -vmlinux.lds diff --git a/trunk/arch/m68k/kernel/entry.S b/trunk/arch/m68k/kernel/entry.S index 5b780826647c..f28404d9a2bc 100644 --- a/trunk/arch/m68k/kernel/entry.S +++ b/trunk/arch/m68k/kernel/entry.S @@ -424,7 +424,7 @@ resume: .data ALIGN sys_call_table: - .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ + .long sys_ni_syscall /* 0 - old "setup()" system call*/ .long sys_exit .long sys_fork .long sys_read diff --git a/trunk/arch/m68k/kernel/setup.c b/trunk/arch/m68k/kernel/setup.c index 303730afb1c9..4d97bd2bd573 100644 --- a/trunk/arch/m68k/kernel/setup.c +++ b/trunk/arch/m68k/kernel/setup.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include @@ -63,6 +62,7 @@ EXPORT_SYMBOL(vme_brdtype); int m68k_is040or060; EXPORT_SYMBOL(m68k_is040or060); +extern int end; extern unsigned long availmem; int m68k_num_memory; @@ -215,10 +215,11 @@ static void __init m68k_parse_bootinfo(const struct bi_record *record) void __init setup_arch(char **cmdline_p) { + extern int _etext, _edata, _end; int i; /* The bootinfo is located right after the kernel bss */ - m68k_parse_bootinfo((const struct bi_record *)_end); + m68k_parse_bootinfo((const struct bi_record *)&_end); if (CPU_IS_040) m68k_is040or060 = 4; @@ -251,9 +252,9 @@ void __init setup_arch(char **cmdline_p) } init_mm.start_code = PAGE_OFFSET; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)_end; + init_mm.end_code = (unsigned long) &_etext; + init_mm.end_data = (unsigned long) &_edata; + init_mm.brk = (unsigned long) &_end; *cmdline_p = m68k_command_line; memcpy(boot_command_line, *cmdline_p, CL_SIZE); diff --git a/trunk/arch/m68k/kernel/signal.c b/trunk/arch/m68k/kernel/signal.c index de2d05ddd86d..f9af893cd289 100644 --- a/trunk/arch/m68k/kernel/signal.c +++ b/trunk/arch/m68k/kernel/signal.c @@ -326,9 +326,6 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u struct sigcontext context; int err; - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - /* get previous context */ if (copy_from_user(&context, usc, sizeof(context))) goto badframe; @@ -414,9 +411,6 @@ rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, unsigned long usp; int err; - /* Always make any pending restarted system calls return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - err = __get_user(temp, &uc->uc_mcontext.version); if (temp != MCONTEXT_VERSION) goto badframe; @@ -943,15 +937,6 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) regs->d0 = -EINTR; break; - case -ERESTART_RESTARTBLOCK: - if (!has_handler) { - regs->d0 = __NR_restart_syscall; - regs->pc -= 2; - break; - } - regs->d0 = -EINTR; - break; - case -ERESTARTSYS: if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { regs->d0 = -EINTR; diff --git a/trunk/arch/m68k/kernel/vmlinux-sun3.lds b/trunk/arch/m68k/kernel/vmlinux-sun3.lds index d9368c0709ba..8a4919e4d36a 100644 --- a/trunk/arch/m68k/kernel/vmlinux-sun3.lds +++ b/trunk/arch/m68k/kernel/vmlinux-sun3.lds @@ -33,7 +33,6 @@ SECTIONS } :data /* End of data goes *here* so that freeing init code works properly. */ _edata = .; - NOTES /* will be freed after init */ . = ALIGN(PAGE_SIZE); /* Init code and data */ diff --git a/trunk/arch/m68k/mac/baboon.c b/trunk/arch/m68k/mac/baboon.c index 2a96bebd8969..245d16d078ad 100644 --- a/trunk/arch/m68k/mac/baboon.c +++ b/trunk/arch/m68k/mac/baboon.c @@ -92,8 +92,7 @@ static irqreturn_t baboon_irq(int irq, void *dev_id) void __init baboon_register_interrupts(void) { baboon_disabled = 0; - if (request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon)) - pr_err("Couldn't register baboon interrupt\n"); + request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon); } /* diff --git a/trunk/arch/m68k/mac/config.c b/trunk/arch/m68k/mac/config.c index 98b6bcfb37bf..8819b97be324 100644 --- a/trunk/arch/m68k/mac/config.c +++ b/trunk/arch/m68k/mac/config.c @@ -47,6 +47,13 @@ struct mac_booter_data mac_bi_data; +/* New m68k bootinfo stuff and videobase */ + +extern int m68k_num_memory; +extern struct mem_info m68k_memory[NUM_MEMINFO]; + +extern struct mem_info m68k_ramdisk; + /* The phys. video addr. - might be bogus on some machines */ static unsigned long mac_orig_videoaddr; @@ -54,6 +61,7 @@ static unsigned long mac_orig_videoaddr; extern unsigned long mac_gettimeoffset(void); extern int mac_hwclk(int, struct rtc_time *); extern int mac_set_clock_mmss(unsigned long); +extern int show_mac_interrupts(struct seq_file *, void *); extern void iop_preinit(void); extern void iop_init(void); extern void via_init(void); @@ -797,6 +805,10 @@ static void __init mac_identify(void) mac_bi_data.boottime, mac_bi_data.gmtbias); printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n", mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize); +#if 0 + printk("Ramdisk: addr 0x%lx size 0x%lx\n", + m68k_ramdisk.addr, m68k_ramdisk.size); +#endif iop_init(); via_init(); diff --git a/trunk/arch/m68k/mac/debug.c b/trunk/arch/m68k/mac/debug.c index bce074ceb768..65dd77a742a3 100644 --- a/trunk/arch/m68k/mac/debug.c +++ b/trunk/arch/m68k/mac/debug.c @@ -27,6 +27,7 @@ #include extern unsigned long mac_videobase; +extern unsigned long mac_videodepth; extern unsigned long mac_rowbytes; extern void mac_serial_print(const char *); diff --git a/trunk/arch/m68k/mac/iop.c b/trunk/arch/m68k/mac/iop.c index 1ad4e9d80eba..326fb9978094 100644 --- a/trunk/arch/m68k/mac/iop.c +++ b/trunk/arch/m68k/mac/iop.c @@ -305,16 +305,14 @@ void __init iop_register_interrupts(void) { if (iop_ism_present) { if (oss_present) { - if (request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, + request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, IRQ_FLG_LOCK, "ISM IOP", - (void *) IOP_NUM_ISM)) - pr_err("Couldn't register ISM IOP interrupt\n"); + (void *) IOP_NUM_ISM); oss_irq_enable(IRQ_MAC_ADB); } else { - if (request_irq(IRQ_VIA2_0, iop_ism_irq, + request_irq(IRQ_VIA2_0, iop_ism_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", - (void *) IOP_NUM_ISM)) - pr_err("Couldn't register ISM IOP interrupt\n"); + (void *) IOP_NUM_ISM); } if (!iop_alive(iop_base[IOP_NUM_ISM])) { printk("IOP: oh my god, they killed the ISM IOP!\n"); diff --git a/trunk/arch/m68k/mac/macints.c b/trunk/arch/m68k/mac/macints.c index 23711074e0e2..82e560c076ce 100644 --- a/trunk/arch/m68k/mac/macints.c +++ b/trunk/arch/m68k/mac/macints.c @@ -134,7 +134,6 @@ #include #include #include -#include #define DEBUG_SPURIOUS #define SHUTUP_SONIC @@ -147,6 +146,7 @@ static int scc_mask; * VIA/RBV hooks */ +extern void via_init(void); extern void via_register_interrupts(void); extern void via_irq_enable(int); extern void via_irq_disable(int); @@ -157,6 +157,9 @@ extern int via_irq_pending(int); * OSS hooks */ +extern int oss_present; + +extern void oss_init(void); extern void oss_register_interrupts(void); extern void oss_irq_enable(int); extern void oss_irq_disable(int); @@ -167,6 +170,9 @@ extern int oss_irq_pending(int); * PSC hooks */ +extern int psc_present; + +extern void psc_init(void); extern void psc_register_interrupts(void); extern void psc_irq_enable(int); extern void psc_irq_disable(int); @@ -185,10 +191,12 @@ extern void iop_register_interrupts(void); extern int baboon_present; +extern void baboon_init(void); extern void baboon_register_interrupts(void); extern void baboon_irq_enable(int); extern void baboon_irq_disable(int); extern void baboon_irq_clear(int); +extern int baboon_irq_pending(int); /* * SCC interrupt routines @@ -250,9 +258,8 @@ void __init mac_init_IRQ(void) if (baboon_present) baboon_register_interrupts(); iop_register_interrupts(); - if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", - mac_nmi_handler)) - pr_err("Couldn't register NMI\n"); + request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", + mac_nmi_handler); #ifdef DEBUG_MACINTS printk("mac_init_IRQ(): Done!\n"); #endif diff --git a/trunk/arch/m68k/mac/misc.c b/trunk/arch/m68k/mac/misc.c index 5d818568b343..a44c7086ab39 100644 --- a/trunk/arch/m68k/mac/misc.c +++ b/trunk/arch/m68k/mac/misc.c @@ -35,6 +35,7 @@ #define RTC_OFFSET 2082844800 +extern struct mac_booter_data mac_bi_data; static void (*rom_reset)(void); #ifdef CONFIG_ADB_CUDA diff --git a/trunk/arch/m68k/mac/oss.c b/trunk/arch/m68k/mac/oss.c index f3d23d6ebcf8..8426501119ca 100644 --- a/trunk/arch/m68k/mac/oss.c +++ b/trunk/arch/m68k/mac/oss.c @@ -66,21 +66,16 @@ void __init oss_init(void) void __init oss_register_interrupts(void) { - if (request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK, - "scsi", (void *) oss)) - pr_err("Couldn't register %s interrupt\n", "scsi"); - if (request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK, - "scc", mac_scc_dispatch)) - pr_err("Couldn't register %s interrupt\n", "scc"); - if (request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK, - "nubus", (void *) oss)) - pr_err("Couldn't register %s interrupt\n", "nubus"); - if (request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK, - "sound", (void *) oss)) - pr_err("Couldn't register %s interrupt\n", "sound"); - if (request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK, - "via1", (void *) via1)) - pr_err("Couldn't register %s interrupt\n", "via1"); + request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK, + "scsi", (void *) oss); + request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK, + "scc", mac_scc_dispatch); + request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK, + "nubus", (void *) oss); + request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK, + "sound", (void *) oss); + request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK, + "via1", (void *) via1); } /* diff --git a/trunk/arch/m68k/mac/psc.c b/trunk/arch/m68k/mac/psc.c index ba6ccab64018..f84a4dd64f94 100644 --- a/trunk/arch/m68k/mac/psc.c +++ b/trunk/arch/m68k/mac/psc.c @@ -117,14 +117,10 @@ void __init psc_init(void) void __init psc_register_interrupts(void) { - if (request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30)) - pr_err("Couldn't register psc%d interrupt\n", 3); - if (request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40)) - pr_err("Couldn't register psc%d interrupt\n", 4); - if (request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50)) - pr_err("Couldn't register psc%d interrupt\n", 5); - if (request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60)) - pr_err("Couldn't register psc%d interrupt\n", 6); + request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30); + request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40); + request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50); + request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60); } /* diff --git a/trunk/arch/m68k/mac/via.c b/trunk/arch/m68k/mac/via.c index 7d97ba54536e..f01d418e64fe 100644 --- a/trunk/arch/m68k/mac/via.c +++ b/trunk/arch/m68k/mac/via.c @@ -34,7 +34,6 @@ #include #include #include -#include volatile __u8 *via1, *via2; int rbv_present; @@ -85,6 +84,7 @@ void via_irq_disable(int irq); void via_irq_clear(int irq); extern irqreturn_t mac_scc_dispatch(int, void *); +extern int oss_present; /* * Initialize the VIAs @@ -283,8 +283,7 @@ void __init via_init_clock(irq_handler_t func) via1[vT1CL] = MAC_CLOCK_LOW; via1[vT1CH] = MAC_CLOCK_HIGH; - if (request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func)) - pr_err("Couldn't register %s interrupt\n", "timer"); + request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func); } /* @@ -294,31 +293,25 @@ void __init via_init_clock(irq_handler_t func) void __init via_register_interrupts(void) { if (via_alt_mapping) { - if (request_irq(IRQ_AUTO_1, via1_irq, + request_irq(IRQ_AUTO_1, via1_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, "software", - (void *) via1)) - pr_err("Couldn't register %s interrupt\n", "software"); - if (request_irq(IRQ_AUTO_6, via1_irq, + (void *) via1); + request_irq(IRQ_AUTO_6, via1_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", - (void *) via1)) - pr_err("Couldn't register %s interrupt\n", "via1"); + (void *) via1); } else { - if (request_irq(IRQ_AUTO_1, via1_irq, + request_irq(IRQ_AUTO_1, via1_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", - (void *) via1)) - pr_err("Couldn't register %s interrupt\n", "via1"); + (void *) via1); } - if (request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, - "via2", (void *) via2)) - pr_err("Couldn't register %s interrupt\n", "via2"); + request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, + "via2", (void *) via2); if (!psc_present) { - if (request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK, - "scc", mac_scc_dispatch)) - pr_err("Couldn't register %s interrupt\n", "scc"); + request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK, + "scc", mac_scc_dispatch); } - if (request_irq(IRQ_MAC_NUBUS, via_nubus_irq, - IRQ_FLG_LOCK|IRQ_FLG_FAST, "nubus", (void *) via2)) - pr_err("Couldn't register %s interrupt\n", "nubus"); + request_irq(IRQ_MAC_NUBUS, via_nubus_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, + "nubus", (void *) via2); } /* diff --git a/trunk/arch/m68k/math-emu/fp_log.c b/trunk/arch/m68k/math-emu/fp_log.c index 367ecee2f981..b1033ae0d6f0 100644 --- a/trunk/arch/m68k/math-emu/fp_log.c +++ b/trunk/arch/m68k/math-emu/fp_log.c @@ -24,6 +24,7 @@ static const struct fp_ext fp_one = extern struct fp_ext *fp_fadd(struct fp_ext *dest, const struct fp_ext *src); extern struct fp_ext *fp_fdiv(struct fp_ext *dest, const struct fp_ext *src); +extern struct fp_ext *fp_fmul(struct fp_ext *dest, const struct fp_ext *src); struct fp_ext * fp_fsqrt(struct fp_ext *dest, struct fp_ext *src) diff --git a/trunk/arch/m68k/mm/init.c b/trunk/arch/m68k/mm/init.c index 0007b2adf3a3..81bb08ceec18 100644 --- a/trunk/arch/m68k/mm/init.c +++ b/trunk/arch/m68k/mm/init.c @@ -28,7 +28,6 @@ #ifdef CONFIG_ATARI #include #endif -#include #include DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); @@ -74,6 +73,9 @@ extern void init_pointer_table(unsigned long ptable); /* References to section boundaries */ +extern char _text[], _etext[]; +extern char __init_begin[], __init_end[]; + extern pmd_t *zero_pgtable; void __init mem_init(void) diff --git a/trunk/arch/m68k/mm/motorola.c b/trunk/arch/m68k/mm/motorola.c index 4665fc84b7dc..c5dbb9bdb322 100644 --- a/trunk/arch/m68k/mm/motorola.c +++ b/trunk/arch/m68k/mm/motorola.c @@ -30,7 +30,6 @@ #ifdef CONFIG_ATARI #include #endif -#include #undef DEBUG @@ -302,12 +301,14 @@ void __init paging_init(void) } } +extern char __init_begin, __init_end; + void free_initmem(void) { unsigned long addr; - addr = (unsigned long)__init_begin; - for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) { + addr = (unsigned long)&__init_begin; + for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) { virt_to_page(addr)->flags &= ~(1 << PG_reserved); init_page_count(virt_to_page(addr)); free_page(addr); diff --git a/trunk/arch/m68k/mvme147/config.c b/trunk/arch/m68k/mvme147/config.c index 100baaa692a1..43cdf476ffab 100644 --- a/trunk/arch/m68k/mvme147/config.c +++ b/trunk/arch/m68k/mvme147/config.c @@ -42,6 +42,7 @@ extern unsigned long mvme147_gettimeoffset (void); extern int mvme147_hwclk (int, struct rtc_time *); extern int mvme147_set_clock_mmss (unsigned long); extern void mvme147_reset (void); +extern void mvme147_waitbut(void); static int bcd2int (unsigned char b); @@ -114,9 +115,8 @@ static irqreturn_t mvme147_timer_int (int irq, void *dev_id) void mvme147_sched_init (irq_handler_t timer_routine) { tick_handler = timer_routine; - if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQ_FLG_REPLACE, - "timer 1", NULL)) - pr_err("Couldn't register timer interrupt\n"); + request_irq (PCC_IRQ_TIMER1, mvme147_timer_int, + IRQ_FLG_REPLACE, "timer 1", NULL); /* Init the clock with a value */ /* our clock goes off every 6.25us */ diff --git a/trunk/arch/m68k/mvme16x/config.c b/trunk/arch/m68k/mvme16x/config.c index 11edf61cc2c4..1521826fc3c7 100644 --- a/trunk/arch/m68k/mvme16x/config.c +++ b/trunk/arch/m68k/mvme16x/config.c @@ -48,6 +48,7 @@ extern unsigned long mvme16x_gettimeoffset (void); extern int mvme16x_hwclk (int, struct rtc_time *); extern int mvme16x_set_clock_mmss (unsigned long); extern void mvme16x_reset (void); +extern void mvme16x_waitbut(void); int bcd2int (unsigned char b); diff --git a/trunk/arch/m68k/q40/config.c b/trunk/arch/m68k/q40/config.c index 31ab3f08bbda..7110546e3c00 100644 --- a/trunk/arch/m68k/q40/config.c +++ b/trunk/arch/m68k/q40/config.c @@ -36,6 +36,7 @@ #include #include +extern irqreturn_t q40_process_int(int level, struct pt_regs *regs); extern void q40_init_IRQ(void); static void q40_get_model(char *model); extern void q40_sched_init(irq_handler_t handler); @@ -46,6 +47,8 @@ static unsigned int q40_get_ss(void); static int q40_set_clock_mmss(unsigned long); static int q40_get_rtc_pll(struct rtc_pll_info *pll); static int q40_set_rtc_pll(struct rtc_pll_info *pll); +extern void q40_waitbut(void); +void q40_set_vectors(void); extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); diff --git a/trunk/arch/m68k/sun3/config.c b/trunk/arch/m68k/sun3/config.c index 2ca25bd01a96..8dfaa201342e 100644 --- a/trunk/arch/m68k/sun3/config.c +++ b/trunk/arch/m68k/sun3/config.c @@ -27,21 +27,23 @@ #include #include #include -#include #include #include -#include #include #include +extern char _text, _end; + char sun3_reserved_pmeg[SUN3_PMEGS_NUM]; extern unsigned long sun3_gettimeoffset(void); static void sun3_sched_init(irq_handler_t handler); extern void sun3_get_model (char* model); +extern void idprom_init (void); extern int sun3_hwclk(int set, struct rtc_time *t); volatile char* clock_va; +extern volatile unsigned char* sun3_intreg; extern unsigned long availmem; unsigned long num_pages; @@ -147,7 +149,7 @@ void __init config_sun3(void) mach_halt = sun3_halt; mach_get_hardware_list = sun3_get_hardware_list; - memory_start = ((((unsigned long)_end) + 0x2000) & ~0x1fff); + memory_start = ((((int)&_end) + 0x2000) & ~0x1fff); // PROM seems to want the last couple of physical pages. --m memory_end = *(romvec->pv_sun3mem) + PAGE_OFFSET - 2*PAGE_SIZE; diff --git a/trunk/arch/m68k/sun3/mmu_emu.c b/trunk/arch/m68k/sun3/mmu_emu.c index 3cd19390aae5..60f9d4500d72 100644 --- a/trunk/arch/m68k/sun3/mmu_emu.c +++ b/trunk/arch/m68k/sun3/mmu_emu.c @@ -27,6 +27,7 @@ #include #include +extern void prom_reboot (char *) __attribute__ ((__noreturn__)); #undef DEBUG_MMU_EMU #define DEBUG_PROM_MAPS diff --git a/trunk/arch/m68k/sun3/sun3ints.c b/trunk/arch/m68k/sun3/sun3ints.c index ad90393a3361..7364cd67455e 100644 --- a/trunk/arch/m68k/sun3/sun3ints.c +++ b/trunk/arch/m68k/sun3/sun3ints.c @@ -105,10 +105,7 @@ void __init sun3_init_IRQ(void) m68k_setup_irq_controller(&sun3_irq_controller, IRQ_AUTO_1, 7); m68k_setup_user_interrupt(VEC_USER, 128, NULL); - if (request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL)) - pr_err("Couldn't register %s interrupt\n", "int5"); - if (request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL)) - pr_err("Couldn't register %s interrupt\n", "int7"); - if (request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL)) - pr_err("Couldn't register %s interrupt\n", "vec255"); + request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL); + request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL); + request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL); } diff --git a/trunk/arch/m68k/sun3x/config.c b/trunk/arch/m68k/sun3x/config.c index fc599fad4a54..2b1ca2db070f 100644 --- a/trunk/arch/m68k/sun3x/config.c +++ b/trunk/arch/m68k/sun3x/config.c @@ -23,6 +23,7 @@ #include "time.h" volatile char *clock_va; +extern volatile unsigned char *sun3_intreg; extern void sun3_get_model(char *model); diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 52c80c2a57f2..a5255e7c79e0 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -595,44 +595,6 @@ config WR_PPMC This enables support for the Wind River MIPS32 4KC PPMC evaluation board, which is based on GT64120 bridge chip. -config CAVIUM_OCTEON_SIMULATOR - bool "Support for the Cavium Networks Octeon Simulator" - select CEVT_R4K - select 64BIT_PHYS_ADDR - select DMA_COHERENT - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select CPU_CAVIUM_OCTEON - help - The Octeon simulator is software performance model of the Cavium - Octeon Processor. It supports simulating Octeon processors on x86 - hardware. - -config CAVIUM_OCTEON_REFERENCE_BOARD - bool "Support for the Cavium Networks Octeon reference board" - select CEVT_R4K - select 64BIT_PHYS_ADDR - select DMA_COHERENT - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select CPU_CAVIUM_OCTEON - select SWAP_IO_SPACE - help - This option supports all of the Octeon reference boards from Cavium - Networks. It builds a kernel that dynamically determines the Octeon - CPU type and supports all known board reference implementations. - Some of the supported boards are: - EBT3000 - EBH3000 - EBH3100 - Thunder - Kodama - Hikari - Say Y here for most Octeon reference boards. - endchoice source "arch/mips/alchemy/Kconfig" @@ -645,7 +607,6 @@ source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" -source "arch/mips/cavium-octeon/Kconfig" endmenu @@ -721,11 +682,7 @@ config CEVT_DS1287 config CEVT_GT641XX bool -config CEVT_R4K_LIB - bool - config CEVT_R4K - select CEVT_R4K_LIB bool config CEVT_SB1250 @@ -740,11 +697,7 @@ config CSRC_BCM1480 config CSRC_IOASIC bool -config CSRC_R4K_LIB - bool - config CSRC_R4K - select CSRC_R4K_LIB bool config CSRC_SB1250 @@ -882,9 +835,6 @@ config IRQ_GT641XX config IRQ_GIC bool -config IRQ_CPU_OCTEON - bool - config MIPS_BOARDS_GEN bool @@ -974,7 +924,7 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION || MIKROTIK_RB532 - default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON + default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM default "4" if PMC_MSP4200_EVAL default "5" @@ -1235,23 +1185,6 @@ config CPU_SB1 select CPU_SUPPORTS_HIGHMEM select WEAK_ORDERING -config CPU_CAVIUM_OCTEON - bool "Cavium Octeon processor" - select IRQ_CPU - select IRQ_CPU_OCTEON - select CPU_HAS_PREFETCH - select CPU_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_SMP - select NR_CPUS_DEFAULT_16 - select WEAK_ORDERING - select WEAK_REORDERING_BEYOND_LLSC - select CPU_SUPPORTS_HIGHMEM - help - The Cavium Octeon processor is a highly integrated chip containing - many ethernet hardware widgets for networking tasks. The processor - can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. - Full details can be found at http://www.caviumnetworks.com. - endchoice config SYS_HAS_CPU_LOONGSON2 @@ -1352,7 +1285,7 @@ config CPU_MIPSR1 config CPU_MIPSR2 bool - default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON + default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 config SYS_SUPPORTS_32BIT_KERNEL bool diff --git a/trunk/arch/mips/Makefile b/trunk/arch/mips/Makefile index 21b00e95daef..28c55f608913 100644 --- a/trunk/arch/mips/Makefile +++ b/trunk/arch/mips/Makefile @@ -144,10 +144,6 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ -Wa,--trap -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap -ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon -endif cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) @@ -188,84 +184,84 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 # # AMD Alchemy Pb1000 eval board # -core-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/pb1000/ cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 # # AMD Alchemy Pb1100 eval board # -core-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/pb1100/ cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 # # AMD Alchemy Pb1500 eval board # -core-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/pb1500/ cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 # # AMD Alchemy Pb1550 eval board # -core-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/pb1550/ cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # # AMD Alchemy Pb1200 eval board # -core-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/pb1200/ cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 # # AMD Alchemy Db1000 eval board # -core-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 # # AMD Alchemy Db1100 eval board # -core-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 # # AMD Alchemy Db1500 eval board # -core-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 # # AMD Alchemy Db1550 eval board # -core-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 # # AMD Alchemy Db1200 eval board # -core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/pb1200/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 # # AMD Alchemy Bosporus eval board # -core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 # # AMD Alchemy Mirage eval board # -core-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/devboards/ +libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/db1x00/ cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 @@ -590,18 +586,6 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ -# -# Cavium Octeon -# -core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/ -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon -core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/ -ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL -load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 -else -load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 -endif - cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ diff --git a/trunk/arch/mips/alchemy/Kconfig b/trunk/arch/mips/alchemy/Kconfig index 7f8ef13d0014..e4a057d80ab6 100644 --- a/trunk/arch/mips/alchemy/Kconfig +++ b/trunk/arch/mips/alchemy/Kconfig @@ -128,10 +128,9 @@ config SOC_AU1200 config SOC_AU1X00 bool select 64BIT_PHYS_ADDR - select CEVT_R4K_LIB - select CSRC_R4K_LIB + select CEVT_R4K + select CSRC_R4K select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION - select GENERIC_HARDIRQS_NO__DO_IRQ diff --git a/trunk/arch/mips/alchemy/common/Makefile b/trunk/arch/mips/alchemy/common/Makefile index d50d4764eafe..df48fd65bbf3 100644 --- a/trunk/arch/mips/alchemy/common/Makefile +++ b/trunk/arch/mips/alchemy/common/Makefile @@ -6,8 +6,8 @@ # obj-y += prom.o irq.o puts.o time.o reset.o \ - clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o gpio.o + au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ + sleeper.o cputable.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o diff --git a/trunk/arch/mips/alchemy/common/au1xxx_irqmap.c b/trunk/arch/mips/alchemy/common/au1xxx_irqmap.c new file mode 100644 index 000000000000..c7ca1596394c --- /dev/null +++ b/trunk/arch/mips/alchemy/common/au1xxx_irqmap.c @@ -0,0 +1,205 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx processor specific IRQ tables + * + * Copyright 2004 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include + +#include + +/* The IC0 interrupt table. This is processor, rather than + * board dependent, so no reason to keep this info in the board + * dependent files. + * + * Careful if you change match 2 request! + * The interrupt handler is called directly from the low level dispatch code. + */ +struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = { + +#if defined(CONFIG_SOC_AU1000) + { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, + +#elif defined(CONFIG_SOC_AU1500) + + { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, + +#elif defined(CONFIG_SOC_AU1100) + + { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */ + { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 }, + +#elif defined(CONFIG_SOC_AU1550) + + { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 }, + { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + +#elif defined(CONFIG_SOC_AU1200) + + { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 }, + { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 }, + { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 }, + +#else +#error "Error: Unknown Alchemy SOC" +#endif + +}; + +int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map); diff --git a/trunk/arch/mips/alchemy/common/clocks.c b/trunk/arch/mips/alchemy/common/clocks.c index d8991854530e..043429d17c5f 100644 --- a/trunk/arch/mips/alchemy/common/clocks.c +++ b/trunk/arch/mips/alchemy/common/clocks.c @@ -27,21 +27,12 @@ */ #include -#include -#include #include -/* - * I haven't found anyone that doesn't use a 12 MHz source clock, - * but just in case..... - */ -#define AU1000_SRC_CLK 12000000 - static unsigned int au1x00_clock; /* Hz */ +static unsigned int lcd_clock; /* KHz */ static unsigned long uart_baud_base; -static DEFINE_SPINLOCK(time_lock); - /* * Set the au1000_clock */ @@ -72,45 +63,31 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) } /* - * We read the real processor speed from the PLL. This is important - * because it is more accurate than computing it from the 32 KHz - * counter, if it exists. If we don't have an accurate processor - * speed, all of the peripherals that derive their clocks based on - * this advertised speed will introduce error and sometimes not work - * properly. This function is futher convoluted to still allow configurations - * to do that in case they have really, really old silicon with a - * write-only PLL register. -- Dan + * Calculate the Au1x00's LCD clock based on the current + * cpu clock and the system bus clock, and try to keep it + * below 40 MHz (the Pb1000 board can lock-up if the LCD + * clock is over 40 MHz). */ -unsigned long au1xxx_calc_clock(void) +void set_au1x00_lcd_clock(void) { - unsigned long cpu_speed; - unsigned long flags; + unsigned int static_cfg0; + unsigned int sys_busclk = (get_au1x00_speed() / 1000) / + ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2); - spin_lock_irqsave(&time_lock, flags); + static_cfg0 = au_readl(MEM_STCFG0); - /* - * On early Au1000, sys_cpupll was write-only. Since these - * silicon versions of Au1000 are not sold by AMD, we don't bend - * over backwards trying to determine the frequency. - */ - if (au1xxx_cpu_has_pll_wo()) -#ifdef CONFIG_SOC_AU1000_FREQUENCY - cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; -#else - cpu_speed = 396000000; -#endif + if (static_cfg0 & (1 << 11)) + lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ else - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; + lcd_clock = sys_busclk / 4; - /* On Alchemy CPU:counter ratio is 1:1 */ - mips_hpt_frequency = cpu_speed; - /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ - set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) - & 0x03) + 2) * 16)); - - spin_unlock_irqrestore(&time_lock, flags); - - set_au1x00_speed(cpu_speed); + if (lcd_clock > 50000) /* Epson MAX */ + printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", + lcd_clock); +} - return cpu_speed; +unsigned int get_au1x00_lcd_clock(void) +{ + return lcd_clock; } +EXPORT_SYMBOL(get_au1x00_lcd_clock); diff --git a/trunk/arch/mips/alchemy/common/cputable.c b/trunk/arch/mips/alchemy/common/cputable.c new file mode 100644 index 000000000000..ba6430bc2d03 --- /dev/null +++ b/trunk/arch/mips/alchemy/common/cputable.c @@ -0,0 +1,52 @@ +/* + * arch/mips/au1000/common/cputable.c + * + * Copyright (C) 2004 Dan Malek (dan@embeddededge.com) + * Copied from PowerPC and updated for Alchemy Au1xxx processors. + * + * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include + +struct cpu_spec *cur_cpu_spec[NR_CPUS]; + +/* With some thought, we can probably use the mask to reduce the + * size of the table. + */ +struct cpu_spec cpu_specs[] = { + { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 }, + { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 }, + { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 }, + { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 }, + { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 }, + { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 }, + { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 }, + { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 }, + { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 }, + { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 }, + { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 }, + { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 }, + { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 }, + { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 }, + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 }, + { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 }, + { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } +}; + +void set_cpuspec(void) +{ + struct cpu_spec *sp; + u32 prid; + + prid = read_c0_prid(); + sp = cpu_specs; + while ((prid & sp->prid_mask) != sp->prid_value) + sp++; + cur_cpu_spec[0] = sp; +} diff --git a/trunk/arch/mips/alchemy/common/dbdma.c b/trunk/arch/mips/alchemy/common/dbdma.c index 3ab6d80d150d..601ee9180ee4 100644 --- a/trunk/arch/mips/alchemy/common/dbdma.c +++ b/trunk/arch/mips/alchemy/common/dbdma.c @@ -174,11 +174,6 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) -#ifdef CONFIG_PM -static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8]; -#endif - - static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; static dbdev_tab_t *find_dbdev_id(u32 id) @@ -980,64 +975,4 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void) -{ - int i; - u32 addr; - - addr = DDMA_GLOBAL_BASE; - au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); - - /* save channel configurations */ - for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { - au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); - au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); - au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); - au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); - au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); - au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); - au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18); - - /* halt channel */ - au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); - au_sync(); - while (!(au_readl(addr + 0x14) & 1)) - au_sync(); - - addr += 0x100; /* next channel base */ - } - /* disable channel interrupts */ - au_writel(0, DDMA_GLOBAL_BASE + 0x0c); - au_sync(); -} - -void au1xxx_dbdma_resume(void) -{ - int i; - u32 addr; - - addr = DDMA_GLOBAL_BASE; - au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); - - /* restore channel configurations */ - for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { - au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); - au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); - au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); - au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); - au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); - au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); - au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18); - au_sync(); - addr += 0x100; /* next channel base */ - } -} -#endif /* CONFIG_PM */ #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/trunk/arch/mips/alchemy/common/irq.c b/trunk/arch/mips/alchemy/common/irq.c index c88c821b4c36..40c6ceceb5f9 100644 --- a/trunk/arch/mips/alchemy/common/irq.c +++ b/trunk/arch/mips/alchemy/common/irq.c @@ -24,7 +24,6 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - #include #include #include @@ -37,172 +36,15 @@ #include #endif -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); - -/* per-processor fixed function irqs */ -struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { - -#if defined(CONFIG_SOC_AU1000) - { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, - -#elif defined(CONFIG_SOC_AU1500) - - { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, - -#elif defined(CONFIG_SOC_AU1100) - - { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, - -#elif defined(CONFIG_SOC_AU1550) - - { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - -#elif defined(CONFIG_SOC_AU1200) - - { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - -#else -#error "Error: Unknown Alchemy SOC" -#endif -}; +#define EXT_INTC0_REQ0 2 /* IP 2 */ +#define EXT_INTC0_REQ1 3 /* IP 3 */ +#define EXT_INTC1_REQ0 4 /* IP 4 */ +#define EXT_INTC1_REQ1 5 /* IP 5 */ +#define MIPS_TIMER_IP 7 /* IP 7 */ + +void (*board_init_irq)(void) __initdata = NULL; +static DEFINE_SPINLOCK(irq_lock); #ifdef CONFIG_PM @@ -288,47 +130,67 @@ void restore_au1xxx_intctl(void) #endif /* CONFIG_PM */ -static void au1x_ic0_unmask(unsigned int irq_nr) +inline void local_enable_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKSET); - au_writel(1 << bit, IC0_WAKESET); + + if (bit >= 32) { + au_writel(1 << (bit - 32), IC1_MASKSET); + au_writel(1 << (bit - 32), IC1_WAKESET); + } else { + au_writel(1 << bit, IC0_MASKSET); + au_writel(1 << bit, IC0_WAKESET); + } au_sync(); } -static void au1x_ic1_unmask(unsigned int irq_nr) + +inline void local_disable_irq(unsigned int irq_nr) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKSET); - au_writel(1 << bit, IC1_WAKESET); + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; -/* very hacky. does the pb1000 cpld auto-disable this int? - * nowhere in the current kernel sources is it disabled. --mlau - */ -#if defined(CONFIG_MIPS_PB1000) - if (irq_nr == AU1000_GPIO_15) - au_writel(0x4000, PB1000_MDR); /* enable int */ -#endif + if (bit >= 32) { + au_writel(1 << (bit - 32), IC1_MASKCLR); + au_writel(1 << (bit - 32), IC1_WAKECLR); + } else { + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_WAKECLR); + } au_sync(); } -static void au1x_ic0_mask(unsigned int irq_nr) + +static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; - au_writel(1 << bit, IC0_MASKCLR); - au_writel(1 << bit, IC0_WAKECLR); + + if (bit >= 32) { + au_writel(1 << (bit - 32), IC1_RISINGCLR); + au_writel(1 << (bit - 32), IC1_MASKCLR); + } else { + au_writel(1 << bit, IC0_RISINGCLR); + au_writel(1 << bit, IC0_MASKCLR); + } au_sync(); } -static void au1x_ic1_mask(unsigned int irq_nr) + +static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; - au_writel(1 << bit, IC1_MASKCLR); - au_writel(1 << bit, IC1_WAKECLR); + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + + if (bit >= 32) { + au_writel(1 << (bit - 32), IC1_FALLINGCLR); + au_writel(1 << (bit - 32), IC1_MASKCLR); + } else { + au_writel(1 << bit, IC0_FALLINGCLR); + au_writel(1 << bit, IC0_MASKCLR); + } au_sync(); } -static void au1x_ic0_ack(unsigned int irq_nr) + +static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -336,229 +198,349 @@ static void au1x_ic0_ack(unsigned int irq_nr) * This may assume that we don't get interrupts from * both edges at once, or if we do, that we don't care. */ - au_writel(1 << bit, IC0_FALLINGCLR); - au_writel(1 << bit, IC0_RISINGCLR); + if (bit >= 32) { + au_writel(1 << (bit - 32), IC1_FALLINGCLR); + au_writel(1 << (bit - 32), IC1_RISINGCLR); + au_writel(1 << (bit - 32), IC1_MASKCLR); + } else { + au_writel(1 << bit, IC0_FALLINGCLR); + au_writel(1 << bit, IC0_RISINGCLR); + au_writel(1 << bit, IC0_MASKCLR); + } au_sync(); } -static void au1x_ic1_ack(unsigned int irq_nr) +static inline void mask_and_ack_level_irq(unsigned int irq_nr) { - unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; - - /* - * This may assume that we don't get interrupts from - * both edges at once, or if we do, that we don't care. - */ - au_writel(1 << bit, IC1_FALLINGCLR); - au_writel(1 << bit, IC1_RISINGCLR); + local_disable_irq(irq_nr); au_sync(); +#if defined(CONFIG_MIPS_PB1000) + if (irq_nr == AU1000_GPIO_15) { + au_writel(0x8000, PB1000_MDR); /* ack int */ + au_sync(); + } +#endif } -static int au1x_ic1_setwake(unsigned int irq, unsigned int on) +static void end_irq(unsigned int irq_nr) { - unsigned int bit = irq - AU1000_INTC1_INT_BASE; - unsigned long wakemsk, flags; + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + local_enable_irq(irq_nr); + +#if defined(CONFIG_MIPS_PB1000) + if (irq_nr == AU1000_GPIO_15) { + au_writel(0x4000, PB1000_MDR); /* enable int */ + au_sync(); + } +#endif +} + +unsigned long save_local_and_disable(int controller) +{ + int i; + unsigned long flags, mask; + + spin_lock_irqsave(&irq_lock, flags); + if (controller) { + mask = au_readl(IC1_MASKSET); + for (i = 32; i < 64; i++) + local_disable_irq(i); + } else { + mask = au_readl(IC0_MASKSET); + for (i = 0; i < 32; i++) + local_disable_irq(i); + } + spin_unlock_irqrestore(&irq_lock, flags); + + return mask; +} - /* only GPIO 0-7 can act as wakeup source: */ - if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) - return -EINVAL; +void restore_local_and_enable(int controller, unsigned long mask) +{ + int i; + unsigned long flags, new_mask; + + spin_lock_irqsave(&irq_lock, flags); + for (i = 0; i < 32; i++) + if (mask & (1 << i)) { + if (controller) + local_enable_irq(i + 32); + else + local_enable_irq(i); + } - local_irq_save(flags); - wakemsk = au_readl(SYS_WAKEMSK); - if (on) - wakemsk |= 1 << bit; + if (controller) + new_mask = au_readl(IC1_MASKSET); else - wakemsk &= ~(1 << bit); - au_writel(wakemsk, SYS_WAKEMSK); - au_sync(); - local_irq_restore(flags); + new_mask = au_readl(IC0_MASKSET); - return 0; + spin_unlock_irqrestore(&irq_lock, flags); } -/* - * irq_chips for both ICs; this way the mask handlers can be - * as short as possible. - * - * NOTE: the ->ack() callback is used by the handle_edge_irq - * flowhandler only, the ->mask_ack() one by handle_level_irq, - * so no need for an irq_chip for each type of irq (level/edge). - */ -static struct irq_chip au1x_ic0_chip = { - .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, /* edge */ - .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_mask, /* level */ - .unmask = au1x_ic0_unmask, - .set_type = au1x_ic_settype, + +static struct irq_chip rise_edge_irq_type = { + .name = "Au1000 Rise Edge", + .ack = mask_and_ack_rise_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_rise_edge_irq, + .unmask = local_enable_irq, + .end = end_irq, +}; + +static struct irq_chip fall_edge_irq_type = { + .name = "Au1000 Fall Edge", + .ack = mask_and_ack_fall_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_fall_edge_irq, + .unmask = local_enable_irq, + .end = end_irq, +}; + +static struct irq_chip either_edge_irq_type = { + .name = "Au1000 Rise or Fall Edge", + .ack = mask_and_ack_either_edge_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_either_edge_irq, + .unmask = local_enable_irq, + .end = end_irq, }; -static struct irq_chip au1x_ic1_chip = { - .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, /* edge */ - .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_mask, /* level */ - .unmask = au1x_ic1_unmask, - .set_type = au1x_ic_settype, - .set_wake = au1x_ic1_setwake, +static struct irq_chip level_irq_type = { + .name = "Au1000 Level", + .ack = mask_and_ack_level_irq, + .mask = local_disable_irq, + .mask_ack = mask_and_ack_level_irq, + .unmask = local_enable_irq, + .end = end_irq, }; -static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) +static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) { - struct irq_chip *chip; - unsigned long icr[6]; - unsigned int bit, ic; - int ret; - - if (irq >= AU1000_INTC1_INT_BASE) { - bit = irq - AU1000_INTC1_INT_BASE; - chip = &au1x_ic1_chip; - ic = 1; - } else { - bit = irq - AU1000_INTC0_INT_BASE; - chip = &au1x_ic0_chip; - ic = 0; - } + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + + if (irq_nr > AU1000_MAX_INTR) + return; - if (bit > 31) - return -EINVAL; - - icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET; - icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET; - icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET; - icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR; - icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR; - icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR; - - ret = 0; - - switch (flow_type) { /* cfgregs 2:1:0 */ - case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "riseedge"); - break; - case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "falledge"); - break; - case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_edge_irq, "bothedge"); - break; - case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[0]); - set_irq_chip_and_handler_name(irq, chip, - handle_level_irq, "hilevel"); - break; - case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ - au_writel(1 << bit, icr[2]); - au_writel(1 << bit, icr[1]); - au_writel(1 << bit, icr[3]); - set_irq_chip_and_handler_name(irq, chip, - handle_level_irq, "lowlevel"); - break; - case IRQ_TYPE_NONE: /* 0:0:0 */ - au_writel(1 << bit, icr[5]); - au_writel(1 << bit, icr[4]); - au_writel(1 << bit, icr[3]); - /* set at least chip so we can call set_irq_type() on it */ - set_irq_chip(irq, chip); - break; - default: - ret = -EINVAL; + /* Config2[n], Config1[n], Config0[n] */ + if (bit >= 32) { + switch (type) { + case INTC_INT_RISE_EDGE: /* 0:0:1 */ + au_writel(1 << (bit - 32), IC1_CFG2CLR); + au_writel(1 << (bit - 32), IC1_CFG1CLR); + au_writel(1 << (bit - 32), IC1_CFG0SET); + set_irq_chip(irq_nr, &rise_edge_irq_type); + break; + case INTC_INT_FALL_EDGE: /* 0:1:0 */ + au_writel(1 << (bit - 32), IC1_CFG2CLR); + au_writel(1 << (bit - 32), IC1_CFG1SET); + au_writel(1 << (bit - 32), IC1_CFG0CLR); + set_irq_chip(irq_nr, &fall_edge_irq_type); + break; + case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ + au_writel(1 << (bit - 32), IC1_CFG2CLR); + au_writel(1 << (bit - 32), IC1_CFG1SET); + au_writel(1 << (bit - 32), IC1_CFG0SET); + set_irq_chip(irq_nr, &either_edge_irq_type); + break; + case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ + au_writel(1 << (bit - 32), IC1_CFG2SET); + au_writel(1 << (bit - 32), IC1_CFG1CLR); + au_writel(1 << (bit - 32), IC1_CFG0SET); + set_irq_chip(irq_nr, &level_irq_type); + break; + case INTC_INT_LOW_LEVEL: /* 1:1:0 */ + au_writel(1 << (bit - 32), IC1_CFG2SET); + au_writel(1 << (bit - 32), IC1_CFG1SET); + au_writel(1 << (bit - 32), IC1_CFG0CLR); + set_irq_chip(irq_nr, &level_irq_type); + break; + case INTC_INT_DISABLED: /* 0:0:0 */ + au_writel(1 << (bit - 32), IC1_CFG0CLR); + au_writel(1 << (bit - 32), IC1_CFG1CLR); + au_writel(1 << (bit - 32), IC1_CFG2CLR); + break; + default: /* disable the interrupt */ + printk(KERN_WARNING "unexpected int type %d (irq %d)\n", + type, irq_nr); + au_writel(1 << (bit - 32), IC1_CFG0CLR); + au_writel(1 << (bit - 32), IC1_CFG1CLR); + au_writel(1 << (bit - 32), IC1_CFG2CLR); + return; + } + if (int_req) /* assign to interrupt request 1 */ + au_writel(1 << (bit - 32), IC1_ASSIGNCLR); + else /* assign to interrupt request 0 */ + au_writel(1 << (bit - 32), IC1_ASSIGNSET); + au_writel(1 << (bit - 32), IC1_SRCSET); + au_writel(1 << (bit - 32), IC1_MASKCLR); + au_writel(1 << (bit - 32), IC1_WAKECLR); + } else { + switch (type) { + case INTC_INT_RISE_EDGE: /* 0:0:1 */ + au_writel(1 << bit, IC0_CFG2CLR); + au_writel(1 << bit, IC0_CFG1CLR); + au_writel(1 << bit, IC0_CFG0SET); + set_irq_chip(irq_nr, &rise_edge_irq_type); + break; + case INTC_INT_FALL_EDGE: /* 0:1:0 */ + au_writel(1 << bit, IC0_CFG2CLR); + au_writel(1 << bit, IC0_CFG1SET); + au_writel(1 << bit, IC0_CFG0CLR); + set_irq_chip(irq_nr, &fall_edge_irq_type); + break; + case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ + au_writel(1 << bit, IC0_CFG2CLR); + au_writel(1 << bit, IC0_CFG1SET); + au_writel(1 << bit, IC0_CFG0SET); + set_irq_chip(irq_nr, &either_edge_irq_type); + break; + case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ + au_writel(1 << bit, IC0_CFG2SET); + au_writel(1 << bit, IC0_CFG1CLR); + au_writel(1 << bit, IC0_CFG0SET); + set_irq_chip(irq_nr, &level_irq_type); + break; + case INTC_INT_LOW_LEVEL: /* 1:1:0 */ + au_writel(1 << bit, IC0_CFG2SET); + au_writel(1 << bit, IC0_CFG1SET); + au_writel(1 << bit, IC0_CFG0CLR); + set_irq_chip(irq_nr, &level_irq_type); + break; + case INTC_INT_DISABLED: /* 0:0:0 */ + au_writel(1 << bit, IC0_CFG0CLR); + au_writel(1 << bit, IC0_CFG1CLR); + au_writel(1 << bit, IC0_CFG2CLR); + break; + default: /* disable the interrupt */ + printk(KERN_WARNING "unexpected int type %d (irq %d)\n", + type, irq_nr); + au_writel(1 << bit, IC0_CFG0CLR); + au_writel(1 << bit, IC0_CFG1CLR); + au_writel(1 << bit, IC0_CFG2CLR); + return; + } + if (int_req) /* assign to interrupt request 1 */ + au_writel(1 << bit, IC0_ASSIGNCLR); + else /* assign to interrupt request 0 */ + au_writel(1 << bit, IC0_ASSIGNSET); + au_writel(1 << bit, IC0_SRCSET); + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_WAKECLR); } au_sync(); - - return ret; } -asmlinkage void plat_irq_dispatch(void) +/* + * Interrupts are nested. Even if an interrupt handler is registered + * as "fast", we might get another interrupt before we return from + * intcX_reqX_irqdispatch(). + */ + +static void intc0_req0_irqdispatch(void) { - unsigned int pending = read_c0_status() & read_c0_cause(); - unsigned long s, off, bit; + static unsigned long intc0_req0; + unsigned int bit; - if (pending & CAUSEF_IP7) { - do_IRQ(MIPS_CPU_IRQ_BASE + 7); - return; - } else if (pending & CAUSEF_IP2) { - s = IC0_REQ0INT; - off = AU1000_INTC0_INT_BASE; - } else if (pending & CAUSEF_IP3) { - s = IC0_REQ1INT; - off = AU1000_INTC0_INT_BASE; - } else if (pending & CAUSEF_IP4) { - s = IC1_REQ0INT; - off = AU1000_INTC1_INT_BASE; - } else if (pending & CAUSEF_IP5) { - s = IC1_REQ1INT; - off = AU1000_INTC1_INT_BASE; - } else - goto spurious; - - bit = 0; - s = au_readl(s); - if (unlikely(!s)) { -spurious: - spurious_interrupt(); + intc0_req0 |= au_readl(IC0_REQ0INT); + + if (!intc0_req0) return; - } + #ifdef AU1000_USB_DEV_REQ_INT /* * Because of the tight timing of SETUP token to reply * transactions, the USB devices-side packet complete * interrupt needs the highest priority. */ - bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE); - if ((pending & CAUSEF_IP2) && (s & bit)) { + if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) { + intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT); do_IRQ(AU1000_USB_DEV_REQ_INT); return; } #endif - do_IRQ(__ffs(s) + off); + bit = __ffs(intc0_req0); + intc0_req0 &= ~(1 << bit); + do_IRQ(AU1000_INTC0_INT_BASE + bit); } -/* setup edge/level and assign request 0/1 */ -void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count) + +static void intc0_req1_irqdispatch(void) { - unsigned int bit, irq_nr; - - while (count--) { - irq_nr = map[count].im_irq; - - if (((irq_nr < AU1000_INTC0_INT_BASE) || - (irq_nr >= AU1000_INTC0_INT_BASE + 32)) && - ((irq_nr < AU1000_INTC1_INT_BASE) || - (irq_nr >= AU1000_INTC1_INT_BASE + 32))) - continue; - - if (irq_nr >= AU1000_INTC1_INT_BASE) { - bit = irq_nr - AU1000_INTC1_INT_BASE; - if (map[count].im_request) - au_writel(1 << bit, IC1_ASSIGNCLR); - } else { - bit = irq_nr - AU1000_INTC0_INT_BASE; - if (map[count].im_request) - au_writel(1 << bit, IC0_ASSIGNCLR); - } + static unsigned long intc0_req1; + unsigned int bit; - au1x_ic_settype(irq_nr, map[count].im_type); - } + intc0_req1 |= au_readl(IC0_REQ1INT); + + if (!intc0_req1) + return; + + bit = __ffs(intc0_req1); + intc0_req1 &= ~(1 << bit); + do_IRQ(AU1000_INTC0_INT_BASE + bit); +} + + +/* + * Interrupt Controller 1: + * interrupts 32 - 63 + */ +static void intc1_req0_irqdispatch(void) +{ + static unsigned long intc1_req0; + unsigned int bit; + + intc1_req0 |= au_readl(IC1_REQ0INT); + + if (!intc1_req0) + return; + + bit = __ffs(intc1_req0); + intc1_req0 &= ~(1 << bit); + do_IRQ(AU1000_INTC1_INT_BASE + bit); +} + + +static void intc1_req1_irqdispatch(void) +{ + static unsigned long intc1_req1; + unsigned int bit; + + intc1_req1 |= au_readl(IC1_REQ1INT); + + if (!intc1_req1) + return; + + bit = __ffs(intc1_req1); + intc1_req1 &= ~(1 << bit); + do_IRQ(AU1000_INTC1_INT_BASE + bit); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & CAUSEF_IP2) + intc0_req0_irqdispatch(); + else if (pending & CAUSEF_IP3) + intc0_req1_irqdispatch(); + else if (pending & CAUSEF_IP4) + intc1_req0_irqdispatch(); + else if (pending & CAUSEF_IP5) + intc1_req1_irqdispatch(); + else + spurious_interrupt(); } void __init arch_init_irq(void) { int i; + struct au1xxx_irqmap *imp; + extern struct au1xxx_irqmap au1xxx_irq_map[]; + extern struct au1xxx_irqmap au1xxx_ic0_map[]; + extern int au1xxx_nr_irqs; + extern int au1xxx_ic0_nr_irqs; /* * Initialize interrupt controllers to a safe state. @@ -587,25 +569,28 @@ void __init arch_init_irq(void) mips_cpu_irq_init(); - /* register all 64 possible IC0+IC1 irq sources as type "none". - * Use set_irq_type() to set edge/level behaviour at runtime. + /* + * Initialize IC0, which is fixed per processor. */ - for (i = AU1000_INTC0_INT_BASE; - (i < AU1000_INTC0_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); - - for (i = AU1000_INTC1_INT_BASE; - (i < AU1000_INTC1_INT_BASE + 32); i++) - au1x_ic_settype(i, IRQ_TYPE_NONE); + imp = au1xxx_ic0_map; + for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { + setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); + imp++; + } /* - * Initialize IC0, which is fixed per processor. + * Now set up the irq mapping for the board. */ - au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map)); + imp = au1xxx_irq_map; + for (i = 0; i < au1xxx_nr_irqs; i++) { + setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); + imp++; + } - /* Boards can register additional (GPIO-based) IRQs. - */ - board_init_irq(); + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); + /* Board specific IRQ initialization. + */ + if (board_init_irq) + board_init_irq(); } diff --git a/trunk/arch/mips/alchemy/common/power.c b/trunk/arch/mips/alchemy/common/power.c index 6ab7b42aa1be..bd854a6d1d89 100644 --- a/trunk/arch/mips/alchemy/common/power.c +++ b/trunk/arch/mips/alchemy/common/power.c @@ -35,13 +35,26 @@ #include #include +#include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) -#include -#endif #ifdef CONFIG_PM +#define DEBUG 1 +#ifdef DEBUG +#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +static void au1000_calibrate_delay(void); + +extern unsigned long save_local_and_disable(int controller); +extern void restore_local_and_enable(int controller, unsigned long mask); +extern void local_enable_irq(unsigned int irq_nr); + +static DEFINE_SPINLOCK(pm_lock); + /* * We need to save/restore a bunch of core registers that are * either volatile or reset to some state across a processor sleep. @@ -52,16 +65,29 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_uart0_inten; -static unsigned int sleep_uart0_fifoctl; -static unsigned int sleep_uart0_linectl; -static unsigned int sleep_uart0_clkdiv; -static unsigned int sleep_uart0_enable; -static unsigned int sleep_usb[2]; -static unsigned int sleep_sys_clocks[5]; -static unsigned int sleep_sys_pinfunc; -static unsigned int sleep_static_memctlr[4][3]; +static unsigned int sleep_aux_pll_cntrl; +static unsigned int sleep_cpu_pll_cntrl; +static unsigned int sleep_pin_function; +static unsigned int sleep_uart0_inten; +static unsigned int sleep_uart0_fifoctl; +static unsigned int sleep_uart0_linectl; +static unsigned int sleep_uart0_clkdiv; +static unsigned int sleep_uart0_enable; +static unsigned int sleep_usbhost_enable; +static unsigned int sleep_usbdev_enable; +static unsigned int sleep_static_memctlr[4][3]; +/* + * Define this to cause the value you write to /proc/sys/pm/sleep to + * set the TOY timer for the amount of time you want to sleep. + * This is done mainly for testing, but may be useful in other cases. + * The value is number of 32KHz ticks to sleep. + */ +#define SLEEP_TEST_TIMEOUT 1 +#ifdef SLEEP_TEST_TIMEOUT +static int sleep_ticks; +void wakeup_counter0_set(int ticks); +#endif static void save_core_regs(void) { @@ -79,45 +105,31 @@ static void save_core_regs(void) sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); - au_sync(); -#ifndef CONFIG_SOC_AU1200 /* Shutdown USB host/device. */ - sleep_usb[0] = au_readl(USB_HOST_CONFIG); + sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); /* There appears to be some undocumented reset register.... */ - au_writel(0, 0xb0100004); - au_sync(); - au_writel(0, USB_HOST_CONFIG); - au_sync(); + au_writel(0, 0xb0100004); au_sync(); + au_writel(0, USB_HOST_CONFIG); au_sync(); - sleep_usb[1] = au_readl(USBD_ENABLE); - au_writel(0, USBD_ENABLE); - au_sync(); - -#else /* AU1200 */ - - /* enable access to OTG mmio so we can save OTG CAP/MUX. - * FIXME: write an OTG driver and move this stuff there! - */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ - sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ -#endif + sleep_usbdev_enable = au_readl(USBD_ENABLE); + au_writel(0, USBD_ENABLE); au_sync(); /* Save interrupt controller state. */ save_au1xxx_intctl(); /* Clocks and PLLs. */ - sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); - sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); - sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); - sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); - sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); + sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); - /* pin mux config */ - sleep_sys_pinfunc = au_readl(SYS_PINFUNC); + /* + * We don't really need to do this one, but unless we + * write it again it won't have a valid value if we + * happen to read it. + */ + sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL); + + sleep_pin_function = au_readl(SYS_PINFUNC); /* Save the static memory controller configuration. */ sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); @@ -132,45 +144,16 @@ static void save_core_regs(void) sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_suspend(); -#endif } static void restore_core_regs(void) { - /* restore clock configuration. Writing CPUPLL last will - * stall a bit and stabilize other clocks (unless this is - * one of those Au1000 with a write-only PLL, where we dont - * have a valid value) - */ - au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); - au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); - au_writel(sleep_sys_clocks[2], SYS_CLKSRC); - au_writel(sleep_sys_clocks[4], SYS_AUXPLL); - if (!au1xxx_cpu_has_pll_wo()) - au_writel(sleep_sys_clocks[3], SYS_CPUPLL); - au_sync(); + extern void restore_au1xxx_intctl(void); + extern void wakeup_counter0_adjust(void); - au_writel(sleep_sys_pinfunc, SYS_PINFUNC); - au_sync(); - -#ifndef CONFIG_SOC_AU1200 - au_writel(sleep_usb[0], USB_HOST_CONFIG); - au_writel(sleep_usb[1], USBD_ENABLE); - au_sync(); -#else - /* enable accces to OTG memory */ - au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); - au_sync(); - - /* restore OTG caps and port mux. */ - au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ - au_sync(); - au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ - au_sync(); -#endif + au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); + au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); + au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); @@ -201,17 +184,282 @@ static void restore_core_regs(void) } restore_au1xxx_intctl(); + wakeup_counter0_adjust(); +} -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - au1xxx_dbdma_resume(); -#endif +unsigned long suspend_mode; + +void wakeup_from_suspend(void) +{ + suspend_mode = 0; } -void au_sleep(void) +int au_sleep(void) { + unsigned long wakeup, flags; + extern void save_and_sleep(void); + + spin_lock_irqsave(&pm_lock, flags); + save_core_regs(); - au1xxx_save_and_sleep(); + + flush_cache_all(); + + /** + ** The code below is all system dependent and we should probably + ** have a function call out of here to set this up. You need + ** to configure the GPIO or timer interrupts that will bring + ** you out of sleep. + ** For testing, the TOY counter wakeup is useful. + **/ +#if 0 + au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); + + /* GPIO 6 can cause a wake up event */ + wakeup = au_readl(SYS_WAKEMSK); + wakeup &= ~(1 << 8); /* turn off match20 wakeup */ + wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ +#else + /* For testing, allow match20 to wake us up. */ +#ifdef SLEEP_TEST_TIMEOUT + wakeup_counter0_set(sleep_ticks); +#endif + wakeup = 1 << 8; /* turn on match20 wakeup */ + wakeup = 0; +#endif + au_writel(1, SYS_WAKESRC); /* clear cause */ + au_sync(); + au_writel(wakeup, SYS_WAKEMSK); + au_sync(); + + save_and_sleep(); + + /* + * After a wakeup, the cpu vectors back to 0x1fc00000, so + * it's up to the boot code to get us back here. + */ restore_core_regs(); + spin_unlock_irqrestore(&pm_lock, flags); + return 0; +} + +static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, + void __user *buffer, size_t *len, loff_t *ppos) +{ +#ifdef SLEEP_TEST_TIMEOUT +#define TMPBUFLEN2 16 + char buf[TMPBUFLEN2], *p; +#endif + + if (!write) + *len = 0; + else { +#ifdef SLEEP_TEST_TIMEOUT + if (*len > TMPBUFLEN2 - 1) + return -EFAULT; + if (copy_from_user(buf, buffer, *len)) + return -EFAULT; + buf[*len] = 0; + p = buf; + sleep_ticks = simple_strtoul(p, &p, 0); +#endif + + au_sleep(); + } + return 0; +} + +static int pm_do_freq(ctl_table *ctl, int write, struct file *file, + void __user *buffer, size_t *len, loff_t *ppos) +{ + int retval = 0, i; + unsigned long val, pll; +#define TMPBUFLEN 64 +#define MAX_CPU_FREQ 396 + char buf[TMPBUFLEN], *p; + unsigned long flags, intc0_mask, intc1_mask; + unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; + unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; + unsigned long baud_rate; + + spin_lock_irqsave(&pm_lock, flags); + if (!write) + *len = 0; + else { + /* Parse the new frequency */ + if (*len > TMPBUFLEN - 1) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + if (copy_from_user(buf, buffer, *len)) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + buf[*len] = 0; + p = buf; + val = simple_strtoul(p, &p, 0); + if (val > MAX_CPU_FREQ) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + pll = val / 12; + if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ + /* Revisit this for higher speed CPUs */ + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + old_baud_base = get_au1x00_uart_baud_base(); + old_cpu_freq = get_au1x00_speed(); + + new_cpu_freq = pll * 12 * 1000000; + new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) + & 0x03) + 2) * 16)); + set_au1x00_speed(new_cpu_freq); + set_au1x00_uart_baud_base(new_baud_base); + + old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; + new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | + (au_readl(MEM_SDREFCFG) & ~0x1ffffff); + + au_writel(pll, SYS_CPUPLL); + au_sync_delay(1); + au_writel(new_refresh, MEM_SDREFCFG); + au_sync_delay(1); + + for (i = 0; i < 4; i++) + if (au_readl(UART_BASE + UART_MOD_CNTRL + + i * 0x00100000) == 3) { + old_clk = au_readl(UART_BASE + UART_CLK + + i * 0x00100000); + baud_rate = old_baud_base / old_clk; + /* + * We won't get an exact baud rate and the error + * could be significant enough that our new + * calculation will result in a clock that will + * give us a baud rate that's too far off from + * what we really want. + */ + if (baud_rate > 100000) + baud_rate = 115200; + else if (baud_rate > 50000) + baud_rate = 57600; + else if (baud_rate > 30000) + baud_rate = 38400; + else if (baud_rate > 17000) + baud_rate = 19200; + else + baud_rate = 9600; + new_clk = new_baud_base / baud_rate; + au_writel(new_clk, UART_BASE + UART_CLK + + i * 0x00100000); + au_sync_delay(10); + } + } + + /* + * We don't want _any_ interrupts other than match20. Otherwise our + * au1000_calibrate_delay() calculation will be off, potentially a lot. + */ + intc0_mask = save_local_and_disable(0); + intc1_mask = save_local_and_disable(1); + local_enable_irq(AU1000_TOY_MATCH2_INT); + spin_unlock_irqrestore(&pm_lock, flags); + au1000_calibrate_delay(); + restore_local_and_enable(0, intc0_mask); + restore_local_and_enable(1, intc1_mask); + + return retval; } + +static struct ctl_table pm_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "sleep", + .data = NULL, + .maxlen = 0, + .mode = 0600, + .proc_handler = &pm_do_sleep + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "freq", + .data = NULL, + .maxlen = 0, + .mode = 0600, + .proc_handler = &pm_do_freq + }, + {} +}; + +static struct ctl_table pm_dir_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "pm", + .mode = 0555, + .child = pm_table + }, + {} +}; + +/* + * Initialize power interface + */ +static int __init pm_init(void) +{ + register_sysctl_table(pm_dir_table); + return 0; +} + +__initcall(pm_init); + +/* + * This is right out of init/main.c + */ + +/* + * This is the number of bits of precision for the loops_per_jiffy. + * Each bit takes on average 1.5/HZ seconds. This (like the original) + * is a little better than 1%. + */ +#define LPS_PREC 8 + +static void au1000_calibrate_delay(void) +{ + unsigned long ticks, loopbit; + int lps_precision = LPS_PREC; + + loops_per_jiffy = 1 << 12; + + while (loops_per_jiffy <<= 1) { + /* Wait for "start of" clock tick */ + ticks = jiffies; + while (ticks == jiffies) + /* nothing */ ; + /* Go ... */ + ticks = jiffies; + __delay(loops_per_jiffy); + ticks = jiffies - ticks; + if (ticks) + break; + } + + /* + * Do a binary approximation to get loops_per_jiffy set to be equal + * one clock (up to lps_precision bits) + */ + loops_per_jiffy >>= 1; + loopbit = loops_per_jiffy; + while (lps_precision-- && (loopbit >>= 1)) { + loops_per_jiffy |= loopbit; + ticks = jiffies; + while (ticks == jiffies); + ticks = jiffies; + __delay(loops_per_jiffy); + if (jiffies != ticks) /* longer than 1 tick */ + loops_per_jiffy &= ~loopbit; + } +} #endif /* CONFIG_PM */ diff --git a/trunk/arch/mips/alchemy/common/reset.c b/trunk/arch/mips/alchemy/common/reset.c index 0191c936cb5e..d555429c8d6f 100644 --- a/trunk/arch/mips/alchemy/common/reset.c +++ b/trunk/arch/mips/alchemy/common/reset.c @@ -31,6 +31,8 @@ #include +extern int au_sleep(void); + void au1000_restart(char *command) { /* Set all integrated peripherals to disabled states */ diff --git a/trunk/arch/mips/alchemy/common/setup.c b/trunk/arch/mips/alchemy/common/setup.c index 3f036b3d400e..1ac6b06f42a3 100644 --- a/trunk/arch/mips/alchemy/common/setup.c +++ b/trunk/arch/mips/alchemy/common/setup.c @@ -35,6 +35,7 @@ #include #include +#include extern void __init board_setup(void); extern void au1000_restart(char *); @@ -44,34 +45,80 @@ extern void set_cpuspec(void); void __init plat_mem_setup(void) { - unsigned long est_freq; + struct cpu_spec *sp; + char *argptr; + unsigned long prid, cpufreq, bclk; - /* determine core clock */ - est_freq = au1xxx_calc_clock(); - est_freq += 5000; /* round */ - est_freq -= est_freq % 10000; - printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), - est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); - - _machine_restart = au1000_restart; - _machine_halt = au1000_halt; - pm_power_off = au1000_power_off; + set_cpuspec(); + sp = cur_cpu_spec[0]; board_setup(); /* board specific setup */ - if (au1xxx_cpu_needs_config_od()) + prid = read_c0_prid(); + if (sp->cpu_pll_wo) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000; +#else + cpufreq = 396; +#endif + else + cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; + printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); + + if (sp->cpu_bclk) { + /* Enable BCLK switching */ + bclk = au_readl(SYS_POWERCTRL); + au_writel(bclk | 0x60, SYS_POWERCTRL); + printk(KERN_INFO "BCLK switching enabled!\n"); + } + + if (sp->cpu_od) /* Various early Au1xx0 errata corrected by this */ set_c0_config(1 << 19); /* Set Config[OD] */ else /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ + argptr = prom_getcmdline(); + +#ifdef CONFIG_SERIAL_8250_CONSOLE + argptr = strstr(argptr, "console="); + if (argptr == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + +#ifdef CONFIG_FB_AU1100 + argptr = strstr(argptr, "video="); + if (argptr == NULL) { + argptr = prom_getcmdline(); + /* default panel */ + /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ + } +#endif + +#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) + /* au1000 does not support vra, au1500 and au1100 do */ + strcat(argptr, " au1000_audio=vra"); + argptr = prom_getcmdline(); +#endif + _machine_restart = au1000_restart; + _machine_halt = au1000_halt; + pm_power_off = au1000_power_off; + /* IO/MEM resources. */ set_io_port_base(0); ioport_resource.start = IOPORT_RESOURCE_START; ioport_resource.end = IOPORT_RESOURCE_END; iomem_resource.start = IOMEM_RESOURCE_START; iomem_resource.end = IOMEM_RESOURCE_END; + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); + au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); + au_writel(0, SYS_TOYTRIM); } #if defined(CONFIG_64BIT_PHYS_ADDR) diff --git a/trunk/arch/mips/alchemy/common/sleeper.S b/trunk/arch/mips/alchemy/common/sleeper.S index 4f4b16741d12..3006e270c8bc 100644 --- a/trunk/arch/mips/alchemy/common/sleeper.S +++ b/trunk/arch/mips/alchemy/common/sleeper.S @@ -15,17 +15,16 @@ #include #include - .extern __flush_cache_all - .text - .set noreorder - .set noat + .set macro + .set noat .align 5 /* Save all of the processor general registers and go to sleep. * A wakeup condition will get us back here to restore the registers. */ -LEAF(au1xxx_save_and_sleep) +LEAF(save_and_sleep) + subu sp, PT_SIZE sw $1, PT_R1(sp) sw $2, PT_R2(sp) @@ -34,6 +33,14 @@ LEAF(au1xxx_save_and_sleep) sw $5, PT_R5(sp) sw $6, PT_R6(sp) sw $7, PT_R7(sp) + sw $8, PT_R8(sp) + sw $9, PT_R9(sp) + sw $10, PT_R10(sp) + sw $11, PT_R11(sp) + sw $12, PT_R12(sp) + sw $13, PT_R13(sp) + sw $14, PT_R14(sp) + sw $15, PT_R15(sp) sw $16, PT_R16(sp) sw $17, PT_R17(sp) sw $18, PT_R18(sp) @@ -42,9 +49,12 @@ LEAF(au1xxx_save_and_sleep) sw $21, PT_R21(sp) sw $22, PT_R22(sp) sw $23, PT_R23(sp) + sw $24, PT_R24(sp) + sw $25, PT_R25(sp) sw $26, PT_R26(sp) sw $27, PT_R27(sp) sw $28, PT_R28(sp) + sw $29, PT_R29(sp) sw $30, PT_R30(sp) sw $31, PT_R31(sp) mfc0 k0, CP0_STATUS @@ -56,26 +66,20 @@ LEAF(au1xxx_save_and_sleep) mfc0 k0, CP0_CONFIG sw k0, 0x14(sp) - /* flush caches to make sure context is in memory */ - la t1, __flush_cache_all - lw t0, 0(t1) - jalr t0 - nop - /* Now set up the scratch registers so the boot rom will * return to this point upon wakeup. - * sys_scratch0 : SP - * sys_scratch1 : RA */ - lui t3, 0xb190 /* sys_xxx */ - sw sp, 0x0018(t3) - la k0, 3f /* resume path */ - sw k0, 0x001c(t3) + la k0, 1f + lui k1, 0xb190 + ori k1, 0x18 + sw sp, 0(k1) + ori k1, 0x1c + sw k0, 0(k1) - /* Put SDRAM into self refresh: Preload instructions into cache, - * issue a precharge, auto/self refresh, then sleep commands to it. - */ - la t0, 1f +/* Put SDRAM into self refresh. Preload instructions into cache, + * issue a precharge, then auto refresh, then sleep commands to it. + */ + la t0, sdsleep .set mips3 cache 0x14, 0(t0) cache 0x14, 32(t0) @@ -83,57 +87,24 @@ LEAF(au1xxx_save_and_sleep) cache 0x14, 96(t0) .set mips0 -1: lui a0, 0xb400 /* mem_xxx */ -#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \ - defined(CONFIG_SOC_AU1500) - sw zero, 0x001c(a0) /* Precharge */ - sync - sw zero, 0x0020(a0) /* Auto Refresh */ - sync - sw zero, 0x0030(a0) /* Sleep */ - sync -#endif - -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - sw zero, 0x08c0(a0) /* Precharge */ +sdsleep: + lui k0, 0xb400 + sw zero, 0x001c(k0) /* Precharge */ + sw zero, 0x0020(k0) /* Auto refresh */ + sw zero, 0x0030(k0) /* SDRAM sleep */ sync - sw zero, 0x08d0(a0) /* Self Refresh */ - sync - - /* wait for sdram to enter self-refresh mode */ - lui t0, 0x0100 -2: lw t1, 0x0850(a0) /* mem_sdstat */ - and t2, t1, t0 - beq t2, zero, 2b - nop - /* disable SDRAM clocks */ - lui t0, 0xcfff - ori t0, t0, 0xffff - lw t1, 0x0840(a0) /* mem_sdconfiga */ - and t1, t0, t1 /* clear CE[1:0] */ - sw t1, 0x0840(a0) /* mem_sdconfiga */ + lui k1, 0xb190 + sw zero, 0x0078(k1) /* get ready to sleep */ sync -#endif - - /* put power supply and processor to sleep */ - sw zero, 0x0078(t3) /* sys_slppwr */ - sync - sw zero, 0x007c(t3) /* sys_sleep */ + sw zero, 0x007c(k1) /* Put processor to sleep */ sync - nop - nop - nop - nop - nop - nop - nop - nop /* This is where we return upon wakeup. * Reload all of the registers and return. */ -3: lw k0, 0x20(sp) +1: nop + lw k0, 0x20(sp) mtc0 k0, CP0_STATUS lw k0, 0x1c(sp) mtc0 k0, CP0_CONTEXT @@ -142,11 +113,10 @@ LEAF(au1xxx_save_and_sleep) lw k0, 0x14(sp) mtc0 k0, CP0_CONFIG - /* We need to catch the early Alchemy SOCs with + /* We need to catch the ealry Alchemy SOCs with * the write-only Config[OD] bit and set it back to one... */ jal au1x00_fixup_config_od - nop lw $1, PT_R1(sp) lw $2, PT_R2(sp) lw $3, PT_R3(sp) @@ -154,6 +124,14 @@ LEAF(au1xxx_save_and_sleep) lw $5, PT_R5(sp) lw $6, PT_R6(sp) lw $7, PT_R7(sp) + lw $8, PT_R8(sp) + lw $9, PT_R9(sp) + lw $10, PT_R10(sp) + lw $11, PT_R11(sp) + lw $12, PT_R12(sp) + lw $13, PT_R13(sp) + lw $14, PT_R14(sp) + lw $15, PT_R15(sp) lw $16, PT_R16(sp) lw $17, PT_R17(sp) lw $18, PT_R18(sp) @@ -162,11 +140,15 @@ LEAF(au1xxx_save_and_sleep) lw $21, PT_R21(sp) lw $22, PT_R22(sp) lw $23, PT_R23(sp) + lw $24, PT_R24(sp) + lw $25, PT_R25(sp) lw $26, PT_R26(sp) lw $27, PT_R27(sp) lw $28, PT_R28(sp) + lw $29, PT_R29(sp) lw $30, PT_R30(sp) lw $31, PT_R31(sp) + addiu sp, PT_SIZE + jr ra - addiu sp, PT_SIZE -END(au1xxx_save_and_sleep) +END(save_and_sleep) diff --git a/trunk/arch/mips/alchemy/common/time.c b/trunk/arch/mips/alchemy/common/time.c index 32880146cbc1..563d9390a872 100644 --- a/trunk/arch/mips/alchemy/common/time.c +++ b/trunk/arch/mips/alchemy/common/time.c @@ -1,7 +1,5 @@ /* - * Copyright (C) 2008 Manuel Lauss * - * Previous incarnations were: * Copyright (C) 2001, 2006, 2008 MontaVista Software, * Copied and modified Carsten Langgaard's time.c * @@ -25,141 +23,244 @@ * * ######################################################################## * - * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the - * databooks). Firmware/Board init code must enable the counters in the - * counter control register, otherwise the CP0 counter clocksource/event - * will be installed instead (and use of 'wait' instruction is prohibited). + * Setting up the clock on the MIPS boards. + * + * We provide the clock interrupt processing and the timer offset compute + * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is + * available. -- Dan */ -#include -#include -#include +#include +#include #include +#include #include #include -/* 32kHz clock enabled and detected */ -#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) - +static int no_au1xxx_32khz; extern int allow_au1k_wait; /* default off for CP0 Counter */ -static cycle_t au1x_counter1_read(void) +#ifdef CONFIG_PM +#if HZ < 100 || HZ > 1000 +#error "unsupported HZ value! Must be in [100,1000]" +#endif +#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */ +static unsigned long last_pc0, last_match20; +#endif + +static DEFINE_SPINLOCK(time_lock); + +unsigned long wtimer; + +#ifdef CONFIG_PM +static irqreturn_t counter0_irq(int irq, void *dev_id) { - return au_readl(SYS_RTCREAD); + unsigned long pc0; + int time_elapsed; + static int jiffie_drift; + + if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { + /* should never happen! */ + printk(KERN_WARNING "counter 0 w status error\n"); + return IRQ_NONE; + } + + pc0 = au_readl(SYS_TOYREAD); + if (pc0 < last_match20) + /* counter overflowed */ + time_elapsed = (0xffffffff - last_match20) + pc0; + else + time_elapsed = pc0 - last_match20; + + while (time_elapsed > 0) { + do_timer(1); +#ifndef CONFIG_SMP + update_process_times(user_mode(get_irq_regs())); +#endif + time_elapsed -= MATCH20_INC; + last_match20 += MATCH20_INC; + jiffie_drift++; + } + + last_pc0 = pc0; + au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); + au_sync(); + + /* + * Our counter ticks at 10.009765625 ms/tick, we we're running + * almost 10 uS too slow per tick. + */ + + if (jiffie_drift >= 999) { + jiffie_drift -= 999; + do_timer(1); /* increment jiffies by one */ +#ifndef CONFIG_SMP + update_process_times(user_mode(get_irq_regs())); +#endif + } + + return IRQ_HANDLED; } -static struct clocksource au1x_counter1_clocksource = { - .name = "alchemy-counter1", - .read = au1x_counter1_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .rating = 100, +struct irqaction counter0_action = { + .handler = counter0_irq, + .flags = IRQF_DISABLED, + .name = "alchemy-toy", + .dev_id = NULL, }; -static int au1x_rtcmatch2_set_next_event(unsigned long delta, - struct clock_event_device *cd) +/* When we wakeup from sleep, we have to "catch up" on all of the + * timer ticks we have missed. + */ +void wakeup_counter0_adjust(void) { - delta += au_readl(SYS_RTCREAD); - /* wait for register access */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) - ; - au_writel(delta, SYS_RTCMATCH2); + unsigned long pc0; + int time_elapsed; + + pc0 = au_readl(SYS_TOYREAD); + if (pc0 < last_match20) + /* counter overflowed */ + time_elapsed = (0xffffffff - last_match20) + pc0; + else + time_elapsed = pc0 - last_match20; + + while (time_elapsed > 0) { + time_elapsed -= MATCH20_INC; + last_match20 += MATCH20_INC; + } + + last_pc0 = pc0; + au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); au_sync(); - return 0; } -static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, - struct clock_event_device *cd) +/* This is just for debugging to set the timer for a sleep delay. */ +void wakeup_counter0_set(int ticks) { + unsigned long pc0; + + pc0 = au_readl(SYS_TOYREAD); + last_pc0 = pc0; + au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2); + au_sync(); } +#endif -static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) +/* + * I haven't found anyone that doesn't use a 12 MHz source clock, + * but just in case..... + */ +#define AU1000_SRC_CLK 12000000 + +/* + * We read the real processor speed from the PLL. This is important + * because it is more accurate than computing it from the 32 KHz + * counter, if it exists. If we don't have an accurate processor + * speed, all of the peripherals that derive their clocks based on + * this advertised speed will introduce error and sometimes not work + * properly. This function is futher convoluted to still allow configurations + * to do that in case they have really, really old silicon with a + * write-only PLL register, that we need the 32 KHz when power management + * "wait" is enabled, and we need to detect if the 32 KHz isn't present + * but requested......got it? :-) -- Dan + */ +unsigned long calc_clock(void) { - struct clock_event_device *cd = dev_id; - cd->event_handler(cd); - return IRQ_HANDLED; -} + unsigned long cpu_speed; + unsigned long flags; + unsigned long counter; -static struct clock_event_device au1x_rtcmatch2_clockdev = { - .name = "rtcmatch2", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 100, - .irq = AU1000_RTC_MATCH2_INT, - .set_next_event = au1x_rtcmatch2_set_next_event, - .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL, -}; + spin_lock_irqsave(&time_lock, flags); -static struct irqaction au1x_rtcmatch2_irqaction = { - .handler = au1x_rtcmatch2_irq, - .flags = IRQF_DISABLED | IRQF_TIMER, - .name = "timer", - .dev_id = &au1x_rtcmatch2_clockdev, -}; + /* Power management cares if we don't have a 32 KHz counter. */ + no_au1xxx_32khz = 0; + counter = au_readl(SYS_COUNTER_CNTRL); + if (counter & SYS_CNTRL_E0) { + int trim_divide = 16; + + au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); + /* RTC now ticks at 32.768/16 kHz */ + au_writel(trim_divide - 1, SYS_RTCTRIM); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + au_writel(0, SYS_TOYWRITE); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + } else + no_au1xxx_32khz = 1; + + /* + * On early Au1000, sys_cpupll was write-only. Since these + * silicon versions of Au1000 are not sold by AMD, we don't bend + * over backwards trying to determine the frequency. + */ + if (cur_cpu_spec[0]->cpu_pll_wo) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; +#else + cpu_speed = 396000000; +#endif + else + cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; + /* On Alchemy CPU:counter ratio is 1:1 */ + mips_hpt_frequency = cpu_speed; + /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ + set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) + & 0x03) + 2) * 16)); + spin_unlock_irqrestore(&time_lock, flags); + return cpu_speed; +} void __init plat_time_init(void) { - struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; - unsigned long t; - - /* Check if firmware (YAMON, ...) has enabled 32kHz and clock - * has been detected. If so install the rtcmatch2 clocksource, - * otherwise don't bother. Note that both bits being set is by - * no means a definite guarantee that the counters actually work - * (the 32S bit seems to be stuck set to 1 once a single clock- - * edge is detected, hence the timeouts). - */ - if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) - goto cntr_err; + unsigned int est_freq = calc_clock(); + + est_freq += 5000; /* round */ + est_freq -= est_freq%10000; + printk(KERN_INFO "CPU frequency %u.%02u MHz\n", + est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); + set_au1x00_speed(est_freq); + set_au1x00_lcd_clock(); /* program the LCD clock */ +#ifdef CONFIG_PM /* - * setup counter 1 (RTC) to tick at full speed + * setup counter 0, since it keeps ticking after a + * 'wait' instruction has been executed. The CP0 timer and + * counter 1 do NOT continue running after 'wait' + * + * It's too early to call request_irq() here, so we handle + * counter 0 interrupt as a special irq and it doesn't show + * up under /proc/interrupts. + * + * Check to ensure we really have a 32 KHz oscillator before + * we do this. */ - t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) - asm volatile ("nop"); - if (!t) - goto cntr_err; + if (no_au1xxx_32khz) + printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); + else { + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); + au_writel(0, SYS_TOYWRITE); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); - au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ - au_sync(); + au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK); + au_writel(~0, SYS_WAKESRC); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) - asm volatile ("nop"); - if (!t) - goto cntr_err; - au_writel(0, SYS_RTCWRITE); - au_sync(); + /* Setup match20 to interrupt once every HZ */ + last_pc0 = last_match20 = au_readl(SYS_TOYREAD); + au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); + setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); + + /* We can use the real 'wait' instruction. */ + allow_au1k_wait = 1; + } - t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) - asm volatile ("nop"); - if (!t) - goto cntr_err; - - /* register counter1 clocksource and event device */ - clocksource_set_clock(&au1x_counter1_clocksource, 32768); - clocksource_register(&au1x_counter1_clocksource); - - cd->shift = 32; - cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); - cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); - cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ - clockevents_register_device(cd); - setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); - - printk(KERN_INFO "Alchemy clocksource installed\n"); - - /* can now use 'wait' */ - allow_au1k_wait = 1; - return; - -cntr_err: - /* counters unusable, use C0 counter */ - r4k_clockevent_init(); - init_r4k_clocksource(); - allow_au1k_wait = 0; +#endif } diff --git a/trunk/arch/mips/alchemy/devboards/db1x00/Makefile b/trunk/arch/mips/alchemy/db1x00/Makefile similarity index 81% rename from trunk/arch/mips/alchemy/devboards/db1x00/Makefile rename to trunk/arch/mips/alchemy/db1x00/Makefile index 432241ab8677..274db3b55d82 100644 --- a/trunk/arch/mips/alchemy/devboards/db1x00/Makefile +++ b/trunk/arch/mips/alchemy/db1x00/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. # -obj-y := board_setup.o irqmap.o +lib-y := init.o board_setup.o irqmap.o diff --git a/trunk/arch/mips/alchemy/devboards/db1x00/board_setup.c b/trunk/arch/mips/alchemy/db1x00/board_setup.c similarity index 80% rename from trunk/arch/mips/alchemy/devboards/db1x00/board_setup.c rename to trunk/arch/mips/alchemy/db1x00/board_setup.c index a75ffbf99f25..9e5ccbbfcedd 100644 --- a/trunk/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/trunk/arch/mips/alchemy/db1x00/board_setup.c @@ -32,20 +32,8 @@ #include #include -#include - - static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; -const char *get_system_type(void) -{ -#ifdef CONFIG_MIPS_BOSPORUS - return "Alchemy Bosporus Gateway Reference"; -#else - return "Alchemy Db1x00"; -#endif -} - void board_reset(void) { /* Hit BCSR.SW_RESET[RESET] */ @@ -55,31 +43,6 @@ void board_reset(void) void __init board_setup(void) { u32 pin_func = 0; - char *argptr; - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - -#ifdef CONFIG_FB_AU1100 - argptr = strstr(argptr, "video="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - /* default panel */ - /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ - } -#endif - -#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) - /* au1000 does not support vra, au1500 and au1100 do */ - strcat(argptr, " au1000_audio=vra"); - argptr = prom_getcmdline(); -#endif /* Not valid for Au1550 */ #if defined(CONFIG_IRDA) && \ diff --git a/trunk/arch/mips/alchemy/db1x00/init.c b/trunk/arch/mips/alchemy/db1x00/init.c new file mode 100644 index 000000000000..847413514964 --- /dev/null +++ b/trunk/arch/mips/alchemy/db1x00/init.c @@ -0,0 +1,62 @@ +/* + * BRIEF MODULE DESCRIPTION + * PB1000 board setup + * + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +#include + +const char *get_system_type(void) +{ +#ifdef CONFIG_MIPS_BOSPORUS + return "Alchemy Bosporus Gateway Reference"; +#else + return "Alchemy Db1x00"; +#endif +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtol(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/trunk/arch/mips/alchemy/devboards/db1x00/irqmap.c b/trunk/arch/mips/alchemy/db1x00/irqmap.c similarity index 77% rename from trunk/arch/mips/alchemy/devboards/db1x00/irqmap.c rename to trunk/arch/mips/alchemy/db1x00/irqmap.c index 0b09025087c6..94c090e8bf7a 100644 --- a/trunk/arch/mips/alchemy/devboards/db1x00/irqmap.c +++ b/trunk/arch/mips/alchemy/db1x00/irqmap.c @@ -27,7 +27,6 @@ */ #include -#include #include @@ -67,24 +66,21 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { #ifndef CONFIG_MIPS_MIRAGE #ifdef CONFIG_MIPS_DB1550 - { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */ - { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */ + { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ + { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ #else - { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */ - { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */ - { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */ + { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 Fully_Interted# */ + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 STSCHG# */ + { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ - { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */ - { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */ - { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */ + { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 Fully_Interted# */ + { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 STSCHG# */ + { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ #endif #else - { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */ + { AU1000_GPIO_7, INTC_INT_RISE_EDGE, 0 }, /* touchscreen pen down */ #endif }; -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/devboards/Makefile b/trunk/arch/mips/alchemy/devboards/Makefile deleted file mode 100644 index 730f9f2b30e8..000000000000 --- a/trunk/arch/mips/alchemy/devboards/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Alchemy Develboards -# - -obj-y += prom.o -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_MIPS_PB1000) += pb1000/ -obj-$(CONFIG_MIPS_PB1100) += pb1100/ -obj-$(CONFIG_MIPS_PB1200) += pb1200/ -obj-$(CONFIG_MIPS_PB1500) += pb1500/ -obj-$(CONFIG_MIPS_PB1550) += pb1550/ -obj-$(CONFIG_MIPS_DB1000) += db1x00/ -obj-$(CONFIG_MIPS_DB1100) += db1x00/ -obj-$(CONFIG_MIPS_DB1200) += pb1200/ -obj-$(CONFIG_MIPS_DB1500) += db1x00/ -obj-$(CONFIG_MIPS_DB1550) += db1x00/ -obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ -obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ diff --git a/trunk/arch/mips/alchemy/devboards/pm.c b/trunk/arch/mips/alchemy/devboards/pm.c deleted file mode 100644 index d5eb9c325ed0..000000000000 --- a/trunk/arch/mips/alchemy/devboards/pm.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Alchemy Development Board example suspend userspace interface. - * - * (c) 2008 Manuel Lauss - */ - -#include -#include -#include -#include -#include - -/* - * Generic suspend userspace interface for Alchemy development boards. - * This code exports a few sysfs nodes under /sys/power/db1x/ which - * can be used by userspace to en/disable all au1x-provided wakeup - * sources and configure the timeout after which the the TOYMATCH2 irq - * is to trigger a wakeup. - */ - - -static unsigned long db1x_pm_sleep_secs; -static unsigned long db1x_pm_wakemsk; -static unsigned long db1x_pm_last_wakesrc; - -static int db1x_pm_enter(suspend_state_t state) -{ - /* enable GPIO based wakeup */ - au_writel(1, SYS_PININPUTEN); - - /* clear and setup wake cause and source */ - au_writel(0, SYS_WAKEMSK); - au_sync(); - au_writel(0, SYS_WAKESRC); - au_sync(); - - au_writel(db1x_pm_wakemsk, SYS_WAKEMSK); - au_sync(); - - /* setup 1Hz-timer-based wakeup: wait for reg access */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) - asm volatile ("nop"); - - au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2); - au_sync(); - - /* wait for value to really hit the register */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) - asm volatile ("nop"); - - /* ...and now the sandman can come! */ - au_sleep(); - - return 0; -} - -static int db1x_pm_begin(suspend_state_t state) -{ - if (!db1x_pm_wakemsk) { - printk(KERN_ERR "db1x: no wakeup source activated!\n"); - return -EINVAL; - } - - return 0; -} - -static void db1x_pm_end(void) -{ - /* read and store wakeup source, the clear the register. To - * be able to clear it, WAKEMSK must be cleared first. - */ - db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); - - au_writel(0, SYS_WAKEMSK); - au_writel(0, SYS_WAKESRC); - au_sync(); - -} - -static struct platform_suspend_ops db1x_pm_ops = { - .valid = suspend_valid_only_mem, - .begin = db1x_pm_begin, - .enter = db1x_pm_enter, - .end = db1x_pm_end, -}; - -#define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x)) - -static ssize_t db1x_pmattr_show(struct kobject *kobj, - struct kobj_attribute *attr, - char *buf) -{ - int idx; - - if (ATTRCMP(timer_timeout)) - return sprintf(buf, "%lu\n", db1x_pm_sleep_secs); - - else if (ATTRCMP(timer)) - return sprintf(buf, "%u\n", - !!(db1x_pm_wakemsk & SYS_WAKEMSK_M2)); - - else if (ATTRCMP(wakesrc)) - return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc); - - else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || - ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || - ATTRCMP(gpio6) || ATTRCMP(gpio7)) { - idx = (attr->attr.name)[4] - '0'; - return sprintf(buf, "%d\n", - !!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx))); - - } else if (ATTRCMP(wakemsk)) { - return sprintf(buf, "%08lx\n", db1x_pm_wakemsk); - } - - return -ENOENT; -} - -static ssize_t db1x_pmattr_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *instr, - size_t bytes) -{ - unsigned long l; - int tmp; - - if (ATTRCMP(timer_timeout)) { - tmp = strict_strtoul(instr, 0, &l); - if (tmp) - return tmp; - - db1x_pm_sleep_secs = l; - - } else if (ATTRCMP(timer)) { - if (instr[0] != '0') - db1x_pm_wakemsk |= SYS_WAKEMSK_M2; - else - db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2; - - } else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || - ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || - ATTRCMP(gpio6) || ATTRCMP(gpio7)) { - tmp = (attr->attr.name)[4] - '0'; - if (instr[0] != '0') { - db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp); - } else { - db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp); - } - - } else if (ATTRCMP(wakemsk)) { - tmp = strict_strtoul(instr, 0, &l); - if (tmp) - return tmp; - - db1x_pm_wakemsk = l & 0x0000003f; - - } else - bytes = -ENOENT; - - return bytes; -} - -#define ATTR(x) \ - static struct kobj_attribute x##_attribute = \ - __ATTR(x, 0664, db1x_pmattr_show, \ - db1x_pmattr_store); - -ATTR(gpio0) /* GPIO-based wakeup enable */ -ATTR(gpio1) -ATTR(gpio2) -ATTR(gpio3) -ATTR(gpio4) -ATTR(gpio5) -ATTR(gpio6) -ATTR(gpio7) -ATTR(timer) /* TOYMATCH2-based wakeup enable */ -ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */ -ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */ -ATTR(wakemsk) /* direct access to SYS_WAKEMSK */ - -#define ATTR_LIST(x) & x ## _attribute.attr -static struct attribute *db1x_pmattrs[] = { - ATTR_LIST(gpio0), - ATTR_LIST(gpio1), - ATTR_LIST(gpio2), - ATTR_LIST(gpio3), - ATTR_LIST(gpio4), - ATTR_LIST(gpio5), - ATTR_LIST(gpio6), - ATTR_LIST(gpio7), - ATTR_LIST(timer), - ATTR_LIST(timer_timeout), - ATTR_LIST(wakesrc), - ATTR_LIST(wakemsk), - NULL, /* terminator */ -}; - -static struct attribute_group db1x_pmattr_group = { - .name = "db1x", - .attrs = db1x_pmattrs, -}; - -/* - * Initialize suspend interface - */ -static int __init pm_init(void) -{ - /* init TOY to tick at 1Hz if not already done. No need to wait - * for confirmation since there's plenty of time from here to - * the next suspend cycle. - */ - if (au_readl(SYS_TOYTRIM) != 32767) { - au_writel(32767, SYS_TOYTRIM); - au_sync(); - } - - db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); - - au_writel(0, SYS_WAKESRC); - au_sync(); - au_writel(0, SYS_WAKEMSK); - au_sync(); - - suspend_set_ops(&db1x_pm_ops); - - return sysfs_create_group(power_kobj, &db1x_pmattr_group); -} - -late_initcall(pm_init); diff --git a/trunk/arch/mips/alchemy/mtx-1/board_setup.c b/trunk/arch/mips/alchemy/mtx-1/board_setup.c index 8ed1ae12bc55..3f8079186cf2 100644 --- a/trunk/arch/mips/alchemy/mtx-1/board_setup.c +++ b/trunk/arch/mips/alchemy/mtx-1/board_setup.c @@ -32,8 +32,6 @@ #include -#include - extern int (*board_pci_idsel)(unsigned int devsel, int assert); int mtx1_pci_idsel(unsigned int devsel, int assert); @@ -45,16 +43,6 @@ void board_reset(void) void __init board_setup(void) { -#ifdef CONFIG_SERIAL_8250_CONSOLE - char *argptr; - argptr = prom_getcmdline(); - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Enable USB power switch */ au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); diff --git a/trunk/arch/mips/alchemy/mtx-1/init.c b/trunk/arch/mips/alchemy/mtx-1/init.c index 5e871c8d9e96..3bae13c28954 100644 --- a/trunk/arch/mips/alchemy/mtx-1/init.c +++ b/trunk/arch/mips/alchemy/mtx-1/init.c @@ -55,6 +55,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtoul(memsize_str, 0, &memsize); + strict_strtol(memsize_str, 0, &memsize); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/alchemy/mtx-1/irqmap.c b/trunk/arch/mips/alchemy/mtx-1/irqmap.c index f1ab12ab3433..f2bf02951e9c 100644 --- a/trunk/arch/mips/alchemy/mtx-1/irqmap.c +++ b/trunk/arch/mips/alchemy/mtx-1/irqmap.c @@ -27,7 +27,7 @@ */ #include -#include + #include char irq_tab_alchemy[][5] __initdata = { @@ -42,15 +42,11 @@ char irq_tab_alchemy[][5] __initdata = { }; struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, - { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, + { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, + { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, }; - -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/devboards/pb1000/Makefile b/trunk/arch/mips/alchemy/pb1000/Makefile similarity index 81% rename from trunk/arch/mips/alchemy/devboards/pb1000/Makefile rename to trunk/arch/mips/alchemy/pb1000/Makefile index 97c6615ba2bb..99bbec0ca41b 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1000/Makefile +++ b/trunk/arch/mips/alchemy/pb1000/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1000 board. # -obj-y := board_setup.o +lib-y := init.o board_setup.o irqmap.o diff --git a/trunk/arch/mips/alchemy/devboards/pb1000/board_setup.c b/trunk/arch/mips/alchemy/pb1000/board_setup.c similarity index 90% rename from trunk/arch/mips/alchemy/devboards/pb1000/board_setup.c rename to trunk/arch/mips/alchemy/pb1000/board_setup.c index aed2fdecc709..25df167a95b3 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/trunk/arch/mips/alchemy/pb1000/board_setup.c @@ -23,48 +23,22 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include -#include +#include + #include #include -#include - - -struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 }, -}; - - -const char *get_system_type(void) -{ - return "Alchemy Pb1000"; -} void board_reset(void) { } -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} - void __init board_setup(void) { u32 pin_func, static_cfg0; u32 sys_freqctrl, sys_clksrc; u32 prid = read_c0_prid(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - char *argptr = prom_getcmdline(); - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); au_writel(0, SYS_PINSTATERD); diff --git a/trunk/arch/mips/alchemy/pb1000/init.c b/trunk/arch/mips/alchemy/pb1000/init.c new file mode 100644 index 000000000000..8a9c7d57208d --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1000/init.c @@ -0,0 +1,57 @@ +/* + * BRIEF MODULE DESCRIPTION + * Pb1000 board setup + * + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +#include + +const char *get_system_type(void) +{ + return "Alchemy Pb1000"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int)fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtol(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/trunk/arch/mips/alchemy/pb1000/irqmap.c b/trunk/arch/mips/alchemy/pb1000/irqmap.c new file mode 100644 index 000000000000..b3d56b0af321 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1000/irqmap.c @@ -0,0 +1,38 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx irq map table + * + * Copyright 2003 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { + { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 }, +}; + +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/devboards/pb1100/Makefile b/trunk/arch/mips/alchemy/pb1100/Makefile similarity index 81% rename from trunk/arch/mips/alchemy/devboards/pb1100/Makefile rename to trunk/arch/mips/alchemy/pb1100/Makefile index c586dd7e91dc..793e97c49e46 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1100/Makefile +++ b/trunk/arch/mips/alchemy/pb1100/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1100 board. # -obj-y := board_setup.o +lib-y := init.o board_setup.o irqmap.o diff --git a/trunk/arch/mips/alchemy/devboards/pb1100/board_setup.c b/trunk/arch/mips/alchemy/pb1100/board_setup.c similarity index 76% rename from trunk/arch/mips/alchemy/devboards/pb1100/board_setup.c rename to trunk/arch/mips/alchemy/pb1100/board_setup.c index 4df57fae15d4..c0bfd59a7a36 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/trunk/arch/mips/alchemy/pb1100/board_setup.c @@ -25,66 +25,19 @@ #include #include -#include #include #include -#include - - -struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1000_GPIO_9, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */ - { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */ - { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */ - { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */ -}; - - -const char *get_system_type(void) -{ - return "Alchemy Pb1100"; -} - void board_reset(void) { /* Hit BCSR.RST_VDDI[SOFT_RESET] */ au_writel(0x00000000, PB1100_RST_VDDI); } -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} - void __init board_setup(void) { volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; - char *argptr; - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - -#ifdef CONFIG_FB_AU1100 - argptr = strstr(argptr, "video="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - /* default panel */ - /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ - } -#endif - -#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) - /* au1000 does not support vra, au1500 and au1100 do */ - strcat(argptr, " au1000_audio=vra"); - argptr = prom_getcmdline(); -#endif /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); diff --git a/trunk/arch/mips/alchemy/pb1100/init.c b/trunk/arch/mips/alchemy/pb1100/init.c new file mode 100644 index 000000000000..7c6792308bc5 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1100/init.c @@ -0,0 +1,60 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Pb1100 board setup + * + * Copyright 2002, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +#include + +const char *get_system_type(void) +{ + return "Alchemy Pb1100"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg3; + + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtol(memsize_str, 0, &memsize); + + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/trunk/arch/mips/alchemy/pb1100/irqmap.c b/trunk/arch/mips/alchemy/pb1100/irqmap.c new file mode 100644 index 000000000000..9b7dd8b41283 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1100/irqmap.c @@ -0,0 +1,40 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xx0 IRQ map table + * + * Copyright 2003 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include + +struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { + { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */ + { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */ + { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */ + { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */ +}; + +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/devboards/pb1200/Makefile b/trunk/arch/mips/alchemy/pb1200/Makefile similarity index 61% rename from trunk/arch/mips/alchemy/devboards/pb1200/Makefile rename to trunk/arch/mips/alchemy/pb1200/Makefile index c8c3a99fb68a..d678adf7ce85 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1200/Makefile +++ b/trunk/arch/mips/alchemy/pb1200/Makefile @@ -2,6 +2,7 @@ # Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. # -obj-y := board_setup.o irqmap.o platform.o +lib-y := init.o board_setup.o irqmap.o +obj-y += platform.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/alchemy/devboards/pb1200/board_setup.c b/trunk/arch/mips/alchemy/pb1200/board_setup.c similarity index 93% rename from trunk/arch/mips/alchemy/devboards/pb1200/board_setup.c rename to trunk/arch/mips/alchemy/pb1200/board_setup.c index 94e6b7e7753d..6cb2115059ad 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/trunk/arch/mips/alchemy/pb1200/board_setup.c @@ -30,11 +30,8 @@ #include #include - -const char *get_system_type(void) -{ - return "Alchemy Pb1200"; -} +extern void _board_init_irq(void); +extern void (*board_init_irq)(void); void board_reset(void) { @@ -44,19 +41,7 @@ void board_reset(void) void __init board_setup(void) { - char *argptr; - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif -#ifdef CONFIG_FB_AU1200 - strcat(argptr, " video=au1200fb:panel:bs"); -#endif + char *argptr = NULL; #if 0 { @@ -114,6 +99,16 @@ void __init board_setup(void) } #endif +#ifdef CONFIG_FB_AU1200 + argptr = prom_getcmdline(); +#ifdef CONFIG_MIPS_PB1200 + strcat(argptr, " video=au1200fb:panel:bs"); +#endif +#ifdef CONFIG_MIPS_DB1200 + strcat(argptr, " video=au1200fb:panel:bs"); +#endif +#endif + /* * The Pb1200 development board uses external MUX for PSC0 to * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI @@ -129,6 +124,9 @@ void __init board_setup(void) #ifdef CONFIG_MIPS_DB1200 printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); #endif + + /* Setup Pb1200 External Interrupt Controller */ + board_init_irq = _board_init_irq; } int board_au1200fb_panel(void) diff --git a/trunk/arch/mips/alchemy/devboards/prom.c b/trunk/arch/mips/alchemy/pb1200/init.c similarity index 71% rename from trunk/arch/mips/alchemy/devboards/prom.c rename to trunk/arch/mips/alchemy/pb1200/init.c index 0042bd6b1d7d..e9b2a0fd48ae 100644 --- a/trunk/arch/mips/alchemy/devboards/prom.c +++ b/trunk/arch/mips/alchemy/pb1200/init.c @@ -1,9 +1,9 @@ /* - * Common code used by all Alchemy develboards. * - * Extracted from files which had this to say: + * BRIEF MODULE DESCRIPTION + * PB1200 board setup * - * Copyright 2000, 2008 MontaVista Software Inc. + * Copyright 2001, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify it @@ -29,19 +29,15 @@ #include #include + #include -#include -#include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \ - defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE) -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 +#include -#else /* Au1550/Au1200-based develboards */ -#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000 -#endif +const char *get_system_type(void) +{ + return "Alchemy Pb1200"; +} void __init prom_init(void) { @@ -55,8 +51,8 @@ void __init prom_init(void) prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) - memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE; + memsize = 0x08000000; else - strict_strtoul(memsize_str, 0, &memsize); + strict_strtol(memsize_str, 0, &memsize); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/alchemy/devboards/pb1200/irqmap.c b/trunk/arch/mips/alchemy/pb1200/irqmap.c similarity index 64% rename from trunk/arch/mips/alchemy/devboards/pb1200/irqmap.c rename to trunk/arch/mips/alchemy/pb1200/irqmap.c index fe47498da280..2a505ad8715b 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1200/irqmap.c +++ b/trunk/arch/mips/alchemy/pb1200/irqmap.c @@ -40,65 +40,91 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { /* This is external interrupt cascade */ - { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 }, + { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, }; +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); /* * Support for External interrupts on the Pb1200 Development platform. */ +static volatile int pb1200_cascade_en; -static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d) +irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) { unsigned short bisr = bcsr->int_status; + int extirq_nr = 0; + + /* Clear all the edge interrupts. This has no effect on level. */ + bcsr->int_status = bisr; + for ( ; bisr; bisr &= bisr - 1) { + extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); + /* Ack and dispatch IRQ */ + do_IRQ(extirq_nr); + } - for ( ; bisr; bisr &= bisr - 1) - generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); + return IRQ_RETVAL(1); } -/* NOTE: both the enable and mask bits must be cleared, otherwise the - * CPLD generates tons of spurious interrupts (at least on the DB1200). - */ -static void pb1200_mask_irq(unsigned int irq_nr) +inline void pb1200_enable_irq(unsigned int irq_nr) { - bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); - au_sync(); + bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); + bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); } -static void pb1200_maskack_irq(unsigned int irq_nr) +inline void pb1200_disable_irq(unsigned int irq_nr) { bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ - au_sync(); } -static void pb1200_unmask_irq(unsigned int irq_nr) +static unsigned int pb1200_setup_cascade(void) { - bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); - bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); - au_sync(); + return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, + 0, "Pb1200 Cascade", &pb1200_cascade_handler); +} + +static unsigned int pb1200_startup_irq(unsigned int irq) +{ + if (++pb1200_cascade_en == 1) { + int res; + + res = pb1200_setup_cascade(); + if (res) + return res; + } + + pb1200_enable_irq(irq); + + return 0; } -static struct irq_chip pb1200_cpld_irq_type = { +static void pb1200_shutdown_irq(unsigned int irq) +{ + pb1200_disable_irq(irq); + if (--pb1200_cascade_en == 0) + free_irq(AU1000_GPIO_7, &pb1200_cascade_handler); +} + +static struct irq_chip external_irq_type = { #ifdef CONFIG_MIPS_PB1200 .name = "Pb1200 Ext", #endif #ifdef CONFIG_MIPS_DB1200 .name = "Db1200 Ext", #endif - .mask = pb1200_mask_irq, - .mask_ack = pb1200_maskack_irq, - .unmask = pb1200_unmask_irq, + .startup = pb1200_startup_irq, + .shutdown = pb1200_shutdown_irq, + .ack = pb1200_disable_irq, + .mask = pb1200_disable_irq, + .mask_ack = pb1200_disable_irq, + .unmask = pb1200_enable_irq, }; -void __init board_init_irq(void) +void _board_init_irq(void) { unsigned int irq; - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); - #ifdef CONFIG_MIPS_PB1200 /* We have a problem with CPLD rev 3. */ if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { @@ -120,15 +146,15 @@ void __init board_init_irq(void) panic("Game over. Your score is 0."); } #endif - /* mask & disable & ack all */ - bcsr->intclr_mask = 0xffff; - bcsr->intclr = 0xffff; - bcsr->int_status = 0xffff; - au_sync(); - for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) - set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type, - handle_level_irq, "level"); + for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { + set_irq_chip_and_handler(irq, &external_irq_type, + handle_level_irq); + pb1200_disable_irq(irq); + } - set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler); + /* + * GPIO_7 can not be hooked here, so it is hooked upon first + * request of any source attached to the cascade. + */ } diff --git a/trunk/arch/mips/alchemy/devboards/pb1200/platform.c b/trunk/arch/mips/alchemy/pb1200/platform.c similarity index 100% rename from trunk/arch/mips/alchemy/devboards/pb1200/platform.c rename to trunk/arch/mips/alchemy/pb1200/platform.c diff --git a/trunk/arch/mips/alchemy/devboards/pb1500/Makefile b/trunk/arch/mips/alchemy/pb1500/Makefile similarity index 81% rename from trunk/arch/mips/alchemy/devboards/pb1500/Makefile rename to trunk/arch/mips/alchemy/pb1500/Makefile index 173b419a7479..602f38df20bb 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1500/Makefile +++ b/trunk/arch/mips/alchemy/pb1500/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1500 board. # -obj-y := board_setup.o +lib-y := init.o board_setup.o irqmap.o diff --git a/trunk/arch/mips/alchemy/devboards/pb1500/board_setup.c b/trunk/arch/mips/alchemy/pb1500/board_setup.c similarity index 79% rename from trunk/arch/mips/alchemy/devboards/pb1500/board_setup.c rename to trunk/arch/mips/alchemy/pb1500/board_setup.c index fed3b093156a..035771c6e5b8 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/trunk/arch/mips/alchemy/pb1500/board_setup.c @@ -25,64 +25,20 @@ #include #include -#include #include #include -#include - - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ -}; - -struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, - { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, -}; - - -const char *get_system_type(void) -{ - return "Alchemy Pb1500"; -} - void board_reset(void) { /* Hit BCSR.RST_VDDI[SOFT_RESET] */ au_writel(0x00000000, PB1500_RST_VDDI); } -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} - void __init board_setup(void) { u32 pin_func; u32 sys_freqctrl, sys_clksrc; - char *argptr; - - argptr = prom_getcmdline(); -#ifdef CONFIG_SERIAL_8250_CONSOLE - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - -#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) - /* au1000 does not support vra, au1500 and au1100 do */ - strcat(argptr, " au1000_audio=vra"); - argptr = prom_getcmdline(); -#endif sys_clksrc = sys_freqctrl = pin_func = 0; /* Set AUX clock to 12 MHz * 8 = 96 MHz */ diff --git a/trunk/arch/mips/alchemy/pb1500/init.c b/trunk/arch/mips/alchemy/pb1500/init.c new file mode 100644 index 000000000000..3b6e395cf952 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1500/init.c @@ -0,0 +1,58 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Pb1500 board setup + * + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +#include + +const char *get_system_type(void) +{ + return "Alchemy Pb1500"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int)fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtol(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/trunk/arch/mips/alchemy/pb1500/irqmap.c b/trunk/arch/mips/alchemy/pb1500/irqmap.c new file mode 100644 index 000000000000..39c4682766a8 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1500/irqmap.c @@ -0,0 +1,46 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xxx irq map table + * + * Copyright 2003 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include + +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ + [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ +}; + +struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { + { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, + { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, +}; + +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/devboards/pb1550/Makefile b/trunk/arch/mips/alchemy/pb1550/Makefile similarity index 81% rename from trunk/arch/mips/alchemy/devboards/pb1550/Makefile rename to trunk/arch/mips/alchemy/pb1550/Makefile index cff95bcdb2ca..7d8beca87fa5 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1550/Makefile +++ b/trunk/arch/mips/alchemy/pb1550/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1550 board. # -obj-y := board_setup.o +lib-y := init.o board_setup.o irqmap.o diff --git a/trunk/arch/mips/alchemy/devboards/pb1550/board_setup.c b/trunk/arch/mips/alchemy/pb1550/board_setup.c similarity index 72% rename from trunk/arch/mips/alchemy/devboards/pb1550/board_setup.c rename to trunk/arch/mips/alchemy/pb1550/board_setup.c index b6e9e7d247a3..0ed76b64b6ab 100644 --- a/trunk/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/trunk/arch/mips/alchemy/pb1550/board_setup.c @@ -28,54 +28,20 @@ */ #include -#include #include #include -#include - - -char irq_tab_alchemy[][5] __initdata = { - [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */ - [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */ -}; - -struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, - { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, -}; - -const char *get_system_type(void) -{ - return "Alchemy Pb1550"; -} - void board_reset(void) { /* Hit BCSR.SYSTEM[RESET] */ au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); } -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} - void __init board_setup(void) { u32 pin_func; -#ifdef CONFIG_SERIAL_8250_CONSOLE - char *argptr; - argptr = prom_getcmdline(); - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - /* * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, * but it is board specific code, so put it here. diff --git a/trunk/arch/mips/alchemy/pb1550/init.c b/trunk/arch/mips/alchemy/pb1550/init.c new file mode 100644 index 000000000000..e1055a13a1a0 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1550/init.c @@ -0,0 +1,58 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Pb1550 board setup + * + * Copyright 2001, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#include + +#include + +const char *get_system_type(void) +{ + return "Alchemy Pb1550"; +} + +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int)fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) + memsize = 0x08000000; + else + strict_strtol(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/trunk/arch/mips/alchemy/pb1550/irqmap.c b/trunk/arch/mips/alchemy/pb1550/irqmap.c new file mode 100644 index 000000000000..a02a4d1fa899 --- /dev/null +++ b/trunk/arch/mips/alchemy/pb1550/irqmap.c @@ -0,0 +1,43 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1xx0 IRQ map table + * + * Copyright 2003 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +#include + +char irq_tab_alchemy[][5] __initdata = { + [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */ + [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */ +}; + +struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { + { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, +}; + +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/alchemy/xxs1500/board_setup.c b/trunk/arch/mips/alchemy/xxs1500/board_setup.c index a2634fabc50d..4c587acac5c3 100644 --- a/trunk/arch/mips/alchemy/xxs1500/board_setup.c +++ b/trunk/arch/mips/alchemy/xxs1500/board_setup.c @@ -28,8 +28,6 @@ #include -#include - void board_reset(void) { /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ @@ -40,16 +38,6 @@ void __init board_setup(void) { u32 pin_func; -#ifdef CONFIG_SERIAL_8250_CONSOLE - char *argptr; - argptr = prom_getcmdline(); - argptr = strstr(argptr, "console="); - if (argptr == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " console=ttyS0,115200"); - } -#endif - /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; pin_func |= SYS_PF_UR3; diff --git a/trunk/arch/mips/alchemy/xxs1500/init.c b/trunk/arch/mips/alchemy/xxs1500/init.c index 456fa142c093..7516434760a1 100644 --- a/trunk/arch/mips/alchemy/xxs1500/init.c +++ b/trunk/arch/mips/alchemy/xxs1500/init.c @@ -53,6 +53,6 @@ void __init prom_init(void) if (!memsize_str) memsize = 0x04000000; else - strict_strtoul(memsize_str, 0, &memsize); + strict_strtol(memsize_str, 0, &memsize); add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/alchemy/xxs1500/irqmap.c b/trunk/arch/mips/alchemy/xxs1500/irqmap.c index 0f0f3012e5fd..edf06ed11870 100644 --- a/trunk/arch/mips/alchemy/xxs1500/irqmap.c +++ b/trunk/arch/mips/alchemy/xxs1500/irqmap.c @@ -27,26 +27,23 @@ */ #include -#include + #include struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { - { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 }, - { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 }, - { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 }, + { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, + { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, + { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, - { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, - { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, - { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, - { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */ - { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, + { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ + { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, }; -void __init board_init_irq(void) -{ - au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -} +int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); diff --git a/trunk/arch/mips/cavium-octeon/Kconfig b/trunk/arch/mips/cavium-octeon/Kconfig deleted file mode 100644 index 094c17e38e16..000000000000 --- a/trunk/arch/mips/cavium-octeon/Kconfig +++ /dev/null @@ -1,85 +0,0 @@ -config CAVIUM_OCTEON_SPECIFIC_OPTIONS - bool "Enable Octeon specific options" - depends on CPU_CAVIUM_OCTEON - default "y" - -config CAVIUM_OCTEON_2ND_KERNEL - bool "Build the kernel to be used as a 2nd kernel on the same chip" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS - default "n" - help - This option configures this kernel to be linked at a different - address and use the 2nd uart for output. This allows a kernel built - with this option to be run at the same time as one built without this - option. - -config CAVIUM_OCTEON_HW_FIX_UNALIGNED - bool "Enable hardware fixups of unaligned loads and stores" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS - default "y" - help - Configure the Octeon hardware to automatically fix unaligned loads - and stores. Normally unaligned accesses are fixed using a kernel - exception handler. This option enables the hardware automatic fixups, - which requires only an extra 3 cycles. Disable this option if you - are running code that relies on address exceptions on unaligned - accesses. - -config CAVIUM_OCTEON_CVMSEG_SIZE - int "Number of L1 cache lines reserved for CVMSEG memory" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS - range 0 54 - default 1 - help - CVMSEG LM is a segment that accesses portions of the dcache as a - local memory; the larger CVMSEG is, the smaller the cache is. - This selects the size of CVMSEG LM, which is in cache blocks. The - legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is - between zero and 6192 bytes). - -config CAVIUM_OCTEON_LOCK_L2 - bool "Lock often used kernel code in the L2" - depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS - default "y" - help - Enable locking parts of the kernel into the L2 cache. - -config CAVIUM_OCTEON_LOCK_L2_TLB - bool "Lock the TLB handler in L2" - depends on CAVIUM_OCTEON_LOCK_L2 - default "y" - help - Lock the low level TLB fast path into L2. - -config CAVIUM_OCTEON_LOCK_L2_EXCEPTION - bool "Lock the exception handler in L2" - depends on CAVIUM_OCTEON_LOCK_L2 - default "y" - help - Lock the low level exception handler into L2. - -config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT - bool "Lock the interrupt handler in L2" - depends on CAVIUM_OCTEON_LOCK_L2 - default "y" - help - Lock the low level interrupt handler into L2. - -config CAVIUM_OCTEON_LOCK_L2_INTERRUPT - bool "Lock the 2nd level interrupt handler in L2" - depends on CAVIUM_OCTEON_LOCK_L2 - default "y" - help - Lock the 2nd level interrupt handler in L2. - -config CAVIUM_OCTEON_LOCK_L2_MEMCPY - bool "Lock memcpy() in L2" - depends on CAVIUM_OCTEON_LOCK_L2 - default "y" - help - Lock the kernel's implementation of memcpy() into L2. - -config ARCH_SPARSEMEM_ENABLE - def_bool y - select SPARSEMEM_STATIC - depends on CPU_CAVIUM_OCTEON diff --git a/trunk/arch/mips/cavium-octeon/Makefile b/trunk/arch/mips/cavium-octeon/Makefile deleted file mode 100644 index 1c2a7faf5881..000000000000 --- a/trunk/arch/mips/cavium-octeon/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Makefile for the Cavium Octeon specific kernel interface routines -# under Linux. -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 2005-2008 Cavium Networks -# - -obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o -obj-y += dma-octeon.o flash_setup.o -obj-y += octeon-memcpy.o - -obj-$(CONFIG_SMP) += smp.o diff --git a/trunk/arch/mips/cavium-octeon/csrc-octeon.c b/trunk/arch/mips/cavium-octeon/csrc-octeon.c deleted file mode 100644 index 70fd92c31657..000000000000 --- a/trunk/arch/mips/cavium-octeon/csrc-octeon.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 by Ralf Baechle - */ -#include -#include - -#include - -#include -#include - -/* - * Set the current core's cvmcount counter to the value of the - * IPD_CLK_COUNT. We do this on all cores as they are brought - * on-line. This allows for a read from a local cpu register to - * access a synchronized counter. - * - */ -void octeon_init_cvmcount(void) -{ - unsigned long flags; - unsigned loops = 2; - - /* Clobber loops so GCC will not unroll the following while loop. */ - asm("" : "+r" (loops)); - - local_irq_save(flags); - /* - * Loop several times so we are executing from the cache, - * which should give more deterministic timing. - */ - while (loops--) - write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT)); - local_irq_restore(flags); -} - -static cycle_t octeon_cvmcount_read(void) -{ - return read_c0_cvmcount(); -} - -static struct clocksource clocksource_mips = { - .name = "OCTEON_CVMCOUNT", - .read = octeon_cvmcount_read, - .mask = CLOCKSOURCE_MASK(64), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -void __init plat_time_init(void) -{ - clocksource_mips.rating = 300; - clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); - clocksource_register(&clocksource_mips); -} diff --git a/trunk/arch/mips/cavium-octeon/dma-octeon.c b/trunk/arch/mips/cavium-octeon/dma-octeon.c deleted file mode 100644 index 01b1ef94b361..000000000000 --- a/trunk/arch/mips/cavium-octeon/dma-octeon.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Ani Joshi - * Copyright (C) 2000, 2001 Ralf Baechle - * Copyright (C) 2005 Ilya A. Volynets-Evenbakh - * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. - * IP32 changes by Ilya. - * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on - * the kernels original. - */ -#include -#include - -#include - -dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) -{ - /* Without PCI/PCIe this function can be called for Octeon internal - devices such as USB. These devices all support 64bit addressing */ - mb(); - return virt_to_phys(ptr); -} - -void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) -{ - /* Without PCI/PCIe this function can be called for Octeon internal - * devices such as USB. These devices all support 64bit addressing */ - return; -} diff --git a/trunk/arch/mips/cavium-octeon/executive/Makefile b/trunk/arch/mips/cavium-octeon/executive/Makefile deleted file mode 100644 index 80d6cb26766b..000000000000 --- a/trunk/arch/mips/cavium-octeon/executive/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for the Cavium Octeon specific kernel interface routines -# under Linux. -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. -# -# Copyright (C) 2005-2008 Cavium Networks -# - -obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o - diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-bootmem.c deleted file mode 100644 index 4f5a08b37ccd..000000000000 --- a/trunk/arch/mips/cavium-octeon/executive/cvmx-bootmem.c +++ /dev/null @@ -1,586 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Simple allocate only memory allocator. Used to allocate memory at - * application start time. - */ - -#include - -#include -#include -#include - -/*#define DEBUG */ - - -static struct cvmx_bootmem_desc *cvmx_bootmem_desc; - -/* See header file for descriptions of functions */ - -/* - * Wrapper functions are provided for reading/writing the size and - * next block values as these may not be directly addressible (in 32 - * bit applications, for instance.) Offsets of data elements in - * bootmem list, must match cvmx_bootmem_block_header_t. - */ -#define NEXT_OFFSET 0 -#define SIZE_OFFSET 8 - -static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size) -{ - cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size); -} - -static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next) -{ - cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next); -} - -static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr) -{ - return cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63)); -} - -static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr) -{ - return cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63)); -} - -void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, - uint64_t min_addr, uint64_t max_addr) -{ - int64_t address; - address = - cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0); - - if (address > 0) - return cvmx_phys_to_ptr(address); - else - return NULL; -} - -void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, - uint64_t alignment) -{ - return cvmx_bootmem_alloc_range(size, alignment, address, - address + size); -} - -void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment) -{ - return cvmx_bootmem_alloc_range(size, alignment, 0, 0); -} - -int cvmx_bootmem_free_named(char *name) -{ - return cvmx_bootmem_phy_named_block_free(name, 0); -} - -struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name) -{ - return cvmx_bootmem_phy_named_block_find(name, 0); -} - -void cvmx_bootmem_lock(void) -{ - cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock)); -} - -void cvmx_bootmem_unlock(void) -{ - cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock)); -} - -int cvmx_bootmem_init(void *mem_desc_ptr) -{ - /* Here we set the global pointer to the bootmem descriptor - * block. This pointer will be used directly, so we will set - * it up to be directly usable by the application. It is set - * up as follows for the various runtime/ABI combinations: - * - * Linux 64 bit: Set XKPHYS bit - * Linux 32 bit: use mmap to create mapping, use virtual address - * CVMX 64 bit: use physical address directly - * CVMX 32 bit: use physical address directly - * - * Note that the CVMX environment assumes the use of 1-1 TLB - * mappings so that the physical addresses can be used - * directly - */ - if (!cvmx_bootmem_desc) { -#if defined(CVMX_ABI_64) - /* Set XKPHYS bit */ - cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr)); -#else - cvmx_bootmem_desc = (struct cvmx_bootmem_desc *) mem_desc_ptr; -#endif - } - - return 0; -} - -/* - * The cvmx_bootmem_phy* functions below return 64 bit physical - * addresses, and expose more features that the cvmx_bootmem_functions - * above. These are required for full memory space access in 32 bit - * applications, as well as for using some advance features. Most - * applications should not need to use these. - */ - -int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, - uint64_t address_max, uint64_t alignment, - uint32_t flags) -{ - - uint64_t head_addr; - uint64_t ent_addr; - /* points to previous list entry, NULL current entry is head of list */ - uint64_t prev_addr = 0; - uint64_t new_ent_addr = 0; - uint64_t desired_min_addr; - -#ifdef DEBUG - cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, " - "min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n", - (unsigned long long)req_size, - (unsigned long long)address_min, - (unsigned long long)address_max, - (unsigned long long)alignment); -#endif - - if (cvmx_bootmem_desc->major_version > 3) { - cvmx_dprintf("ERROR: Incompatible bootmem descriptor " - "version: %d.%d at addr: %p\n", - (int)cvmx_bootmem_desc->major_version, - (int)cvmx_bootmem_desc->minor_version, - cvmx_bootmem_desc); - goto error_out; - } - - /* - * Do a variety of checks to validate the arguments. The - * allocator code will later assume that these checks have - * been made. We validate that the requested constraints are - * not self-contradictory before we look through the list of - * available memory. - */ - - /* 0 is not a valid req_size for this allocator */ - if (!req_size) - goto error_out; - - /* Round req_size up to mult of minimum alignment bytes */ - req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) & - ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1); - - /* - * Convert !0 address_min and 0 address_max to special case of - * range that specifies an exact memory block to allocate. Do - * this before other checks and adjustments so that this - * tranformation will be validated. - */ - if (address_min && !address_max) - address_max = address_min + req_size; - else if (!address_min && !address_max) - address_max = ~0ull; /* If no limits given, use max limits */ - - - /* - * Enforce minimum alignment (this also keeps the minimum free block - * req_size the same as the alignment req_size. - */ - if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE) - alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE; - - /* - * Adjust address minimum based on requested alignment (round - * up to meet alignment). Do this here so we can reject - * impossible requests up front. (NOP for address_min == 0) - */ - if (alignment) - address_min = __ALIGN_MASK(address_min, (alignment - 1)); - - /* - * Reject inconsistent args. We have adjusted these, so this - * may fail due to our internal changes even if this check - * would pass for the values the user supplied. - */ - if (req_size > address_max - address_min) - goto error_out; - - /* Walk through the list entries - first fit found is returned */ - - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_lock(); - head_addr = cvmx_bootmem_desc->head_addr; - ent_addr = head_addr; - for (; ent_addr; - prev_addr = ent_addr, - ent_addr = cvmx_bootmem_phy_get_next(ent_addr)) { - uint64_t usable_base, usable_max; - uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr); - - if (cvmx_bootmem_phy_get_next(ent_addr) - && ent_addr > cvmx_bootmem_phy_get_next(ent_addr)) { - cvmx_dprintf("Internal bootmem_alloc() error: ent: " - "0x%llx, next: 0x%llx\n", - (unsigned long long)ent_addr, - (unsigned long long) - cvmx_bootmem_phy_get_next(ent_addr)); - goto error_out; - } - - /* - * Determine if this is an entry that can satisify the - * request Check to make sure entry is large enough to - * satisfy request. - */ - usable_base = - __ALIGN_MASK(max(address_min, ent_addr), alignment - 1); - usable_max = min(address_max, ent_addr + ent_size); - /* - * We should be able to allocate block at address - * usable_base. - */ - - desired_min_addr = usable_base; - /* - * Determine if request can be satisfied from the - * current entry. - */ - if (!((ent_addr + ent_size) > usable_base - && ent_addr < address_max - && req_size <= usable_max - usable_base)) - continue; - /* - * We have found an entry that has room to satisfy the - * request, so allocate it from this entry. If end - * CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from - * the end of this block rather than the beginning. - */ - if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC) { - desired_min_addr = usable_max - req_size; - /* - * Align desired address down to required - * alignment. - */ - desired_min_addr &= ~(alignment - 1); - } - - /* Match at start of entry */ - if (desired_min_addr == ent_addr) { - if (req_size < ent_size) { - /* - * big enough to create a new block - * from top portion of block. - */ - new_ent_addr = ent_addr + req_size; - cvmx_bootmem_phy_set_next(new_ent_addr, - cvmx_bootmem_phy_get_next(ent_addr)); - cvmx_bootmem_phy_set_size(new_ent_addr, - ent_size - - req_size); - - /* - * Adjust next pointer as following - * code uses this. - */ - cvmx_bootmem_phy_set_next(ent_addr, - new_ent_addr); - } - - /* - * adjust prev ptr or head to remove this - * entry from list. - */ - if (prev_addr) - cvmx_bootmem_phy_set_next(prev_addr, - cvmx_bootmem_phy_get_next(ent_addr)); - else - /* - * head of list being returned, so - * update head ptr. - */ - cvmx_bootmem_desc->head_addr = - cvmx_bootmem_phy_get_next(ent_addr); - - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_unlock(); - return desired_min_addr; - } - /* - * block returned doesn't start at beginning of entry, - * so we know that we will be splitting a block off - * the front of this one. Create a new block from the - * beginning, add to list, and go to top of loop - * again. - * - * create new block from high portion of - * block, so that top block starts at desired - * addr. - */ - new_ent_addr = desired_min_addr; - cvmx_bootmem_phy_set_next(new_ent_addr, - cvmx_bootmem_phy_get_next - (ent_addr)); - cvmx_bootmem_phy_set_size(new_ent_addr, - cvmx_bootmem_phy_get_size - (ent_addr) - - (desired_min_addr - - ent_addr)); - cvmx_bootmem_phy_set_size(ent_addr, - desired_min_addr - ent_addr); - cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr); - /* Loop again to handle actual alloc from new block */ - } -error_out: - /* We didn't find anything, so return error */ - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_unlock(); - return -1; -} - -int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags) -{ - uint64_t cur_addr; - uint64_t prev_addr = 0; /* zero is invalid */ - int retval = 0; - -#ifdef DEBUG - cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n", - (unsigned long long)phy_addr, (unsigned long long)size); -#endif - if (cvmx_bootmem_desc->major_version > 3) { - cvmx_dprintf("ERROR: Incompatible bootmem descriptor " - "version: %d.%d at addr: %p\n", - (int)cvmx_bootmem_desc->major_version, - (int)cvmx_bootmem_desc->minor_version, - cvmx_bootmem_desc); - return 0; - } - - /* 0 is not a valid size for this allocator */ - if (!size) - return 0; - - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_lock(); - cur_addr = cvmx_bootmem_desc->head_addr; - if (cur_addr == 0 || phy_addr < cur_addr) { - /* add at front of list - special case with changing head ptr */ - if (cur_addr && phy_addr + size > cur_addr) - goto bootmem_free_done; /* error, overlapping section */ - else if (phy_addr + size == cur_addr) { - /* Add to front of existing first block */ - cvmx_bootmem_phy_set_next(phy_addr, - cvmx_bootmem_phy_get_next - (cur_addr)); - cvmx_bootmem_phy_set_size(phy_addr, - cvmx_bootmem_phy_get_size - (cur_addr) + size); - cvmx_bootmem_desc->head_addr = phy_addr; - - } else { - /* New block before first block. OK if cur_addr is 0 */ - cvmx_bootmem_phy_set_next(phy_addr, cur_addr); - cvmx_bootmem_phy_set_size(phy_addr, size); - cvmx_bootmem_desc->head_addr = phy_addr; - } - retval = 1; - goto bootmem_free_done; - } - - /* Find place in list to add block */ - while (cur_addr && phy_addr > cur_addr) { - prev_addr = cur_addr; - cur_addr = cvmx_bootmem_phy_get_next(cur_addr); - } - - if (!cur_addr) { - /* - * We have reached the end of the list, add on to end, - * checking to see if we need to combine with last - * block - */ - if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) == - phy_addr) { - cvmx_bootmem_phy_set_size(prev_addr, - cvmx_bootmem_phy_get_size - (prev_addr) + size); - } else { - cvmx_bootmem_phy_set_next(prev_addr, phy_addr); - cvmx_bootmem_phy_set_size(phy_addr, size); - cvmx_bootmem_phy_set_next(phy_addr, 0); - } - retval = 1; - goto bootmem_free_done; - } else { - /* - * insert between prev and cur nodes, checking for - * merge with either/both. - */ - if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) == - phy_addr) { - /* Merge with previous */ - cvmx_bootmem_phy_set_size(prev_addr, - cvmx_bootmem_phy_get_size - (prev_addr) + size); - if (phy_addr + size == cur_addr) { - /* Also merge with current */ - cvmx_bootmem_phy_set_size(prev_addr, - cvmx_bootmem_phy_get_size(cur_addr) + - cvmx_bootmem_phy_get_size(prev_addr)); - cvmx_bootmem_phy_set_next(prev_addr, - cvmx_bootmem_phy_get_next(cur_addr)); - } - retval = 1; - goto bootmem_free_done; - } else if (phy_addr + size == cur_addr) { - /* Merge with current */ - cvmx_bootmem_phy_set_size(phy_addr, - cvmx_bootmem_phy_get_size - (cur_addr) + size); - cvmx_bootmem_phy_set_next(phy_addr, - cvmx_bootmem_phy_get_next - (cur_addr)); - cvmx_bootmem_phy_set_next(prev_addr, phy_addr); - retval = 1; - goto bootmem_free_done; - } - - /* It is a standalone block, add in between prev and cur */ - cvmx_bootmem_phy_set_size(phy_addr, size); - cvmx_bootmem_phy_set_next(phy_addr, cur_addr); - cvmx_bootmem_phy_set_next(prev_addr, phy_addr); - - } - retval = 1; - -bootmem_free_done: - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_unlock(); - return retval; - -} - -struct cvmx_bootmem_named_block_desc * - cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags) -{ - unsigned int i; - struct cvmx_bootmem_named_block_desc *named_block_array_ptr; - -#ifdef DEBUG - cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name); -#endif - /* - * Lock the structure to make sure that it is not being - * changed while we are examining it. - */ - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_lock(); - - /* Use XKPHYS for 64 bit linux */ - named_block_array_ptr = (struct cvmx_bootmem_named_block_desc *) - cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr); - -#ifdef DEBUG - cvmx_dprintf - ("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n", - named_block_array_ptr); -#endif - if (cvmx_bootmem_desc->major_version == 3) { - for (i = 0; - i < cvmx_bootmem_desc->named_block_num_blocks; i++) { - if ((name && named_block_array_ptr[i].size - && !strncmp(name, named_block_array_ptr[i].name, - cvmx_bootmem_desc->named_block_name_len - - 1)) - || (!name && !named_block_array_ptr[i].size)) { - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_unlock(); - - return &(named_block_array_ptr[i]); - } - } - } else { - cvmx_dprintf("ERROR: Incompatible bootmem descriptor " - "version: %d.%d at addr: %p\n", - (int)cvmx_bootmem_desc->major_version, - (int)cvmx_bootmem_desc->minor_version, - cvmx_bootmem_desc); - } - if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) - cvmx_bootmem_unlock(); - - return NULL; -} - -int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags) -{ - struct cvmx_bootmem_named_block_desc *named_block_ptr; - - if (cvmx_bootmem_desc->major_version != 3) { - cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: " - "%d.%d at addr: %p\n", - (int)cvmx_bootmem_desc->major_version, - (int)cvmx_bootmem_desc->minor_version, - cvmx_bootmem_desc); - return 0; - } -#ifdef DEBUG - cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name); -#endif - - /* - * Take lock here, as name lookup/block free/name free need to - * be atomic. - */ - cvmx_bootmem_lock(); - - named_block_ptr = - cvmx_bootmem_phy_named_block_find(name, - CVMX_BOOTMEM_FLAG_NO_LOCKING); - if (named_block_ptr) { -#ifdef DEBUG - cvmx_dprintf("cvmx_bootmem_phy_named_block_free: " - "%s, base: 0x%llx, size: 0x%llx\n", - name, - (unsigned long long)named_block_ptr->base_addr, - (unsigned long long)named_block_ptr->size); -#endif - __cvmx_bootmem_phy_free(named_block_ptr->base_addr, - named_block_ptr->size, - CVMX_BOOTMEM_FLAG_NO_LOCKING); - named_block_ptr->size = 0; - /* Set size to zero to indicate block not used. */ - } - - cvmx_bootmem_unlock(); - return named_block_ptr != NULL; /* 0 on failure, 1 on success */ -} diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c deleted file mode 100644 index 6abe56f1e097..000000000000 --- a/trunk/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ /dev/null @@ -1,734 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Implementation of the Level 2 Cache (L2C) control, measurement, and - * debugging facilities. - */ - -#include -#include -#include - -/* - * This spinlock is used internally to ensure that only one core is - * performing certain L2 operations at a time. - * - * NOTE: This only protects calls from within a single application - - * if multiple applications or operating systems are running, then it - * is up to the user program to coordinate between them. - */ -static cvmx_spinlock_t cvmx_l2c_spinlock; - -static inline int l2_size_half(void) -{ - uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3); - return !!(val & (1ull << 34)); -} - -int cvmx_l2c_get_core_way_partition(uint32_t core) -{ - uint32_t field; - - /* Validate the core number */ - if (core >= cvmx_octeon_num_cores()) - return -1; - - /* - * Use the lower two bits of the coreNumber to determine the - * bit offset of the UMSK[] field in the L2C_SPAR register. - */ - field = (core & 0x3) * 8; - - /* - * Return the UMSK[] field from the appropriate L2C_SPAR - * register based on the coreNumber. - */ - - switch (core & 0xC) { - case 0x0: - return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> - field; - case 0x4: - return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> - field; - case 0x8: - return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> - field; - case 0xC: - return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> - field; - } - return 0; -} - -int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) -{ - uint32_t field; - uint32_t valid_mask; - - valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; - - mask &= valid_mask; - - /* A UMSK setting which blocks all L2C Ways is an error. */ - if (mask == valid_mask) - return -1; - - /* Validate the core number */ - if (core >= cvmx_octeon_num_cores()) - return -1; - - /* Check to make sure current mask & new mask don't block all ways */ - if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) == - valid_mask) - return -1; - - /* Use the lower two bits of core to determine the bit offset of the - * UMSK[] field in the L2C_SPAR register. - */ - field = (core & 0x3) * 8; - - /* Assign the new mask setting to the UMSK[] field in the appropriate - * L2C_SPAR register based on the core_num. - * - */ - switch (core & 0xC) { - case 0x0: - cvmx_write_csr(CVMX_L2C_SPAR0, - (cvmx_read_csr(CVMX_L2C_SPAR0) & - ~(0xFF << field)) | mask << field); - break; - case 0x4: - cvmx_write_csr(CVMX_L2C_SPAR1, - (cvmx_read_csr(CVMX_L2C_SPAR1) & - ~(0xFF << field)) | mask << field); - break; - case 0x8: - cvmx_write_csr(CVMX_L2C_SPAR2, - (cvmx_read_csr(CVMX_L2C_SPAR2) & - ~(0xFF << field)) | mask << field); - break; - case 0xC: - cvmx_write_csr(CVMX_L2C_SPAR3, - (cvmx_read_csr(CVMX_L2C_SPAR3) & - ~(0xFF << field)) | mask << field); - break; - } - return 0; -} - -int cvmx_l2c_set_hw_way_partition(uint32_t mask) -{ - uint32_t valid_mask; - - valid_mask = 0xff; - - if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) { - if (l2_size_half()) - valid_mask = 0xf; - } else if (l2_size_half()) - valid_mask = 0x3; - - mask &= valid_mask; - - /* A UMSK setting which blocks all L2C Ways is an error. */ - if (mask == valid_mask) - return -1; - /* Check to make sure current mask & new mask don't block all ways */ - if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) == - valid_mask) - return -1; - - cvmx_write_csr(CVMX_L2C_SPAR4, - (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); - return 0; -} - -int cvmx_l2c_get_hw_way_partition(void) -{ - return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF); -} - -void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, - uint32_t clear_on_read) -{ - union cvmx_l2c_pfctl pfctl; - - pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL); - - switch (counter) { - case 0: - pfctl.s.cnt0sel = event; - pfctl.s.cnt0ena = 1; - if (!cvmx_octeon_is_pass1()) - pfctl.s.cnt0rdclr = clear_on_read; - break; - case 1: - pfctl.s.cnt1sel = event; - pfctl.s.cnt1ena = 1; - if (!cvmx_octeon_is_pass1()) - pfctl.s.cnt1rdclr = clear_on_read; - break; - case 2: - pfctl.s.cnt2sel = event; - pfctl.s.cnt2ena = 1; - if (!cvmx_octeon_is_pass1()) - pfctl.s.cnt2rdclr = clear_on_read; - break; - case 3: - default: - pfctl.s.cnt3sel = event; - pfctl.s.cnt3ena = 1; - if (!cvmx_octeon_is_pass1()) - pfctl.s.cnt3rdclr = clear_on_read; - break; - } - - cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); -} - -uint64_t cvmx_l2c_read_perf(uint32_t counter) -{ - switch (counter) { - case 0: - return cvmx_read_csr(CVMX_L2C_PFC0); - case 1: - return cvmx_read_csr(CVMX_L2C_PFC1); - case 2: - return cvmx_read_csr(CVMX_L2C_PFC2); - case 3: - default: - return cvmx_read_csr(CVMX_L2C_PFC3); - } -} - -/** - * @INTERNAL - * Helper function use to fault in cache lines for L2 cache locking - * - * @addr: Address of base of memory region to read into L2 cache - * @len: Length (in bytes) of region to fault in - */ -static void fault_in(uint64_t addr, int len) -{ - volatile char *ptr; - volatile char dummy; - /* - * Adjust addr and length so we get all cache lines even for - * small ranges spanning two cache lines - */ - len += addr & CVMX_CACHE_LINE_MASK; - addr &= ~CVMX_CACHE_LINE_MASK; - ptr = (volatile char *)cvmx_phys_to_ptr(addr); - /* - * Invalidate L1 cache to make sure all loads result in data - * being in L2. - */ - CVMX_DCACHE_INVALIDATE; - while (len > 0) { - dummy += *ptr; - len -= CVMX_CACHE_LINE_SIZE; - ptr += CVMX_CACHE_LINE_SIZE; - } -} - -int cvmx_l2c_lock_line(uint64_t addr) -{ - int retval = 0; - union cvmx_l2c_dbg l2cdbg; - union cvmx_l2c_lckbase lckbase; - union cvmx_l2c_lckoff lckoff; - union cvmx_l2t_err l2t_err; - l2cdbg.u64 = 0; - lckbase.u64 = 0; - lckoff.u64 = 0; - - cvmx_spinlock_lock(&cvmx_l2c_spinlock); - - /* Clear l2t error bits if set */ - l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); - l2t_err.s.lckerr = 1; - l2t_err.s.lckerr2 = 1; - cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); - - addr &= ~CVMX_CACHE_LINE_MASK; - - /* Set this core as debug core */ - l2cdbg.s.ppnum = cvmx_get_core_num(); - CVMX_SYNC; - cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); - cvmx_read_csr(CVMX_L2C_DBG); - - lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */ - cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64); - cvmx_read_csr(CVMX_L2C_LCKOFF); - - if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) { - int alias_shift = - CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1; - uint64_t addr_tmp = - addr ^ (addr & ((1 << alias_shift) - 1)) >> - CVMX_L2_SET_BITS; - lckbase.s.lck_base = addr_tmp >> 7; - } else { - lckbase.s.lck_base = addr >> 7; - } - - lckbase.s.lck_ena = 1; - cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); - cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */ - - fault_in(addr, CVMX_CACHE_LINE_SIZE); - - lckbase.s.lck_ena = 0; - cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64); - cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */ - - /* Stop being debug core */ - cvmx_write_csr(CVMX_L2C_DBG, 0); - cvmx_read_csr(CVMX_L2C_DBG); - - l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR); - if (l2t_err.s.lckerr || l2t_err.s.lckerr2) - retval = 1; /* We were unable to lock the line */ - - cvmx_spinlock_unlock(&cvmx_l2c_spinlock); - - return retval; -} - -int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len) -{ - int retval = 0; - - /* Round start/end to cache line boundaries */ - len += start & CVMX_CACHE_LINE_MASK; - start &= ~CVMX_CACHE_LINE_MASK; - len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK; - - while (len) { - retval += cvmx_l2c_lock_line(start); - start += CVMX_CACHE_LINE_SIZE; - len -= CVMX_CACHE_LINE_SIZE; - } - - return retval; -} - -void cvmx_l2c_flush(void) -{ - uint64_t assoc, set; - uint64_t n_assoc, n_set; - union cvmx_l2c_dbg l2cdbg; - - cvmx_spinlock_lock(&cvmx_l2c_spinlock); - - l2cdbg.u64 = 0; - if (!OCTEON_IS_MODEL(OCTEON_CN30XX)) - l2cdbg.s.ppnum = cvmx_get_core_num(); - l2cdbg.s.finv = 1; - n_set = CVMX_L2_SETS; - n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC; - for (set = 0; set < n_set; set++) { - for (assoc = 0; assoc < n_assoc; assoc++) { - l2cdbg.s.set = assoc; - /* Enter debug mode, and make sure all other - ** writes complete before we enter debug - ** mode */ - CVMX_SYNCW; - cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); - cvmx_read_csr(CVMX_L2C_DBG); - - CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG - (CVMX_MIPS_SPACE_XKPHYS, - set * CVMX_CACHE_LINE_SIZE), 0); - CVMX_SYNCW; /* Push STF out to L2 */ - /* Exit debug mode */ - CVMX_SYNC; - cvmx_write_csr(CVMX_L2C_DBG, 0); - cvmx_read_csr(CVMX_L2C_DBG); - } - } - - cvmx_spinlock_unlock(&cvmx_l2c_spinlock); -} - -int cvmx_l2c_unlock_line(uint64_t address) -{ - int assoc; - union cvmx_l2c_tag tag; - union cvmx_l2c_dbg l2cdbg; - uint32_t tag_addr; - - uint32_t index = cvmx_l2c_address_to_index(address); - - cvmx_spinlock_lock(&cvmx_l2c_spinlock); - /* Compute portion of address that is stored in tag */ - tag_addr = - ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & - ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1)); - for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) { - tag = cvmx_get_l2c_tag(assoc, index); - - if (tag.s.V && (tag.s.addr == tag_addr)) { - l2cdbg.u64 = 0; - l2cdbg.s.ppnum = cvmx_get_core_num(); - l2cdbg.s.set = assoc; - l2cdbg.s.finv = 1; - - CVMX_SYNC; - /* Enter debug mode */ - cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); - cvmx_read_csr(CVMX_L2C_DBG); - - CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG - (CVMX_MIPS_SPACE_XKPHYS, - address), 0); - CVMX_SYNC; - /* Exit debug mode */ - cvmx_write_csr(CVMX_L2C_DBG, 0); - cvmx_read_csr(CVMX_L2C_DBG); - cvmx_spinlock_unlock(&cvmx_l2c_spinlock); - return tag.s.L; - } - } - cvmx_spinlock_unlock(&cvmx_l2c_spinlock); - return 0; -} - -int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len) -{ - int num_unlocked = 0; - /* Round start/end to cache line boundaries */ - len += start & CVMX_CACHE_LINE_MASK; - start &= ~CVMX_CACHE_LINE_MASK; - len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK; - while (len > 0) { - num_unlocked += cvmx_l2c_unlock_line(start); - start += CVMX_CACHE_LINE_SIZE; - len -= CVMX_CACHE_LINE_SIZE; - } - - return num_unlocked; -} - -/* - * Internal l2c tag types. These are converted to a generic structure - * that can be used on all chips. - */ -union __cvmx_l2c_tag { - uint64_t u64; - struct cvmx_l2c_tag_cn50xx { - uint64_t reserved:40; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:20; /* Phys mem addr (33..14) */ - } cn50xx; - struct cvmx_l2c_tag_cn30xx { - uint64_t reserved:41; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:19; /* Phys mem addr (33..15) */ - } cn30xx; - struct cvmx_l2c_tag_cn31xx { - uint64_t reserved:42; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:18; /* Phys mem addr (33..16) */ - } cn31xx; - struct cvmx_l2c_tag_cn38xx { - uint64_t reserved:43; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:17; /* Phys mem addr (33..17) */ - } cn38xx; - struct cvmx_l2c_tag_cn58xx { - uint64_t reserved:44; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:16; /* Phys mem addr (33..18) */ - } cn58xx; - struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ - struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ -}; - -/** - * @INTERNAL - * Function to read a L2C tag. This code make the current core - * the 'debug core' for the L2. This code must only be executed by - * 1 core at a time. - * - * @assoc: Association (way) of the tag to dump - * @index: Index of the cacheline - * - * Returns The Octeon model specific tag structure. This is - * translated by a wrapper function to a generic form that is - * easier for applications to use. - */ -static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index) -{ - - uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96); - uint64_t core = cvmx_get_core_num(); - union __cvmx_l2c_tag tag_val; - uint64_t dbg_addr = CVMX_L2C_DBG; - unsigned long flags; - - union cvmx_l2c_dbg debug_val; - debug_val.u64 = 0; - /* - * For low core count parts, the core number is always small enough - * to stay in the correct field and not set any reserved bits. - */ - debug_val.s.ppnum = core; - debug_val.s.l2t = 1; - debug_val.s.set = assoc; - /* - * Make sure core is quiet (no prefetches, etc.) before - * entering debug mode. - */ - CVMX_SYNC; - /* Flush L1 to make sure debug load misses L1 */ - CVMX_DCACHE_INVALIDATE; - - local_irq_save(flags); - - /* - * The following must be done in assembly as when in debug - * mode all data loads from L2 return special debug data, not - * normal memory contents. Also, interrupts must be - * disabled, since if an interrupt occurs while in debug mode - * the ISR will get debug data from all its memory reads - * instead of the contents of memory - */ - - asm volatile (".set push \n" - " .set mips64 \n" - " .set noreorder \n" - /* Enter debug mode, wait for store */ - " sd %[dbg_val], 0(%[dbg_addr]) \n" - " ld $0, 0(%[dbg_addr]) \n" - /* Read L2C tag data */ - " ld %[tag_val], 0(%[tag_addr]) \n" - /* Exit debug mode, wait for store */ - " sd $0, 0(%[dbg_addr]) \n" - " ld $0, 0(%[dbg_addr]) \n" - /* Invalidate dcache to discard debug data */ - " cache 9, 0($0) \n" - " .set pop" : - [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr), - [dbg_val] "r"(debug_val.u64), - [tag_addr] "r"(debug_tag_addr) : "memory"); - - local_irq_restore(flags); - return tag_val; - -} - -union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) -{ - union __cvmx_l2c_tag tmp_tag; - union cvmx_l2c_tag tag; - tag.u64 = 0; - - if ((int)association >= cvmx_l2c_get_num_assoc()) { - cvmx_dprintf - ("ERROR: cvmx_get_l2c_tag association out of range\n"); - return tag; - } - if ((int)index >= cvmx_l2c_get_num_sets()) { - cvmx_dprintf("ERROR: cvmx_get_l2c_tag " - "index out of range (arg: %d, max: %d\n", - index, cvmx_l2c_get_num_sets()); - return tag; - } - /* __read_l2_tag is intended for internal use only */ - tmp_tag = __read_l2_tag(association, index); - - /* - * Convert all tag structure types to generic version, as it - * can represent all models. - */ - if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { - tag.s.V = tmp_tag.cn58xx.V; - tag.s.D = tmp_tag.cn58xx.D; - tag.s.L = tmp_tag.cn58xx.L; - tag.s.U = tmp_tag.cn58xx.U; - tag.s.addr = tmp_tag.cn58xx.addr; - } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { - tag.s.V = tmp_tag.cn38xx.V; - tag.s.D = tmp_tag.cn38xx.D; - tag.s.L = tmp_tag.cn38xx.L; - tag.s.U = tmp_tag.cn38xx.U; - tag.s.addr = tmp_tag.cn38xx.addr; - } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) { - tag.s.V = tmp_tag.cn31xx.V; - tag.s.D = tmp_tag.cn31xx.D; - tag.s.L = tmp_tag.cn31xx.L; - tag.s.U = tmp_tag.cn31xx.U; - tag.s.addr = tmp_tag.cn31xx.addr; - } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { - tag.s.V = tmp_tag.cn30xx.V; - tag.s.D = tmp_tag.cn30xx.D; - tag.s.L = tmp_tag.cn30xx.L; - tag.s.U = tmp_tag.cn30xx.U; - tag.s.addr = tmp_tag.cn30xx.addr; - } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { - tag.s.V = tmp_tag.cn50xx.V; - tag.s.D = tmp_tag.cn50xx.D; - tag.s.L = tmp_tag.cn50xx.L; - tag.s.U = tmp_tag.cn50xx.U; - tag.s.addr = tmp_tag.cn50xx.addr; - } else { - cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); - } - - return tag; -} - -uint32_t cvmx_l2c_address_to_index(uint64_t addr) -{ - uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT; - union cvmx_l2c_cfg l2c_cfg; - l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); - - if (l2c_cfg.s.idxalias) { - idx ^= - ((addr & CVMX_L2C_ALIAS_MASK) >> - CVMX_L2C_TAG_ADDR_ALIAS_SHIFT); - } - idx &= CVMX_L2C_IDX_MASK; - return idx; -} - -int cvmx_l2c_get_cache_size_bytes(void) -{ - return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() * - CVMX_CACHE_LINE_SIZE; -} - -/** - * Return log base 2 of the number of sets in the L2 cache - * Returns - */ -int cvmx_l2c_get_set_bits(void) -{ - int l2_set_bits; - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - l2_set_bits = 11; /* 2048 sets */ - else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) - l2_set_bits = 10; /* 1024 sets */ - else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) - l2_set_bits = 9; /* 512 sets */ - else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) - l2_set_bits = 8; /* 256 sets */ - else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) - l2_set_bits = 7; /* 128 sets */ - else { - cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); - l2_set_bits = 11; /* 2048 sets */ - } - return l2_set_bits; - -} - -/* Return the number of sets in the L2 Cache */ -int cvmx_l2c_get_num_sets(void) -{ - return 1 << cvmx_l2c_get_set_bits(); -} - -/* Return the number of associations in the L2 Cache */ -int cvmx_l2c_get_num_assoc(void) -{ - int l2_assoc; - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || - OCTEON_IS_MODEL(OCTEON_CN52XX) || - OCTEON_IS_MODEL(OCTEON_CN58XX) || - OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) - l2_assoc = 8; - else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || - OCTEON_IS_MODEL(OCTEON_CN30XX)) - l2_assoc = 4; - else { - cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); - l2_assoc = 8; - } - - /* Check to see if part of the cache is disabled */ - if (cvmx_fuse_read(265)) - l2_assoc = l2_assoc >> 2; - else if (cvmx_fuse_read(264)) - l2_assoc = l2_assoc >> 1; - - return l2_assoc; -} - -/** - * Flush a line from the L2 cache - * This should only be called from one core at a time, as this routine - * sets the core to the 'debug' core in order to flush the line. - * - * @assoc: Association (or way) to flush - * @index: Index to flush - */ -void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index) -{ - union cvmx_l2c_dbg l2cdbg; - - l2cdbg.u64 = 0; - l2cdbg.s.ppnum = cvmx_get_core_num(); - l2cdbg.s.finv = 1; - - l2cdbg.s.set = assoc; - /* - * Enter debug mode, and make sure all other writes complete - * before we enter debug mode. - */ - asm volatile ("sync" : : : "memory"); - cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); - cvmx_read_csr(CVMX_L2C_DBG); - - CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0); - /* Exit debug mode */ - asm volatile ("sync" : : : "memory"); - cvmx_write_csr(CVMX_L2C_DBG, 0); - cvmx_read_csr(CVMX_L2C_DBG); -} diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c deleted file mode 100644 index 4812370706a1..000000000000 --- a/trunk/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c +++ /dev/null @@ -1,116 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * This module provides system/board/application information obtained - * by the bootloader. - */ - -#include -#include -#include - -/** - * This structure defines the private state maintained by sysinfo module. - * - */ -static struct { - struct cvmx_sysinfo sysinfo; /* system information */ - cvmx_spinlock_t lock; /* mutex spinlock */ - -} state = { - .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER -}; - - -/* - * Global variables that define the min/max of the memory region set - * up for 32 bit userspace access. - */ -uint64_t linux_mem32_min; -uint64_t linux_mem32_max; -uint64_t linux_mem32_wired; -uint64_t linux_mem32_offset; - -/** - * This function returns the application information as obtained - * by the bootloader. This provides the core mask of the cores - * running the same application image, as well as the physical - * memory regions available to the core. - * - * Returns Pointer to the boot information structure - * - */ -struct cvmx_sysinfo *cvmx_sysinfo_get(void) -{ - return &(state.sysinfo); -} - -/** - * This function is used in non-simple executive environments (such as - * Linux kernel, u-boot, etc.) to configure the minimal fields that - * are required to use simple executive files directly. - * - * Locking (if required) must be handled outside of this - * function - * - * @phy_mem_desc_ptr: - * Pointer to global physical memory descriptor - * (bootmem descriptor) @board_type: Octeon board - * type enumeration - * - * @board_rev_major: - * Board major revision - * @board_rev_minor: - * Board minor revision - * @cpu_clock_hz: - * CPU clock freqency in hertz - * - * Returns 0: Failure - * 1: success - */ -int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, - uint16_t board_type, - uint8_t board_rev_major, - uint8_t board_rev_minor, - uint32_t cpu_clock_hz) -{ - - /* The sysinfo structure was already initialized */ - if (state.sysinfo.board_type) - return 0; - - memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo)); - state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr; - state.sysinfo.board_type = board_type; - state.sysinfo.board_rev_major = board_rev_major; - state.sysinfo.board_rev_minor = board_rev_minor; - state.sysinfo.cpu_clock_hz = cpu_clock_hz; - - return 1; -} - diff --git a/trunk/arch/mips/cavium-octeon/executive/octeon-model.c b/trunk/arch/mips/cavium-octeon/executive/octeon-model.c deleted file mode 100644 index 9afc3794ed1b..000000000000 --- a/trunk/arch/mips/cavium-octeon/executive/octeon-model.c +++ /dev/null @@ -1,358 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * File defining functions for working with different Octeon - * models. - */ -#include - -/** - * Given the chip processor ID from COP0, this function returns a - * string representing the chip model number. The string is of the - * form CNXXXXpX.X-FREQ-SUFFIX. - * - XXXX = The chip model number - * - X.X = Chip pass number - * - FREQ = Current frequency in Mhz - * - SUFFIX = NSP, EXP, SCP, SSP, or CP - * - * @chip_id: Chip ID - * - * Returns Model string - */ -const char *octeon_model_get_string(uint32_t chip_id) -{ - static char buffer[32]; - return octeon_model_get_string_buffer(chip_id, buffer); -} - -/* - * Version of octeon_model_get_string() that takes buffer as argument, - * as running early in u-boot static/global variables don't work when - * running from flash. - */ -const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer) -{ - const char *family; - const char *core_model; - char pass[4]; - int clock_mhz; - const char *suffix; - union cvmx_l2d_fus3 fus3; - int num_cores; - union cvmx_mio_fus_dat2 fus_dat2; - union cvmx_mio_fus_dat3 fus_dat3; - char fuse_model[10]; - uint32_t fuse_data = 0; - - fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); - fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); - fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); - - num_cores = cvmx_octeon_num_cores(); - - /* Make sure the non existant devices look disabled */ - switch ((chip_id >> 8) & 0xff) { - case 6: /* CN50XX */ - case 2: /* CN30XX */ - fus_dat3.s.nodfa_dte = 1; - fus_dat3.s.nozip = 1; - break; - case 4: /* CN57XX or CN56XX */ - fus_dat3.s.nodfa_dte = 1; - break; - default: - break; - } - - /* Make a guess at the suffix */ - /* NSP = everything */ - /* EXP = No crypto */ - /* SCP = No DFA, No zip */ - /* CP = No DFA, No crypto, No zip */ - if (fus_dat3.s.nodfa_dte) { - if (fus_dat2.s.nocrypto) - suffix = "CP"; - else - suffix = "SCP"; - } else if (fus_dat2.s.nocrypto) - suffix = "EXP"; - else - suffix = "NSP"; - - /* - * Assume pass number is encoded using <5:3><2:0>. Exceptions - * will be fixed later. - */ - sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7); - - /* - * Use the number of cores to determine the last 2 digits of - * the model number. There are some exceptions that are fixed - * later. - */ - switch (num_cores) { - case 16: - core_model = "60"; - break; - case 15: - core_model = "58"; - break; - case 14: - core_model = "55"; - break; - case 13: - core_model = "52"; - break; - case 12: - core_model = "50"; - break; - case 11: - core_model = "48"; - break; - case 10: - core_model = "45"; - break; - case 9: - core_model = "42"; - break; - case 8: - core_model = "40"; - break; - case 7: - core_model = "38"; - break; - case 6: - core_model = "34"; - break; - case 5: - core_model = "32"; - break; - case 4: - core_model = "30"; - break; - case 3: - core_model = "25"; - break; - case 2: - core_model = "20"; - break; - case 1: - core_model = "10"; - break; - default: - core_model = "XX"; - break; - } - - /* Now figure out the family, the first two digits */ - switch ((chip_id >> 8) & 0xff) { - case 0: /* CN38XX, CN37XX or CN36XX */ - if (fus3.cn38xx.crip_512k) { - /* - * For some unknown reason, the 16 core one is - * called 37 instead of 36. - */ - if (num_cores >= 16) - family = "37"; - else - family = "36"; - } else - family = "38"; - /* - * This series of chips didn't follow the standard - * pass numbering. - */ - switch (chip_id & 0xf) { - case 0: - strcpy(pass, "1.X"); - break; - case 1: - strcpy(pass, "2.X"); - break; - case 3: - strcpy(pass, "3.X"); - break; - default: - strcpy(pass, "X.X"); - break; - } - break; - case 1: /* CN31XX or CN3020 */ - if ((chip_id & 0x10) || fus3.cn31xx.crip_128k) - family = "30"; - else - family = "31"; - /* - * This series of chips didn't follow the standard - * pass numbering. - */ - switch (chip_id & 0xf) { - case 0: - strcpy(pass, "1.0"); - break; - case 2: - strcpy(pass, "1.1"); - break; - default: - strcpy(pass, "X.X"); - break; - } - break; - case 2: /* CN3010 or CN3005 */ - family = "30"; - /* A chip with half cache is an 05 */ - if (fus3.cn30xx.crip_64k) - core_model = "05"; - /* - * This series of chips didn't follow the standard - * pass numbering. - */ - switch (chip_id & 0xf) { - case 0: - strcpy(pass, "1.0"); - break; - case 2: - strcpy(pass, "1.1"); - break; - default: - strcpy(pass, "X.X"); - break; - } - break; - case 3: /* CN58XX */ - family = "58"; - /* Special case. 4 core, no crypto */ - if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto) - core_model = "29"; - - /* Pass 1 uses different encodings for pass numbers */ - if ((chip_id & 0xFF) < 0x8) { - switch (chip_id & 0x3) { - case 0: - strcpy(pass, "1.0"); - break; - case 1: - strcpy(pass, "1.1"); - break; - case 3: - strcpy(pass, "1.2"); - break; - default: - strcpy(pass, "1.X"); - break; - } - } - break; - case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */ - if (fus_dat2.cn56xx.raid_en) { - if (fus3.cn56xx.crip_1024k) - family = "55"; - else - family = "57"; - if (fus_dat2.cn56xx.nocrypto) - suffix = "SP"; - else - suffix = "SSP"; - } else { - if (fus_dat2.cn56xx.nocrypto) - suffix = "CP"; - else { - suffix = "NSP"; - if (fus_dat3.s.nozip) - suffix = "SCP"; - } - if (fus3.cn56xx.crip_1024k) - family = "54"; - else - family = "56"; - } - break; - case 6: /* CN50XX */ - family = "50"; - break; - case 7: /* CN52XX */ - if (fus3.cn52xx.crip_256k) - family = "51"; - else - family = "52"; - break; - default: - family = "XX"; - core_model = "XX"; - strcpy(pass, "X.X"); - suffix = "XXX"; - break; - } - - clock_mhz = octeon_get_clock_rate() / 1000000; - - if (family[0] != '3') { - /* Check for model in fuses, overrides normal decode */ - /* This is _not_ valid for Octeon CN3XXX models */ - fuse_data |= cvmx_fuse_read_byte(51); - fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(50); - fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(49); - fuse_data = fuse_data << 8; - fuse_data |= cvmx_fuse_read_byte(48); - if (fuse_data & 0x7ffff) { - int model = fuse_data & 0x3fff; - int suffix = (fuse_data >> 14) & 0x1f; - if (suffix && model) { - /* - * Have both number and suffix in - * fuses, so both - */ - sprintf(fuse_model, "%d%c", - model, 'A' + suffix - 1); - core_model = ""; - family = fuse_model; - } else if (suffix && !model) { - /* - * Only have suffix, so add suffix to - * 'normal' model number. - */ - sprintf(fuse_model, "%s%c", core_model, - 'A' + suffix - 1); - core_model = fuse_model; - } else { - /* - * Don't have suffix, so just use - * model from fuses. - */ - sprintf(fuse_model, "%d", model); - core_model = ""; - family = fuse_model; - } - } - } - sprintf(buffer, "CN%s%sp%s-%d-%s", - family, core_model, pass, clock_mhz, suffix); - return buffer; -} diff --git a/trunk/arch/mips/cavium-octeon/flash_setup.c b/trunk/arch/mips/cavium-octeon/flash_setup.c deleted file mode 100644 index 553d36cbcc42..000000000000 --- a/trunk/arch/mips/cavium-octeon/flash_setup.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Octeon Bootbus flash setup - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007, 2008 Cavium Networks - */ -#include -#include -#include -#include - -#include - -static struct map_info flash_map; -static struct mtd_info *mymtd; -#ifdef CONFIG_MTD_PARTITIONS -static int nr_parts; -static struct mtd_partition *parts; -static const char *part_probe_types[] = { - "cmdlinepart", -#ifdef CONFIG_MTD_REDBOOT_PARTS - "RedBoot", -#endif - NULL -}; -#endif - -/** - * Module/ driver initialization. - * - * Returns Zero on success - */ -static int __init flash_init(void) -{ - /* - * Read the bootbus region 0 setup to determine the base - * address of the flash. - */ - union cvmx_mio_boot_reg_cfgx region_cfg; - region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0)); - if (region_cfg.s.en) { - /* - * The bootloader always takes the flash and sets its - * address so the entire flash fits below - * 0x1fc00000. This way the flash aliases to - * 0x1fc00000 for booting. Software can access the - * full flash at the true address, while core boot can - * access 4MB. - */ - /* Use this name so old part lines work */ - flash_map.name = "phys_mapped_flash"; - flash_map.phys = region_cfg.s.base << 16; - flash_map.size = 0x1fc00000 - flash_map.phys; - flash_map.bankwidth = 1; - flash_map.virt = ioremap(flash_map.phys, flash_map.size); - pr_notice("Bootbus flash: Setting flash for %luMB flash at " - "0x%08lx\n", flash_map.size >> 20, flash_map.phys); - simple_map_init(&flash_map); - mymtd = do_map_probe("cfi_probe", &flash_map); - if (mymtd) { - mymtd->owner = THIS_MODULE; - -#ifdef CONFIG_MTD_PARTITIONS - nr_parts = parse_mtd_partitions(mymtd, - part_probe_types, - &parts, 0); - if (nr_parts > 0) - add_mtd_partitions(mymtd, parts, nr_parts); - else - add_mtd_device(mymtd); -#else - add_mtd_device(mymtd); -#endif - } else { - pr_err("Failed to register MTD device for flash\n"); - } - } - return 0; -} - -late_initcall(flash_init); diff --git a/trunk/arch/mips/cavium-octeon/octeon-irq.c b/trunk/arch/mips/cavium-octeon/octeon-irq.c deleted file mode 100644 index fc72984a5dae..000000000000 --- a/trunk/arch/mips/cavium-octeon/octeon-irq.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2008 Cavium Networks - */ -#include -#include -#include - -#include - -DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); -DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); -DEFINE_SPINLOCK(octeon_irq_msi_lock); - -static void octeon_irq_core_ack(unsigned int irq) -{ - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * We don't need to disable IRQs to make these atomic since - * they are already disabled earlier in the low level - * interrupt code. - */ - clear_c0_status(0x100 << bit); - /* The two user interrupts must be cleared manually. */ - if (bit < 2) - clear_c0_cause(0x100 << bit); -} - -static void octeon_irq_core_eoi(unsigned int irq) -{ - irq_desc_t *desc = irq_desc + irq; - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * If an IRQ is being processed while we are disabling it the - * handler will attempt to unmask the interrupt after it has - * been disabled. - */ - if (desc->status & IRQ_DISABLED) - return; - - /* There is a race here. We should fix it. */ - - /* - * We don't need to disable IRQs to make these atomic since - * they are already disabled earlier in the low level - * interrupt code. - */ - set_c0_status(0x100 << bit); -} - -static void octeon_irq_core_enable(unsigned int irq) -{ - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; - - /* - * We need to disable interrupts to make sure our updates are - * atomic. - */ - local_irq_save(flags); - set_c0_status(0x100 << bit); - local_irq_restore(flags); -} - -static void octeon_irq_core_disable_local(unsigned int irq) -{ - unsigned long flags; - unsigned int bit = irq - OCTEON_IRQ_SW0; - /* - * We need to disable interrupts to make sure our updates are - * atomic. - */ - local_irq_save(flags); - clear_c0_status(0x100 << bit); - local_irq_restore(flags); -} - -static void octeon_irq_core_disable(unsigned int irq) -{ -#ifdef CONFIG_SMP - on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, - (void *) (long) irq, 1); -#else - octeon_irq_core_disable_local(irq); -#endif -} - -static struct irq_chip octeon_irq_chip_core = { - .name = "Core", - .enable = octeon_irq_core_enable, - .disable = octeon_irq_core_disable, - .ack = octeon_irq_core_ack, - .eoi = octeon_irq_core_eoi, -}; - - -static void octeon_irq_ciu0_ack(unsigned int irq) -{ - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. - * - * We don't need to disable IRQs to make these atomic since - * they are already disabled earlier in the low level - * interrupt code. - */ - clear_c0_status(0x100 << 2); -} - -static void octeon_irq_ciu0_eoi(unsigned int irq) -{ - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 2); -} - -static void octeon_irq_ciu0_enable(unsigned int irq) -{ - int coreid = cvmx_get_core_num(); - unsigned long flags; - uint64_t en0; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - - /* - * A read lock is used here to make sure only one core is ever - * updating the CIU enable bits at a time. During an enable - * the cores don't interfere with each other. During a disable - * the write lock stops any enables that might cause a - * problem. - */ - read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); -} - -static void octeon_irq_ciu0_disable(unsigned int irq) -{ - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - unsigned long flags; - uint64_t en0; -#ifdef CONFIG_SMP - int cpu; - write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); - for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); -#else - int coreid = cvmx_get_core_num(); - local_irq_save(flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - local_irq_restore(flags); -#endif -} - -#ifdef CONFIG_SMP -static void octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) -{ - int cpu; - int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - - write_lock(&octeon_irq_ciu0_rwlock); - for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); - uint64_t en0 = - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - if (cpumask_test_cpu(cpu, dest)) - en0 |= 1ull << bit; - else - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - write_unlock(&octeon_irq_ciu0_rwlock); -} -#endif - -static struct irq_chip octeon_irq_chip_ciu0 = { - .name = "CIU0", - .enable = octeon_irq_ciu0_enable, - .disable = octeon_irq_ciu0_disable, - .ack = octeon_irq_ciu0_ack, - .eoi = octeon_irq_ciu0_eoi, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu0_set_affinity, -#endif -}; - - -static void octeon_irq_ciu1_ack(unsigned int irq) -{ - /* - * In order to avoid any locking accessing the CIU, we - * acknowledge CIU interrupts by disabling all of them. This - * way we can use a per core register and avoid any out of - * core locking requirements. This has the side affect that - * CIU interrupts can't be processed recursively. We don't - * need to disable IRQs to make these atomic since they are - * already disabled earlier in the low level interrupt code. - */ - clear_c0_status(0x100 << 3); -} - -static void octeon_irq_ciu1_eoi(unsigned int irq) -{ - /* - * Enable all CIU interrupts again. We don't need to disable - * IRQs to make these atomic since they are already disabled - * earlier in the low level interrupt code. - */ - set_c0_status(0x100 << 3); -} - -static void octeon_irq_ciu1_enable(unsigned int irq) -{ - int coreid = cvmx_get_core_num(); - unsigned long flags; - uint64_t en1; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - - /* - * A read lock is used here to make sure only one core is ever - * updating the CIU enable bits at a time. During an enable - * the cores don't interfere with each other. During a disable - * the write lock stops any enables that might cause a - * problem. - */ - read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 |= 1ull << bit; - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); -} - -static void octeon_irq_ciu1_disable(unsigned int irq) -{ - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - unsigned long flags; - uint64_t en1; -#ifdef CONFIG_SMP - int cpu; - write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); - for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); -#else - int coreid = cvmx_get_core_num(); - local_irq_save(flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - local_irq_restore(flags); -#endif -} - -#ifdef CONFIG_SMP -static void octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) -{ - int cpu; - int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - - write_lock(&octeon_irq_ciu1_rwlock); - for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); - uint64_t en1 = - cvmx_read_csr(CVMX_CIU_INTX_EN1 - (coreid * 2 + 1)); - if (cpumask_test_cpu(cpu, dest)) - en1 |= 1ull << bit; - else - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - } - /* - * We need to do a read after the last update to make sure all - * of them are done. - */ - cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - write_unlock(&octeon_irq_ciu1_rwlock); -} -#endif - -static struct irq_chip octeon_irq_chip_ciu1 = { - .name = "CIU1", - .enable = octeon_irq_ciu1_enable, - .disable = octeon_irq_ciu1_disable, - .ack = octeon_irq_ciu1_ack, - .eoi = octeon_irq_ciu1_eoi, -#ifdef CONFIG_SMP - .set_affinity = octeon_irq_ciu1_set_affinity, -#endif -}; - -#ifdef CONFIG_PCI_MSI - -static void octeon_irq_msi_ack(unsigned int irq) -{ - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* These chips have PCI */ - cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } else { - /* - * These chips have PCIe. Thankfully the ACK doesn't - * need any locking. - */ - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, - 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - } -} - -static void octeon_irq_msi_eoi(unsigned int irq) -{ - /* Nothing needed */ -} - -static void octeon_irq_msi_enable(unsigned int irq) -{ - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* - * Octeon PCI doesn't have the ability to mask/unmask - * MSI interrupts individually. Instead of - * masking/unmasking them in groups of 16, we simple - * assume MSI devices are well behaved. MSI - * interrupts are always enable and the ACK is assumed - * to be enough. - */ - } else { - /* These chips have PCIe. Note that we only support - * the first 64 MSI interrupts. Unfortunately all the - * MSI enables are in the same register. We use - * MSI0's lock to control access to them all. - */ - uint64_t en; - unsigned long flags; - spin_lock_irqsave(&octeon_irq_msi_lock, flags); - en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0); - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); - cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); - } -} - -static void octeon_irq_msi_disable(unsigned int irq) -{ - if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { - /* See comment in enable */ - } else { - /* - * These chips have PCIe. Note that we only support - * the first 64 MSI interrupts. Unfortunately all the - * MSI enables are in the same register. We use - * MSI0's lock to control access to them all. - */ - uint64_t en; - unsigned long flags; - spin_lock_irqsave(&octeon_irq_msi_lock, flags); - en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0)); - cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); - cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); - spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); - } -} - -static struct irq_chip octeon_irq_chip_msi = { - .name = "MSI", - .enable = octeon_irq_msi_enable, - .disable = octeon_irq_msi_disable, - .ack = octeon_irq_msi_ack, - .eoi = octeon_irq_msi_eoi, -}; -#endif - -void __init arch_init_irq(void) -{ - int irq; - -#ifdef CONFIG_SMP - /* Set the default affinity to the boot cpu. */ - cpumask_clear(irq_default_affinity); - cpumask_set_cpu(smp_processor_id(), irq_default_affinity); -#endif - - if (NR_IRQS < OCTEON_IRQ_LAST) - pr_err("octeon_irq_init: NR_IRQS is set too low\n"); - - /* 0 - 15 reserved for i8259 master and slave controller. */ - - /* 17 - 23 Mips internal */ - for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_core, - handle_percpu_irq); - } - - /* 24 - 87 CIU_INT_SUM0 */ - for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, - handle_percpu_irq); - } - - /* 88 - 151 CIU_INT_SUM1 */ - for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, - handle_percpu_irq); - } - -#ifdef CONFIG_PCI_MSI - /* 152 - 215 PCI/PCIe MSI interrupts */ - for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, - handle_percpu_irq); - } -#endif - set_c0_status(0x300 << 2); -} - -asmlinkage void plat_irq_dispatch(void) -{ - const unsigned long core_id = cvmx_get_core_num(); - const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); - const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); - const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; - const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); - unsigned long cop0_cause; - unsigned long cop0_status; - uint64_t ciu_en; - uint64_t ciu_sum; - - while (1) { - cop0_cause = read_c0_cause(); - cop0_status = read_c0_status(); - cop0_cause &= cop0_status; - cop0_cause &= ST0_IM; - - if (unlikely(cop0_cause & STATUSF_IP2)) { - ciu_sum = cvmx_read_csr(ciu_sum0_address); - ciu_en = cvmx_read_csr(ciu_en0_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) - do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1); - else - spurious_interrupt(); - } else if (unlikely(cop0_cause & STATUSF_IP3)) { - ciu_sum = cvmx_read_csr(ciu_sum1_address); - ciu_en = cvmx_read_csr(ciu_en1_address); - ciu_sum &= ciu_en; - if (likely(ciu_sum)) - do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1); - else - spurious_interrupt(); - } else if (likely(cop0_cause)) { - do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); - } else { - break; - } - } -} diff --git a/trunk/arch/mips/cavium-octeon/octeon-memcpy.S b/trunk/arch/mips/cavium-octeon/octeon-memcpy.S deleted file mode 100644 index 88e0cddca205..000000000000 --- a/trunk/arch/mips/cavium-octeon/octeon-memcpy.S +++ /dev/null @@ -1,521 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Unified implementation of memcpy, memmove and the __copy_user backend. - * - * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. - * Copyright (C) 2002 Broadcom, Inc. - * memcpy/copy_user author: Mark Vandevoorde - * - * Mnemonic names for arguments to memcpy/__copy_user - */ - -#include -#include -#include - -#define dst a0 -#define src a1 -#define len a2 - -/* - * Spec - * - * memcpy copies len bytes from src to dst and sets v0 to dst. - * It assumes that - * - src and dst don't overlap - * - src is readable - * - dst is writable - * memcpy uses the standard calling convention - * - * __copy_user copies up to len bytes from src to dst and sets a2 (len) to - * the number of uncopied bytes due to an exception caused by a read or write. - * __copy_user assumes that src and dst don't overlap, and that the call is - * implementing one of the following: - * copy_to_user - * - src is readable (no exceptions when reading src) - * copy_from_user - * - dst is writable (no exceptions when writing dst) - * __copy_user uses a non-standard calling convention; see - * arch/mips/include/asm/uaccess.h - * - * When an exception happens on a load, the handler must - # ensure that all of the destination buffer is overwritten to prevent - * leaking information to user mode programs. - */ - -/* - * Implementation - */ - -/* - * The exception handler for loads requires that: - * 1- AT contain the address of the byte just past the end of the source - * of the copy, - * 2- src_entry <= src < AT, and - * 3- (dst - src) == (dst_entry - src_entry), - * The _entry suffix denotes values when __copy_user was called. - * - * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user - * (2) is met by incrementing src by the number of bytes copied - * (3) is met by not doing loads between a pair of increments of dst and src - * - * The exception handlers for stores adjust len (if necessary) and return. - * These handlers do not need to overwrite any data. - * - * For __rmemcpy and memmove an exception is always a kernel bug, therefore - * they're not protected. - */ - -#define EXC(inst_reg,addr,handler) \ -9: inst_reg, addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - .previous - -/* - * Only on the 64-bit kernel we can made use of 64-bit registers. - */ -#ifdef CONFIG_64BIT -#define USE_DOUBLE -#endif - -#ifdef USE_DOUBLE - -#define LOAD ld -#define LOADL ldl -#define LOADR ldr -#define STOREL sdl -#define STORER sdr -#define STORE sd -#define ADD daddu -#define SUB dsubu -#define SRL dsrl -#define SRA dsra -#define SLL dsll -#define SLLV dsllv -#define SRLV dsrlv -#define NBYTES 8 -#define LOG_NBYTES 3 - -/* - * As we are sharing code base with the mips32 tree (which use the o32 ABI - * register definitions). We need to redefine the register definitions from - * the n64 ABI register naming to the o32 ABI register naming. - */ -#undef t0 -#undef t1 -#undef t2 -#undef t3 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 - -#else - -#define LOAD lw -#define LOADL lwl -#define LOADR lwr -#define STOREL swl -#define STORER swr -#define STORE sw -#define ADD addu -#define SUB subu -#define SRL srl -#define SLL sll -#define SRA sra -#define SLLV sllv -#define SRLV srlv -#define NBYTES 4 -#define LOG_NBYTES 2 - -#endif /* USE_DOUBLE */ - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define LDFIRST LOADR -#define LDREST LOADL -#define STFIRST STORER -#define STREST STOREL -#define SHIFT_DISCARD SLLV -#else -#define LDFIRST LOADL -#define LDREST LOADR -#define STFIRST STOREL -#define STREST STORER -#define SHIFT_DISCARD SRLV -#endif - -#define FIRST(unit) ((unit)*NBYTES) -#define REST(unit) (FIRST(unit)+NBYTES-1) -#define UNIT(unit) FIRST(unit) - -#define ADDRMASK (NBYTES-1) - - .text - .set noreorder - .set noat - -/* - * A combined memcpy/__copy_user - * __copy_user sets len to 0 for success; else to an upper bound of - * the number of uncopied bytes. - * memcpy sets v0 to dst. - */ - .align 5 -LEAF(memcpy) /* a0=dst a1=src a2=len */ - move v0, dst /* return value */ -__memcpy: -FEXPORT(__copy_user) - /* - * Note: dst & src may be unaligned, len may be 0 - * Temps - */ - # - # Octeon doesn't care if the destination is unaligned. The hardware - # can fix it faster than we can special case the assembly. - # - pref 0, 0(src) - sltu t0, len, NBYTES # Check if < 1 word - bnez t0, copy_bytes_checklen - and t0, src, ADDRMASK # Check if src unaligned - bnez t0, src_unaligned - sltu t0, len, 4*NBYTES # Check if < 4 words - bnez t0, less_than_4units - sltu t0, len, 8*NBYTES # Check if < 8 words - bnez t0, less_than_8units - sltu t0, len, 16*NBYTES # Check if < 16 words - bnez t0, cleanup_both_aligned - sltu t0, len, 128+1 # Check if len < 129 - bnez t0, 1f # Skip prefetch if len is too short - sltu t0, len, 256+1 # Check if len < 257 - bnez t0, 1f # Skip prefetch if len is too short - pref 0, 128(src) # We must not prefetch invalid addresses - # - # This is where we loop if there is more than 128 bytes left -2: pref 0, 256(src) # We must not prefetch invalid addresses - # - # This is where we loop if we can't prefetch anymore -1: -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) - SUB len, len, 16*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc_p16u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p15u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p14u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p13u) -EXC( LOAD t0, UNIT(4)(src), l_exc_copy) -EXC( LOAD t1, UNIT(5)(src), l_exc_copy) -EXC( LOAD t2, UNIT(6)(src), l_exc_copy) -EXC( LOAD t3, UNIT(7)(src), l_exc_copy) -EXC( STORE t0, UNIT(4)(dst), s_exc_p12u) -EXC( STORE t1, UNIT(5)(dst), s_exc_p11u) -EXC( STORE t2, UNIT(6)(dst), s_exc_p10u) - ADD src, src, 16*NBYTES -EXC( STORE t3, UNIT(7)(dst), s_exc_p9u) - ADD dst, dst, 16*NBYTES -EXC( LOAD t0, UNIT(-8)(src), l_exc_copy) -EXC( LOAD t1, UNIT(-7)(src), l_exc_copy) -EXC( LOAD t2, UNIT(-6)(src), l_exc_copy) -EXC( LOAD t3, UNIT(-5)(src), l_exc_copy) -EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u) -EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u) -EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) -EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) -EXC( LOAD t0, UNIT(-4)(src), l_exc_copy) -EXC( LOAD t1, UNIT(-3)(src), l_exc_copy) -EXC( LOAD t2, UNIT(-2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(-1)(src), l_exc_copy) -EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u) - sltu t0, len, 256+1 # See if we can prefetch more - beqz t0, 2b - sltu t0, len, 128 # See if we can loop more time - beqz t0, 1b - nop - # - # Jump here if there are less than 16*NBYTES left. - # -cleanup_both_aligned: - beqz len, done - sltu t0, len, 8*NBYTES - bnez t0, less_than_8units - nop -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) - SUB len, len, 8*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p6u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p5u) -EXC( LOAD t0, UNIT(4)(src), l_exc_copy) -EXC( LOAD t1, UNIT(5)(src), l_exc_copy) -EXC( LOAD t2, UNIT(6)(src), l_exc_copy) -EXC( LOAD t3, UNIT(7)(src), l_exc_copy) -EXC( STORE t0, UNIT(4)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(5)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(6)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(7)(dst), s_exc_p1u) - ADD src, src, 8*NBYTES - beqz len, done - ADD dst, dst, 8*NBYTES - # - # Jump here if there are less than 8*NBYTES left. - # -less_than_8units: - sltu t0, len, 4*NBYTES - bnez t0, less_than_4units - nop -EXC( LOAD t0, UNIT(0)(src), l_exc) -EXC( LOAD t1, UNIT(1)(src), l_exc_copy) -EXC( LOAD t2, UNIT(2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(3)(src), l_exc_copy) - SUB len, len, 4*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) - ADD src, src, 4*NBYTES - beqz len, done - ADD dst, dst, 4*NBYTES - # - # Jump here if there are less than 4*NBYTES left. This means - # we may need to copy up to 3 NBYTES words. - # -less_than_4units: - sltu t0, len, 1*NBYTES - bnez t0, copy_bytes_checklen - nop - # - # 1) Copy NBYTES, then check length again - # -EXC( LOAD t0, 0(src), l_exc) - SUB len, len, NBYTES - sltu t1, len, 8 -EXC( STORE t0, 0(dst), s_exc_p1u) - ADD src, src, NBYTES - bnez t1, copy_bytes_checklen - ADD dst, dst, NBYTES - # - # 2) Copy NBYTES, then check length again - # -EXC( LOAD t0, 0(src), l_exc) - SUB len, len, NBYTES - sltu t1, len, 8 -EXC( STORE t0, 0(dst), s_exc_p1u) - ADD src, src, NBYTES - bnez t1, copy_bytes_checklen - ADD dst, dst, NBYTES - # - # 3) Copy NBYTES, then check length again - # -EXC( LOAD t0, 0(src), l_exc) - SUB len, len, NBYTES - ADD src, src, NBYTES - ADD dst, dst, NBYTES - b copy_bytes_checklen -EXC( STORE t0, -8(dst), s_exc_p1u) - -src_unaligned: -#define rem t8 - SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter - beqz t0, cleanup_src_unaligned - and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES -1: -/* - * Avoid consecutive LD*'s to the same register since some mips - * implementations can't issue them in the same cycle. - * It's OK to load FIRST(N+1) before REST(N) because the two addresses - * are to the same unit (unless src is aligned, but it's not). - */ -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) - SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), l_exc_copy) -EXC( LDREST t1, REST(1)(src), l_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) -EXC( LDREST t2, REST(2)(src), l_exc_copy) -EXC( LDREST t3, REST(3)(src), l_exc_copy) - ADD src, src, 4*NBYTES -EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) - bne len, rem, 1b - ADD dst, dst, 4*NBYTES - -cleanup_src_unaligned: - beqz len, done - and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, copy_bytes - nop -1: -EXC( LDFIRST t0, FIRST(0)(src), l_exc) -EXC( LDREST t0, REST(0)(src), l_exc_copy) - SUB len, len, NBYTES -EXC( STORE t0, 0(dst), s_exc_p1u) - ADD src, src, NBYTES - bne len, rem, 1b - ADD dst, dst, NBYTES - -copy_bytes_checklen: - beqz len, done - nop -copy_bytes: - /* 0 < len < NBYTES */ -#define COPY_BYTE(N) \ -EXC( lb t0, N(src), l_exc); \ - SUB len, len, 1; \ - beqz len, done; \ -EXC( sb t0, N(dst), s_exc_p1) - - COPY_BYTE(0) - COPY_BYTE(1) -#ifdef USE_DOUBLE - COPY_BYTE(2) - COPY_BYTE(3) - COPY_BYTE(4) - COPY_BYTE(5) -#endif -EXC( lb t0, NBYTES-2(src), l_exc) - SUB len, len, 1 - jr ra -EXC( sb t0, NBYTES-2(dst), s_exc_p1) -done: - jr ra - nop - END(memcpy) - -l_exc_copy: - /* - * Copy bytes from src until faulting load address (or until a - * lb faults) - * - * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) - * may be more than a byte beyond the last address. - * Hence, the lb below may get an exception. - * - * Assumes src < THREAD_BUADDR($28) - */ - LOAD t0, TI_TASK($28) - nop - LOAD t0, THREAD_BUADDR(t0) -1: -EXC( lb t1, 0(src), l_exc) - ADD src, src, 1 - sb t1, 0(dst) # can't fault -- we're copy_from_user - bne src, t0, 1b - ADD dst, dst, 1 -l_exc: - LOAD t0, TI_TASK($28) - nop - LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address - nop - SUB len, AT, t0 # len number of uncopied bytes - /* - * Here's where we rely on src and dst being incremented in tandem, - * See (3) above. - * dst += (fault addr - src) to put dst at first byte to clear - */ - ADD dst, t0 # compute start address in a1 - SUB dst, src - /* - * Clear len bytes starting at dst. Can't call __bzero because it - * might modify len. An inefficient loop for these rare times... - */ - beqz len, done - SUB src, len, 1 -1: sb zero, 0(dst) - ADD dst, dst, 1 - bnez src, 1b - SUB src, src, 1 - jr ra - nop - - -#define SEXC(n) \ -s_exc_p ## n ## u: \ - jr ra; \ - ADD len, len, n*NBYTES - -SEXC(16) -SEXC(15) -SEXC(14) -SEXC(13) -SEXC(12) -SEXC(11) -SEXC(10) -SEXC(9) -SEXC(8) -SEXC(7) -SEXC(6) -SEXC(5) -SEXC(4) -SEXC(3) -SEXC(2) -SEXC(1) - -s_exc_p1: - jr ra - ADD len, len, 1 -s_exc: - jr ra - nop - - .align 5 -LEAF(memmove) - ADD t0, a0, a2 - ADD t1, a1, a2 - sltu t0, a1, t0 # dst + len <= src -> memcpy - sltu t1, a0, t1 # dst >= src + len -> memcpy - and t0, t1 - beqz t0, __memcpy - move v0, a0 /* return value */ - beqz a2, r_out - END(memmove) - - /* fall through to __rmemcpy */ -LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ - sltu t0, a1, a0 - beqz t0, r_end_bytes_up # src >= dst - nop - ADD a0, a2 # dst = dst + len - ADD a1, a2 # src = src + len - -r_end_bytes: - lb t0, -1(a1) - SUB a2, a2, 0x1 - sb t0, -1(a0) - SUB a1, a1, 0x1 - bnez a2, r_end_bytes - SUB a0, a0, 0x1 - -r_out: - jr ra - move a2, zero - -r_end_bytes_up: - lb t0, (a1) - SUB a2, a2, 0x1 - sb t0, (a0) - ADD a1, a1, 0x1 - bnez a2, r_end_bytes_up - ADD a0, a0, 0x1 - - jr ra - move a2, zero - END(__rmemcpy) diff --git a/trunk/arch/mips/cavium-octeon/serial.c b/trunk/arch/mips/cavium-octeon/serial.c deleted file mode 100644 index 8240728d485a..000000000000 --- a/trunk/arch/mips/cavium-octeon/serial.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2007 Cavium Networks - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#ifdef CONFIG_GDB_CONSOLE -#define DEBUG_UART 0 -#else -#define DEBUG_UART 1 -#endif - -unsigned int octeon_serial_in(struct uart_port *up, int offset) -{ - int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); - if (offset == UART_IIR && (rv & 0xf) == 7) { - /* Busy interrupt, read the USR (39) and try again. */ - cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); - rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); - } - return rv; -} - -void octeon_serial_out(struct uart_port *up, int offset, int value) -{ - /* - * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits - * working. - */ - if (offset == UART_LCR) - value &= 0x9f; - cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); -} - -/* - * Allocated in .bss, so it is all zeroed. - */ -#define OCTEON_MAX_UARTS 3 -static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1]; -static struct platform_device octeon_uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = octeon_uart8250_data, - }, -}; - -static void __init octeon_uart_set_common(struct plat_serial8250_port *p) -{ - p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; - p->type = PORT_OCTEON; - p->iotype = UPIO_MEM; - p->regshift = 3; /* I/O addresses are every 8 bytes */ - p->uartclk = mips_hpt_frequency; - p->serial_in = octeon_serial_in; - p->serial_out = octeon_serial_out; -} - -static int __init octeon_serial_init(void) -{ - int enable_uart0; - int enable_uart1; - int enable_uart2; - struct plat_serial8250_port *p; - -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - /* - * If we are configured to run as the second of two kernels, - * disable uart0 and enable uart1. Uart0 is owned by the first - * kernel - */ - enable_uart0 = 0; - enable_uart1 = 1; -#else - /* - * We are configured for the first kernel. We'll enable uart0 - * if the bootloader told us to use 0, otherwise will enable - * uart 1. - */ - enable_uart0 = (octeon_get_boot_uart() == 0); - enable_uart1 = (octeon_get_boot_uart() == 1); -#ifdef CONFIG_KGDB - enable_uart1 = 1; -#endif -#endif - - /* Right now CN52XX is the only chip with a third uart */ - enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX); - - p = octeon_uart8250_data; - if (enable_uart0) { - /* Add a ttyS device for hardware uart 0 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UARTX_RBR(0); - p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART0; - p++; - } - - if (enable_uart1) { - /* Add a ttyS device for hardware uart 1 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UARTX_RBR(1); - p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART1; - p++; - } - if (enable_uart2) { - /* Add a ttyS device for hardware uart 2 */ - octeon_uart_set_common(p); - p->membase = (void *) CVMX_MIO_UART2_RBR; - p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1); - p->irq = OCTEON_IRQ_UART2; - p++; - } - - BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); - - return platform_device_register(&octeon_uart8250_device); -} - -device_initcall(octeon_serial_init); diff --git a/trunk/arch/mips/cavium-octeon/setup.c b/trunk/arch/mips/cavium-octeon/setup.c deleted file mode 100644 index e085feddb4a4..000000000000 --- a/trunk/arch/mips/cavium-octeon/setup.c +++ /dev/null @@ -1,929 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2007 Cavium Networks - * Copyright (C) 2008 Wind River Systems - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include /* for memset */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#ifdef CONFIG_CAVIUM_DECODE_RSL -extern void cvmx_interrupt_rsl_decode(void); -extern int __cvmx_interrupt_ecc_report_single_bit_errors; -extern void cvmx_interrupt_rsl_enable(void); -#endif - -extern struct plat_smp_ops octeon_smp_ops; - -#ifdef CONFIG_PCI -extern void pci_console_init(const char *arg); -#endif - -#ifdef CONFIG_CAVIUM_RESERVE32 -extern uint64_t octeon_reserve32_memory; -#endif -static unsigned long long MAX_MEMORY = 512ull << 20; - -struct octeon_boot_descriptor *octeon_boot_desc_ptr; - -struct cvmx_bootinfo *octeon_bootinfo; -EXPORT_SYMBOL(octeon_bootinfo); - -#ifdef CONFIG_CAVIUM_RESERVE32 -uint64_t octeon_reserve32_memory; -EXPORT_SYMBOL(octeon_reserve32_memory); -#endif - -static int octeon_uart; - -extern asmlinkage void handle_int(void); -extern asmlinkage void plat_irq_dispatch(void); - -/** - * Return non zero if we are currently running in the Octeon simulator - * - * Returns - */ -int octeon_is_simulation(void) -{ - return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; -} -EXPORT_SYMBOL(octeon_is_simulation); - -/** - * Return true if Octeon is in PCI Host mode. This means - * Linux can control the PCI bus. - * - * Returns Non zero if Octeon in host mode. - */ -int octeon_is_pci_host(void) -{ -#ifdef CONFIG_PCI - return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; -#else - return 0; -#endif -} - -/** - * Get the clock rate of Octeon - * - * Returns Clock rate in HZ - */ -uint64_t octeon_get_clock_rate(void) -{ - if (octeon_is_simulation()) - octeon_bootinfo->eclock_hz = 6000000; - return octeon_bootinfo->eclock_hz; -} -EXPORT_SYMBOL(octeon_get_clock_rate); - -/** - * Write to the LCD display connected to the bootbus. This display - * exists on most Cavium evaluation boards. If it doesn't exist, then - * this function doesn't do anything. - * - * @s: String to write - */ -void octeon_write_lcd(const char *s) -{ - if (octeon_bootinfo->led_display_base_addr) { - void __iomem *lcd_address = - ioremap_nocache(octeon_bootinfo->led_display_base_addr, - 8); - int i; - for (i = 0; i < 8; i++, s++) { - if (*s) - iowrite8(*s, lcd_address + i); - else - iowrite8(' ', lcd_address + i); - } - iounmap(lcd_address); - } -} - -/** - * Return the console uart passed by the bootloader - * - * Returns uart (0 or 1) - */ -int octeon_get_boot_uart(void) -{ - int uart; -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - uart = 1; -#else - uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? - 1 : 0; -#endif - return uart; -} - -/** - * Get the coremask Linux was booted on. - * - * Returns Core mask - */ -int octeon_get_boot_coremask(void) -{ - return octeon_boot_desc_ptr->core_mask; -} - -/** - * Check the hardware BIST results for a CPU - */ -void octeon_check_cpu_bist(void) -{ - const int coreid = cvmx_get_core_num(); - unsigned long long mask; - unsigned long long bist_val; - - /* Check BIST results for COP0 registers */ - mask = 0x1f00000000ull; - bist_val = read_octeon_c0_icacheerr(); - if (bist_val & mask) - pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", - coreid, bist_val); - - bist_val = read_octeon_c0_dcacheerr(); - if (bist_val & 1) - pr_err("Core%d L1 Dcache parity error: " - "CacheErr(dcache) = 0x%llx\n", - coreid, bist_val); - - mask = 0xfc00000000000000ull; - bist_val = read_c0_cvmmemctl(); - if (bist_val & mask) - pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", - coreid, bist_val); - - write_octeon_c0_dcacheerr(0); -} - -#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB -/** - * Called on every core to setup the wired tlb entry needed - * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set. - * - */ -static void octeon_hal_setup_per_cpu_reserved32(void *unused) -{ - /* - * The config has selected to wire the reserve32 memory for all - * userspace applications. We need to put a wired TLB entry in for each - * 512MB of reserve32 memory. We only handle double 256MB pages here, - * so reserve32 must be multiple of 512MB. - */ - uint32_t size = CONFIG_CAVIUM_RESERVE32; - uint32_t entrylo0 = - 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6); - uint32_t entrylo1 = entrylo0 + (256 << 14); - uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20)); - while (size >= 512) { -#if 0 - pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n", - smp_processor_id(), entryhi); -#endif - add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M); - entrylo0 += 512 << 14; - entrylo1 += 512 << 14; - entryhi += 512 << 20; - size -= 512; - } -} -#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */ - -/** - * Called to release the named block which was used to made sure - * that nobody used the memory for something else during - * init. Now we'll free it so userspace apps can use this - * memory region with bootmem_alloc. - * - * This function is called only once from prom_free_prom_memory(). - */ -void octeon_hal_setup_reserved32(void) -{ -#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB - on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1); -#endif -} - -/** - * Reboot Octeon - * - * @command: Command to pass to the bootloader. Currently ignored. - */ -static void octeon_restart(char *command) -{ - /* Disable all watchdogs before soft reset. They don't get cleared */ -#ifdef CONFIG_SMP - int cpu; - for_each_online_cpu(cpu) - cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); -#else - cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); -#endif - - mb(); - while (1) - cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); -} - - -/** - * Permanently stop a core. - * - * @arg: Ignored. - */ -static void octeon_kill_core(void *arg) -{ - mb(); - if (octeon_is_simulation()) { - /* The simulator needs the watchdog to stop for dead cores */ - cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); - /* A break instruction causes the simulator stop a core */ - asm volatile ("sync\nbreak"); - } -} - - -/** - * Halt the system - */ -static void octeon_halt(void) -{ - smp_call_function(octeon_kill_core, NULL, 0); - - switch (octeon_bootinfo->board_type) { - case CVMX_BOARD_TYPE_NAO38: - /* Driving a 1 to GPIO 12 shuts off this board */ - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); - cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); - break; - default: - octeon_write_lcd("PowerOff"); - break; - } - - octeon_kill_core(NULL); -} - -#if 0 -/** - * Platform time init specifics. - * Returns - */ -void __init plat_time_init(void) -{ - /* Nothing special here, but we are required to have one */ -} - -#endif - -/** - * Handle all the error condition interrupts that might occur. - * - */ -#ifdef CONFIG_CAVIUM_DECODE_RSL -static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) -{ - cvmx_interrupt_rsl_decode(); - return IRQ_HANDLED; -} -#endif - -/** - * Return a string representing the system type - * - * Returns - */ -const char *octeon_board_type_string(void) -{ - static char name[80]; - sprintf(name, "%s (%s)", - cvmx_board_type_to_string(octeon_bootinfo->board_type), - octeon_model_get_string(read_c0_prid())); - return name; -} - -const char *get_system_type(void) - __attribute__ ((alias("octeon_board_type_string"))); - -void octeon_user_io_init(void) -{ - union octeon_cvmemctl cvmmemctl; - union cvmx_iob_fau_timeout fau_timeout; - union cvmx_pow_nw_tim nm_tim; - uint64_t cvmctl; - - /* Get the current settings for CP0_CVMMEMCTL_REG */ - cvmmemctl.u64 = read_c0_cvmmemctl(); - /* R/W If set, marked write-buffer entries time out the same - * as as other entries; if clear, marked write-buffer entries - * use the maximum timeout. */ - cvmmemctl.s.dismarkwblongto = 1; - /* R/W If set, a merged store does not clear the write-buffer - * entry timeout state. */ - cvmmemctl.s.dismrgclrwbto = 0; - /* R/W Two bits that are the MSBs of the resultant CVMSEG LM - * word location for an IOBDMA. The other 8 bits come from the - * SCRADDR field of the IOBDMA. */ - cvmmemctl.s.iobdmascrmsb = 0; - /* R/W If set, SYNCWS and SYNCS only order marked stores; if - * clear, SYNCWS and SYNCS only order unmarked - * stores. SYNCWSMARKED has no effect when DISSYNCWS is - * set. */ - cvmmemctl.s.syncwsmarked = 0; - /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ - cvmmemctl.s.dissyncws = 0; - /* R/W If set, no stall happens on write buffer full. */ - if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) - cvmmemctl.s.diswbfst = 1; - else - cvmmemctl.s.diswbfst = 0; - /* R/W If set (and SX set), supervisor-level loads/stores can - * use XKPHYS addresses with <48>==0 */ - cvmmemctl.s.xkmemenas = 0; - - /* R/W If set (and UX set), user-level loads/stores can use - * XKPHYS addresses with VA<48>==0 */ - cvmmemctl.s.xkmemenau = 0; - - /* R/W If set (and SX set), supervisor-level loads/stores can - * use XKPHYS addresses with VA<48>==1 */ - cvmmemctl.s.xkioenas = 0; - - /* R/W If set (and UX set), user-level loads/stores can use - * XKPHYS addresses with VA<48>==1 */ - cvmmemctl.s.xkioenau = 0; - - /* R/W If set, all stores act as SYNCW (NOMERGE must be set - * when this is set) RW, reset to 0. */ - cvmmemctl.s.allsyncw = 0; - - /* R/W If set, no stores merge, and all stores reach the - * coherent bus in order. */ - cvmmemctl.s.nomerge = 0; - /* R/W Selects the bit in the counter used for DID time-outs 0 - * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is - * between 1x and 2x this interval. For example, with - * DIDTTO=3, expiration interval is between 16K and 32K. */ - cvmmemctl.s.didtto = 0; - /* R/W If set, the (mem) CSR clock never turns off. */ - cvmmemctl.s.csrckalwys = 0; - /* R/W If set, mclk never turns off. */ - cvmmemctl.s.mclkalwys = 0; - /* R/W Selects the bit in the counter used for write buffer - * flush time-outs (WBFLT+11) is the bit position in an - * internal counter used to determine expiration. The write - * buffer expires between 1x and 2x this interval. For - * example, with WBFLT = 0, a write buffer expires between 2K - * and 4K cycles after the write buffer entry is allocated. */ - cvmmemctl.s.wbfltime = 0; - /* R/W If set, do not put Istream in the L2 cache. */ - cvmmemctl.s.istrnol2 = 0; - /* R/W The write buffer threshold. */ - cvmmemctl.s.wbthresh = 10; - /* R/W If set, CVMSEG is available for loads/stores in - * kernel/debug mode. */ -#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 - cvmmemctl.s.cvmsegenak = 1; -#else - cvmmemctl.s.cvmsegenak = 0; -#endif - /* R/W If set, CVMSEG is available for loads/stores in - * supervisor mode. */ - cvmmemctl.s.cvmsegenas = 0; - /* R/W If set, CVMSEG is available for loads/stores in user - * mode. */ - cvmmemctl.s.cvmsegenau = 0; - /* R/W Size of local memory in cache blocks, 54 (6912 bytes) - * is max legal value. */ - cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; - - - if (smp_processor_id() == 0) - pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", - CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, - CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); - - write_c0_cvmmemctl(cvmmemctl.u64); - - /* Move the performance counter interrupts to IRQ 6 */ - cvmctl = read_c0_cvmctl(); - cvmctl &= ~(7 << 7); - cvmctl |= 6 << 7; - write_c0_cvmctl(cvmctl); - - /* Set a default for the hardware timeouts */ - fau_timeout.u64 = 0; - fau_timeout.s.tout_val = 0xfff; - /* Disable tagwait FAU timeout */ - fau_timeout.s.tout_enb = 0; - cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); - - nm_tim.u64 = 0; - /* 4096 cycles */ - nm_tim.s.nw_tim = 3; - cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); - - write_octeon_c0_icacheerr(0); - write_c0_derraddr1(0); -} - -/** - * Early entry point for arch setup - */ -void __init prom_init(void) -{ - struct cvmx_sysinfo *sysinfo; - const int coreid = cvmx_get_core_num(); - int i; - int argc; - struct uart_port octeon_port; -#ifdef CONFIG_CAVIUM_RESERVE32 - int64_t addr = -1; -#endif - /* - * The bootloader passes a pointer to the boot descriptor in - * $a3, this is available as fw_arg3. - */ - octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; - octeon_bootinfo = - cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); - cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); - - /* - * Only enable the LED controller if we're running on a CN38XX, CN58XX, - * or CN56XX. The CN30XX and CN31XX don't have an LED controller. - */ - if (!octeon_is_simulation() && - octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { - cvmx_write_csr(CVMX_LED_EN, 0); - cvmx_write_csr(CVMX_LED_PRT, 0); - cvmx_write_csr(CVMX_LED_DBG, 0); - cvmx_write_csr(CVMX_LED_PRT_FMT, 0); - cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); - cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); - cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); - cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); - cvmx_write_csr(CVMX_LED_EN, 1); - } -#ifdef CONFIG_CAVIUM_RESERVE32 - /* - * We need to temporarily allocate all memory in the reserve32 - * region. This makes sure the kernel doesn't allocate this - * memory when it is getting memory from the - * bootloader. Later, after the memory allocations are - * complete, the reserve32 will be freed. - */ -#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB - if (CONFIG_CAVIUM_RESERVE32 & 0x1ff) - pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. " - "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB " - "is set\n"); - else - addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, - 0, 0, 512 << 20, - "CAVIUM_RESERVE32", 0); -#else - /* - * Allocate memory for RESERVED32 aligned on 2MB boundary. This - * is in case we later use hugetlb entries with it. - */ - addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, - 0, 0, 2 << 20, - "CAVIUM_RESERVE32", 0); -#endif - if (addr < 0) - pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); - else - octeon_reserve32_memory = addr; -#endif - -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 - if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { - pr_info("Skipping L2 locking due to reduced L2 cache size\n"); - } else { - uint32_t ebase = read_c0_ebase() & 0x3ffff000; -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB - /* TLB refill */ - cvmx_l2c_lock_mem_region(ebase, 0x100); -#endif -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION - /* General exception */ - cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); -#endif -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT - /* Interrupt handler */ - cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); -#endif -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT - cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); - cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); -#endif -#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY - cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); -#endif - } -#endif - - sysinfo = cvmx_sysinfo_get(); - memset(sysinfo, 0, sizeof(*sysinfo)); - sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; - sysinfo->phy_mem_desc_ptr = - cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); - sysinfo->core_mask = octeon_bootinfo->core_mask; - sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; - sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; - sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; - sysinfo->board_type = octeon_bootinfo->board_type; - sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; - sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; - memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, - sizeof(sysinfo->mac_addr_base)); - sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; - memcpy(sysinfo->board_serial_number, - octeon_bootinfo->board_serial_number, - sizeof(sysinfo->board_serial_number)); - sysinfo->compact_flash_common_base_addr = - octeon_bootinfo->compact_flash_common_base_addr; - sysinfo->compact_flash_attribute_base_addr = - octeon_bootinfo->compact_flash_attribute_base_addr; - sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; - sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; - sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; - - - octeon_check_cpu_bist(); - - octeon_uart = octeon_get_boot_uart(); - - /* - * Disable All CIU Interrupts. The ones we need will be - * enabled later. Read the SUM register so we know the write - * completed. - */ - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); - -#ifdef CONFIG_SMP - octeon_write_lcd("LinuxSMP"); -#else - octeon_write_lcd("Linux"); -#endif - -#ifdef CONFIG_CAVIUM_GDB - /* - * When debugging the linux kernel, force the cores to enter - * the debug exception handler to break in. - */ - if (octeon_get_boot_debug_flag()) { - cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); - cvmx_read_csr(CVMX_CIU_DINT); - } -#endif - - /* - * BIST should always be enabled when doing a soft reset. L2 - * Cache locking for instance is not cleared unless BIST is - * enabled. Unfortunately due to a chip errata G-200 for - * Cn38XX and CN31XX, BIST msut be disabled on these parts. - */ - if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || - OCTEON_IS_MODEL(OCTEON_CN31XX)) - cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); - else - cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); - - /* Default to 64MB in the simulator to speed things up */ - if (octeon_is_simulation()) - MAX_MEMORY = 64ull << 20; - - arcs_cmdline[0] = 0; - argc = octeon_boot_desc_ptr->argc; - for (i = 0; i < argc; i++) { - const char *arg = - cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); - if ((strncmp(arg, "MEM=", 4) == 0) || - (strncmp(arg, "mem=", 4) == 0)) { - sscanf(arg + 4, "%llu", &MAX_MEMORY); - MAX_MEMORY <<= 20; - if (MAX_MEMORY == 0) - MAX_MEMORY = 32ull << 30; - } else if (strcmp(arg, "ecc_verbose") == 0) { -#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC - __cvmx_interrupt_ecc_report_single_bit_errors = 1; - pr_notice("Reporting of single bit ECC errors is " - "turned on\n"); -#endif - } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < - sizeof(arcs_cmdline) - 1) { - strcat(arcs_cmdline, " "); - strcat(arcs_cmdline, arg); - } - } - - if (strstr(arcs_cmdline, "console=") == NULL) { -#ifdef CONFIG_GDB_CONSOLE - strcat(arcs_cmdline, " console=gdb"); -#else -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - strcat(arcs_cmdline, " console=ttyS0,115200"); -#else - if (octeon_uart == 1) - strcat(arcs_cmdline, " console=ttyS1,115200"); - else - strcat(arcs_cmdline, " console=ttyS0,115200"); -#endif -#endif - } - - if (octeon_is_simulation()) { - /* - * The simulator uses a mtdram device pre filled with - * the filesystem. Also specify the calibration delay - * to avoid calculating it every time. - */ - strcat(arcs_cmdline, " rw root=1f00" - " lpj=60176 slram=root,0x40000000,+1073741824"); - } - - mips_hpt_frequency = octeon_get_clock_rate(); - - octeon_init_cvmcount(); - - _machine_restart = octeon_restart; - _machine_halt = octeon_halt; - - memset(&octeon_port, 0, sizeof(octeon_port)); - /* - * For early_serial_setup we don't set the port type or - * UPF_FIXED_TYPE. - */ - octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ; - octeon_port.iotype = UPIO_MEM; - /* I/O addresses are every 8 bytes */ - octeon_port.regshift = 3; - /* Clock rate of the chip */ - octeon_port.uartclk = mips_hpt_frequency; - octeon_port.fifosize = 64; - octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart); - octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase); - octeon_port.serial_in = octeon_serial_in; - octeon_port.serial_out = octeon_serial_out; -#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL - octeon_port.line = 0; -#else - octeon_port.line = octeon_uart; -#endif - octeon_port.irq = 42 + octeon_uart; - early_serial_setup(&octeon_port); - - octeon_user_io_init(); - register_smp_ops(&octeon_smp_ops); -} - -void __init plat_mem_setup(void) -{ - uint64_t mem_alloc_size; - uint64_t total; - int64_t memory; - - total = 0; - - /* First add the init memory we will be returning. */ - memory = __pa_symbol(&__init_begin) & PAGE_MASK; - mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; - if (mem_alloc_size > 0) { - add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); - total += mem_alloc_size; - } - - /* - * The Mips memory init uses the first memory location for - * some memory vectors. When SPARSEMEM is in use, it doesn't - * verify that the size is big enough for the final - * vectors. Making the smallest chuck 4MB seems to be enough - * to consistantly work. - */ - mem_alloc_size = 4 << 20; - if (mem_alloc_size > MAX_MEMORY) - mem_alloc_size = MAX_MEMORY; - - /* - * When allocating memory, we want incrementing addresses from - * bootmem_alloc so the code in add_memory_region can merge - * regions next to each other. - */ - cvmx_bootmem_lock(); - while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) - && (total < MAX_MEMORY)) { -#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) - memory = cvmx_bootmem_phy_alloc(mem_alloc_size, - __pa_symbol(&__init_end), -1, - 0x100000, - CVMX_BOOTMEM_FLAG_NO_LOCKING); -#elif defined(CONFIG_HIGHMEM) - memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, - 0x100000, - CVMX_BOOTMEM_FLAG_NO_LOCKING); -#else - memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, - 0x100000, - CVMX_BOOTMEM_FLAG_NO_LOCKING); -#endif - if (memory >= 0) { - /* - * This function automatically merges address - * regions next to each other if they are - * received in incrementing order. - */ - add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); - total += mem_alloc_size; - } else { - break; - } - } - cvmx_bootmem_unlock(); - -#ifdef CONFIG_CAVIUM_RESERVE32 - /* - * Now that we've allocated the kernel memory it is safe to - * free the reserved region. We free it here so that builtin - * drivers can use the memory. - */ - if (octeon_reserve32_memory) - cvmx_bootmem_free_named("CAVIUM_RESERVE32"); -#endif /* CONFIG_CAVIUM_RESERVE32 */ - - if (total == 0) - panic("Unable to allocate memory from " - "cvmx_bootmem_phy_alloc\n"); -} - - -int prom_putchar(char c) -{ - uint64_t lsrval; - - /* Spin until there is room */ - do { - lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); - } while ((lsrval & 0x20) == 0); - - /* Write the byte */ - cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c); - return 1; -} - -void prom_free_prom_memory(void) -{ -#ifdef CONFIG_CAVIUM_DECODE_RSL - cvmx_interrupt_rsl_enable(); - - /* Add an interrupt handler for general failures. */ - if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, - "RML/RSL", octeon_rlm_interrupt)) { - panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); - } -#endif - - /* This call is here so that it is performed after any TLB - initializations. It needs to be after these in case the - CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */ - octeon_hal_setup_reserved32(); -} - -static struct octeon_cf_data octeon_cf_data; - -static int __init octeon_cf_device_init(void) -{ - union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; - unsigned long base_ptr, region_base, region_size; - struct platform_device *pd; - struct resource cf_resources[3]; - unsigned int num_resources; - int i; - int ret = 0; - - /* Setup octeon-cf platform device if present. */ - base_ptr = 0; - if (octeon_bootinfo->major_version == 1 - && octeon_bootinfo->minor_version >= 1) { - if (octeon_bootinfo->compact_flash_common_base_addr) - base_ptr = - octeon_bootinfo->compact_flash_common_base_addr; - } else { - base_ptr = 0x1d000800; - } - - if (!base_ptr) - return ret; - - /* Find CS0 region. */ - for (i = 0; i < 8; i++) { - mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i)); - region_base = mio_boot_reg_cfg.s.base << 16; - region_size = (mio_boot_reg_cfg.s.size + 1) << 16; - if (mio_boot_reg_cfg.s.en && base_ptr >= region_base - && base_ptr < region_base + region_size) - break; - } - if (i >= 7) { - /* i and i + 1 are CS0 and CS1, both must be less than 8. */ - goto out; - } - octeon_cf_data.base_region = i; - octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width; - octeon_cf_data.base_region_bias = base_ptr - region_base; - memset(cf_resources, 0, sizeof(cf_resources)); - num_resources = 0; - cf_resources[num_resources].flags = IORESOURCE_MEM; - cf_resources[num_resources].start = region_base; - cf_resources[num_resources].end = region_base + region_size - 1; - num_resources++; - - - if (!(base_ptr & 0xfffful)) { - /* - * Boot loader signals availability of DMA (true_ide - * mode) by setting low order bits of base_ptr to - * zero. - */ - - /* Asume that CS1 immediately follows. */ - mio_boot_reg_cfg.u64 = - cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1)); - region_base = mio_boot_reg_cfg.s.base << 16; - region_size = (mio_boot_reg_cfg.s.size + 1) << 16; - if (!mio_boot_reg_cfg.s.en) - goto out; - - cf_resources[num_resources].flags = IORESOURCE_MEM; - cf_resources[num_resources].start = region_base; - cf_resources[num_resources].end = region_base + region_size - 1; - num_resources++; - - octeon_cf_data.dma_engine = 0; - cf_resources[num_resources].flags = IORESOURCE_IRQ; - cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA; - cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA; - num_resources++; - } else { - octeon_cf_data.dma_engine = -1; - } - - pd = platform_device_alloc("pata_octeon_cf", -1); - if (!pd) { - ret = -ENOMEM; - goto out; - } - pd->dev.platform_data = &octeon_cf_data; - - ret = platform_device_add_resources(pd, cf_resources, num_resources); - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); -out: - return ret; -} -device_initcall(octeon_cf_device_init); diff --git a/trunk/arch/mips/cavium-octeon/smp.c b/trunk/arch/mips/cavium-octeon/smp.c deleted file mode 100644 index 24e0ad63980a..000000000000 --- a/trunk/arch/mips/cavium-octeon/smp.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2008 Cavium Networks - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -volatile unsigned long octeon_processor_boot = 0xff; -volatile unsigned long octeon_processor_sp; -volatile unsigned long octeon_processor_gp; - -static irqreturn_t mailbox_interrupt(int irq, void *dev_id) -{ - const int coreid = cvmx_get_core_num(); - uint64_t action; - - /* Load the mailbox register to figure out what we're supposed to do */ - action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)); - - /* Clear the mailbox to clear the interrupt */ - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); - - if (action & SMP_CALL_FUNCTION) - smp_call_function_interrupt(); - - /* Check if we've been told to flush the icache */ - if (action & SMP_ICACHE_FLUSH) - asm volatile ("synci 0($0)\n"); - return IRQ_HANDLED; -} - -/** - * Cause the function described by call_data to be executed on the passed - * cpu. When the function has finished, increment the finished field of - * call_data. - */ -void octeon_send_ipi_single(int cpu, unsigned int action) -{ - int coreid = cpu_logical_map(cpu); - /* - pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, - coreid, action); - */ - cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); -} - -static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - octeon_send_ipi_single(i, action); -} - -/** - * Detect available CPUs, populate phys_cpu_present_map - */ -static void octeon_smp_setup(void) -{ - const int coreid = cvmx_get_core_num(); - int cpus; - int id; - - int core_mask = octeon_get_boot_coremask(); - - cpus_clear(cpu_possible_map); - __cpu_number_map[coreid] = 0; - __cpu_logical_map[0] = coreid; - cpu_set(0, cpu_possible_map); - - cpus = 1; - for (id = 0; id < 16; id++) { - if ((id != coreid) && (core_mask & (1 << id))) { - cpu_set(cpus, cpu_possible_map); - __cpu_number_map[id] = cpus; - __cpu_logical_map[cpus] = id; - cpus++; - } - } -} - -/** - * Firmware CPU startup hook - * - */ -static void octeon_boot_secondary(int cpu, struct task_struct *idle) -{ - int count; - - pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, - cpu_logical_map(cpu)); - - octeon_processor_sp = __KSTK_TOS(idle); - octeon_processor_gp = (unsigned long)(task_thread_info(idle)); - octeon_processor_boot = cpu_logical_map(cpu); - mb(); - - count = 10000; - while (octeon_processor_sp && count) { - /* Waiting for processor to get the SP and GP */ - udelay(1); - count--; - } - if (count == 0) - pr_err("Secondary boot timeout\n"); -} - -/** - * After we've done initial boot, this function is called to allow the - * board code to clean up state, if needed - */ -static void octeon_init_secondary(void) -{ - const int coreid = cvmx_get_core_num(); - union cvmx_ciu_intx_sum0 interrupt_enable; - - octeon_check_cpu_bist(); - octeon_init_cvmcount(); - /* - pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); - */ - /* Enable Mailbox interrupts to this core. These are the only - interrupts allowed on line 3 */ - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); - interrupt_enable.u64 = 0; - interrupt_enable.s.mbox = 0x3; - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); - cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); - cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); - /* Enable core interrupt processing for 2,3 and 7 */ - set_c0_status(0x8c01); -} - -/** - * Callout to firmware before smp_init - * - */ -void octeon_prepare_cpus(unsigned int max_cpus) -{ - cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); - if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED, - "mailbox0", mailbox_interrupt)) { - panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); - } - if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED, - "mailbox1", mailbox_interrupt)) { - panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); - } -} - -/** - * Last chance for the board code to finish SMP initialization before - * the CPU is "online". - */ -static void octeon_smp_finish(void) -{ -#ifdef CONFIG_CAVIUM_GDB - unsigned long tmp; - /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 - to be not masked by this core so we know the signal is received by - someone */ - asm volatile ("dmfc0 %0, $22\n" - "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); -#endif - - octeon_user_io_init(); - - /* to generate the first CPU timer interrupt */ - write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); -} - -/** - * Hook for after all CPUs are online - */ -static void octeon_cpus_done(void) -{ -#ifdef CONFIG_CAVIUM_GDB - unsigned long tmp; - /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 - to be not masked by this core so we know the signal is received by - someone */ - asm volatile ("dmfc0 %0, $22\n" - "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); -#endif -} - -struct plat_smp_ops octeon_smp_ops = { - .send_ipi_single = octeon_send_ipi_single, - .send_ipi_mask = octeon_send_ipi_mask, - .init_secondary = octeon_init_secondary, - .smp_finish = octeon_smp_finish, - .cpus_done = octeon_cpus_done, - .boot_secondary = octeon_boot_secondary, - .smp_setup = octeon_smp_setup, - .prepare_cpus = octeon_prepare_cpus, -}; diff --git a/trunk/arch/mips/configs/cavium-octeon_defconfig b/trunk/arch/mips/configs/cavium-octeon_defconfig deleted file mode 100644 index 7afaa28a3768..000000000000 --- a/trunk/arch/mips/configs/cavium-octeon_defconfig +++ /dev/null @@ -1,943 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.28-rc6 -# Wed Dec 3 11:00:58 2008 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_BCM47XX is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MACH_EMMA is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SNI_RM is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_WR_PPMC is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y -CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y -# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set -CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y -CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 -CONFIG_CAVIUM_OCTEON_LOCK_L2=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set -CONFIG_CEVT_R4K=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_COHERENT=y -# CONFIG_EARLY_PRINTK is not set -CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_HOTPLUG_CPU is not set -# CONFIG_NO_IOPORT is not set -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_IRQ_CPU_OCTEON=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_MIPS_L1_CACHE_SHIFT=7 - -# -# CPU selection -# -# CONFIG_CPU_LOONGSON2 is not set -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_CAVIUM_OCTEON=y -CONFIG_WEAK_ORDERING=y -CONFIG_WEAK_REORDERING_BEYOND_LLSC=y -CONFIG_CPU_MIPSR2=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -CONFIG_64BIT_PHYS_ADDR=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_IRQ_PER_CPU=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -# CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_SMP=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_NR_CPUS_DEFAULT_16=y -CONFIG_NR_CPUS=16 -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=250 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -# CONFIG_PREEMPT_RCU is not set -# CONFIG_KEXEC is not set -CONFIG_SECCOMP=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -# CONFIG_PCSPKR_PLATFORM is not set -CONFIG_COMPAT_BRK=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_USE_GENERIC_SMP_HELPERS=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y -CONFIG_STOP_MACHINE=y -CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -CONFIG_BLOCK_COMPAT=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y -# CONFIG_PROBE_INITRD_HEADER is not set -# CONFIG_FREEZER is not set - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_MMU=y -# CONFIG_PCCARD is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETLABEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set -CONFIG_FIB_RULES=y -# CONFIG_WIRELESS is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x8000000 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_ONENAND is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -CONFIG_NETDEV_1000=y -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_SOUND is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set -CONFIG_STAGING_EXCLUDE_BUILD=y - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=2048 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -CONFIG_DEBUG_SPINLOCK=y -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y - -# -# Tracers -# -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_CMDLINE="" -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_RUNTIME_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set -CONFIG_SECURITY_NETWORK=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_MANAGER=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/trunk/arch/mips/include/asm/cpu-features.h b/trunk/arch/mips/include/asm/cpu-features.h index a0d14f85b781..12d12dfe73c0 100644 --- a/trunk/arch/mips/include/asm/cpu-features.h +++ b/trunk/arch/mips/include/asm/cpu-features.h @@ -38,9 +38,6 @@ #ifndef cpu_has_tx39_cache #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) #endif -#ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 -#endif #ifndef cpu_has_fpu #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) diff --git a/trunk/arch/mips/include/asm/cpu.h b/trunk/arch/mips/include/asm/cpu.h index c018727c7ddc..229a786101d9 100644 --- a/trunk/arch/mips/include/asm/cpu.h +++ b/trunk/arch/mips/include/asm/cpu.h @@ -33,7 +33,6 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 -#define PRID_COMP_CAVIUM 0x0d0000 /* @@ -114,18 +113,6 @@ #define PRID_IMP_BCM4710 0x4000 #define PRID_IMP_BCM3302 0x9000 -/* - * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM - */ - -#define PRID_IMP_CAVIUM_CN38XX 0x0000 -#define PRID_IMP_CAVIUM_CN31XX 0x0100 -#define PRID_IMP_CAVIUM_CN30XX 0x0200 -#define PRID_IMP_CAVIUM_CN58XX 0x0300 -#define PRID_IMP_CAVIUM_CN56XX 0x0400 -#define PRID_IMP_CAVIUM_CN50XX 0x0600 -#define PRID_IMP_CAVIUM_CN52XX 0x0700 - /* * Definitions for 7:0 on legacy processors */ @@ -216,7 +203,6 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_LAST }; diff --git a/trunk/arch/mips/include/asm/hazards.h b/trunk/arch/mips/include/asm/hazards.h index 43baed16a109..2de638f84c86 100644 --- a/trunk/arch/mips/include/asm/hazards.h +++ b/trunk/arch/mips/include/asm/hazards.h @@ -42,7 +42,7 @@ ASMMACRO(_ehb, /* * TLB hazards */ -#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON) +#if defined(CONFIG_CPU_MIPSR2) /* * MIPSR2 defines ehb for hazard avoidance @@ -138,7 +138,7 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) +#elif defined(CONFIG_CPU_R10000) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. diff --git a/trunk/arch/mips/include/asm/io.h b/trunk/arch/mips/include/asm/io.h index 436878e4e063..501a40b9f18d 100644 --- a/trunk/arch/mips/include/asm/io.h +++ b/trunk/arch/mips/include/asm/io.h @@ -295,12 +295,6 @@ static inline void iounmap(const volatile void __iomem *addr) #undef __IS_KSEG1 } -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define war_octeon_io_reorder_wmb() wmb() -#else -#define war_octeon_io_reorder_wmb() do { } while (0) -#endif - #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ \ static inline void pfx##write##bwlq(type val, \ @@ -309,8 +303,6 @@ static inline void pfx##write##bwlq(type val, \ volatile type *__mem; \ type __val; \ \ - war_octeon_io_reorder_wmb(); \ - \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ __val = pfx##ioswab##bwlq(__mem, val); \ @@ -378,8 +370,6 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ volatile type *__addr; \ type __val; \ \ - war_octeon_io_reorder_wmb(); \ - \ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ @@ -514,12 +504,8 @@ BUILDSTRING(q, u64) #endif -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define mmiowb() wmb() -#else /* Depends on MIPS II instruction set */ #define mmiowb() asm volatile ("sync" ::: "memory") -#endif static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { diff --git a/trunk/arch/mips/include/asm/mach-au1x00/au1000.h b/trunk/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f50b5b5..0d302bad4492 100644 --- a/trunk/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/trunk/arch/mips/include/asm/mach-au1x00/au1000.h @@ -91,57 +91,14 @@ static inline u32 au_readl(unsigned long reg) return *(volatile u32 *)reg; } -/* Early Au1000 have a write-only SYS_CPUPLL register. */ -static inline int au1xxx_cpu_has_pll_wo(void) -{ - switch (read_c0_prid()) { - case 0x00030100: /* Au1000 DA */ - case 0x00030201: /* Au1000 HA */ - case 0x00030202: /* Au1000 HB */ - return 1; - } - return 0; -} - -/* does CPU need CONFIG[OD] set to fix tons of errata? */ -static inline int au1xxx_cpu_needs_config_od(void) -{ - /* - * c0_config.od (bit 19) was write only (and read as 0) on the - * early revisions of Alchemy SOCs. It disables the bus trans- - * action overlapping and needs to be set to fix various errata. - */ - switch (read_c0_prid()) { - case 0x00030100: /* Au1000 DA */ - case 0x00030201: /* Au1000 HA */ - case 0x00030202: /* Au1000 HB */ - case 0x01030200: /* Au1500 AB */ - /* - * Au1100/Au1200 errata actually keep silence about this bit, - * so we set it just in case for those revisions that require - * it to be set according to the (now gone) cpu_table. - */ - case 0x02030200: /* Au1100 AB */ - case 0x02030201: /* Au1100 BA */ - case 0x02030202: /* Au1100 BC */ - case 0x04030201: /* Au1200 AC */ - return 1; - } - return 0; -} /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); -extern unsigned long au1xxx_calc_clock(void); - -/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ -void au1xxx_save_and_sleep(void); -void au_sleep(void); -void save_au1xxx_intctl(void); -void restore_au1xxx_intctl(void); +extern void set_au1x00_lcd_clock(void); +extern unsigned int get_au1x00_lcd_clock(void); /* * Every board describes its IRQ mapping with this table. @@ -152,11 +109,10 @@ struct au1xxx_irqmap { int im_request; }; -/* core calls this function to let boards initialize other IRQ sources */ -void board_init_irq(void); - -/* boards call this to register additional (GPIO) interrupts */ -void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); +/* + * init_IRQ looks for a table with this name. + */ +extern struct au1xxx_irqmap au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ @@ -549,6 +505,15 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); #define IC1_TESTBIT 0xB1800080 +/* Interrupt Configuration Modes */ +#define INTC_INT_DISABLED 0x0 +#define INTC_INT_RISE_EDGE 0x1 +#define INTC_INT_FALL_EDGE 0x2 +#define INTC_INT_RISE_AND_FALL_EDGE 0x3 +#define INTC_INT_HIGH_LEVEL 0x5 +#define INTC_INT_LOW_LEVEL 0x6 +#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 + /* Interrupt Numbers */ /* Au1000 */ #ifdef CONFIG_SOC_AU1000 @@ -1560,10 +1525,6 @@ enum soc_au1200_ints { #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C -#define SYS_WAKEMSK_D2 (1 << 9) -#define SYS_WAKEMSK_M2 (1 << 8) -#define SYS_WAKEMSK_GPIO(x) (1 << (x)) - /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 # define SYS_FC_FRDIV2_BIT 22 @@ -1788,4 +1749,24 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; #endif +/* + * Processor information based on PRID. + * Copied from PowerPC. + */ +#ifndef _LANGUAGE_ASSEMBLY +struct cpu_spec { + /* CPU is matched via (PRID & prid_mask) == prid_value */ + unsigned int prid_mask; + unsigned int prid_value; + + char *cpu_name; + unsigned char cpu_od; /* Set Config[OD] */ + unsigned char cpu_bclk; /* Enable BCLK switching */ + unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ +}; + +extern struct cpu_spec cpu_specs[]; +extern struct cpu_spec *cur_cpu_spec[]; +#endif + #endif diff --git a/trunk/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/trunk/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 06f68f43800a..44a67bf05dc1 100644 --- a/trunk/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/trunk/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -357,11 +357,6 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr); u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); extern void au1xxx_ddma_del_device(u32 devid); void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); -#ifdef CONFIG_PM -void au1xxx_dbdma_suspend(void); -void au1xxx_dbdma_resume(void); -#endif - /* * Some compatibilty macros -- needed to make changes to API diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h deleted file mode 100644 index 04ce6e6569da..000000000000 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Cavium Networks - */ -#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H - -#include -#include - -/* - * Cavium Octeons are MIPS64v2 processors - */ -#define cpu_dcache_line_size() 128 -#define cpu_icache_line_size() 128 - - -#define cpu_has_4kex 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 0 -#define cpu_has_tx39_cache 0 -#define cpu_has_fpu 0 -#define cpu_has_counter 1 -#define cpu_has_watch 1 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 - -/* - * We should disable LL/SC on non SMP systems as it is faster to - * disable interrupts for atomic access than a LL/SC. Unfortunatly we - * cannot as this breaks asm/futex.h - */ -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 1 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_64bits 1 -#define cpu_has_octeon_cache 1 -#define cpu_has_saa octeon_has_saa() -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 1 -#define cpu_has_dsp 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 -#define cpu_has_vint 0 -#define cpu_has_veic 0 -#define ARCH_HAS_READ_CURRENT_TIMER 1 -#define ARCH_HAS_IRQ_PER_CPU 1 -#define ARCH_HAS_SPINLOCK_PREFETCH 1 -#define spin_lock_prefetch(x) prefetch(x) -#define PREFETCH_STRIDE 128 - -static inline int read_current_timer(unsigned long *result) -{ - asm volatile ("rdhwr %0,$31\n" -#ifndef CONFIG_64BIT - "\tsll %0, 0" -#endif - : "=r" (*result)); - return 0; -} - -static inline int octeon_has_saa(void) -{ - int id; - asm volatile ("mfc0 %0, $15,0" : "=r" (id)); - return id >= 0x000d0300; -} - -#endif diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h deleted file mode 100644 index f30fce92aabb..000000000000 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle - * - * - * Similar to mach-generic/dma-coherence.h except - * plat_device_is_coherent hard coded to return 1. - * - */ -#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H -#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H - -struct device; - -dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t); -void octeon_unmap_dma_mem(struct device *, dma_addr_t); - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - return octeon_map_dma_mem(dev, addr, size); -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); -} - -static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) -{ - return dma_addr; -} - -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) -{ - octeon_unmap_dma_mem(dev, dma_addr); -} - -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - mb(); -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 1; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return dma_addr == -1; -} - -#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */ diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h deleted file mode 100644 index d32220fbf4f1..000000000000 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2008 Cavium Networks - */ -#ifndef __OCTEON_IRQ_H__ -#define __OCTEON_IRQ_H__ - -#define NR_IRQS OCTEON_IRQ_LAST -#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 - -/* 0 - 7 represent the i8259 master */ -#define OCTEON_IRQ_I8259M0 0 -#define OCTEON_IRQ_I8259M1 1 -#define OCTEON_IRQ_I8259M2 2 -#define OCTEON_IRQ_I8259M3 3 -#define OCTEON_IRQ_I8259M4 4 -#define OCTEON_IRQ_I8259M5 5 -#define OCTEON_IRQ_I8259M6 6 -#define OCTEON_IRQ_I8259M7 7 -/* 8 - 15 represent the i8259 slave */ -#define OCTEON_IRQ_I8259S0 8 -#define OCTEON_IRQ_I8259S1 9 -#define OCTEON_IRQ_I8259S2 10 -#define OCTEON_IRQ_I8259S3 11 -#define OCTEON_IRQ_I8259S4 12 -#define OCTEON_IRQ_I8259S5 13 -#define OCTEON_IRQ_I8259S6 14 -#define OCTEON_IRQ_I8259S7 15 -/* 16 - 23 represent the 8 MIPS standard interrupt sources */ -#define OCTEON_IRQ_SW0 16 -#define OCTEON_IRQ_SW1 17 -#define OCTEON_IRQ_CIU0 18 -#define OCTEON_IRQ_CIU1 19 -#define OCTEON_IRQ_CIU4 20 -#define OCTEON_IRQ_5 21 -#define OCTEON_IRQ_PERF 22 -#define OCTEON_IRQ_TIMER 23 -/* 24 - 87 represent the sources in CIU_INTX_EN0 */ -#define OCTEON_IRQ_WORKQ0 24 -#define OCTEON_IRQ_WORKQ1 25 -#define OCTEON_IRQ_WORKQ2 26 -#define OCTEON_IRQ_WORKQ3 27 -#define OCTEON_IRQ_WORKQ4 28 -#define OCTEON_IRQ_WORKQ5 29 -#define OCTEON_IRQ_WORKQ6 30 -#define OCTEON_IRQ_WORKQ7 31 -#define OCTEON_IRQ_WORKQ8 32 -#define OCTEON_IRQ_WORKQ9 33 -#define OCTEON_IRQ_WORKQ10 34 -#define OCTEON_IRQ_WORKQ11 35 -#define OCTEON_IRQ_WORKQ12 36 -#define OCTEON_IRQ_WORKQ13 37 -#define OCTEON_IRQ_WORKQ14 38 -#define OCTEON_IRQ_WORKQ15 39 -#define OCTEON_IRQ_GPIO0 40 -#define OCTEON_IRQ_GPIO1 41 -#define OCTEON_IRQ_GPIO2 42 -#define OCTEON_IRQ_GPIO3 43 -#define OCTEON_IRQ_GPIO4 44 -#define OCTEON_IRQ_GPIO5 45 -#define OCTEON_IRQ_GPIO6 46 -#define OCTEON_IRQ_GPIO7 47 -#define OCTEON_IRQ_GPIO8 48 -#define OCTEON_IRQ_GPIO9 49 -#define OCTEON_IRQ_GPIO10 50 -#define OCTEON_IRQ_GPIO11 51 -#define OCTEON_IRQ_GPIO12 52 -#define OCTEON_IRQ_GPIO13 53 -#define OCTEON_IRQ_GPIO14 54 -#define OCTEON_IRQ_GPIO15 55 -#define OCTEON_IRQ_MBOX0 56 -#define OCTEON_IRQ_MBOX1 57 -#define OCTEON_IRQ_UART0 58 -#define OCTEON_IRQ_UART1 59 -#define OCTEON_IRQ_PCI_INT0 60 -#define OCTEON_IRQ_PCI_INT1 61 -#define OCTEON_IRQ_PCI_INT2 62 -#define OCTEON_IRQ_PCI_INT3 63 -#define OCTEON_IRQ_PCI_MSI0 64 -#define OCTEON_IRQ_PCI_MSI1 65 -#define OCTEON_IRQ_PCI_MSI2 66 -#define OCTEON_IRQ_PCI_MSI3 67 -#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ -#define OCTEON_IRQ_TWSI 69 -#define OCTEON_IRQ_RML 70 -#define OCTEON_IRQ_TRACE 71 -#define OCTEON_IRQ_GMX_DRP0 72 -#define OCTEON_IRQ_GMX_DRP1 73 -#define OCTEON_IRQ_IPD_DRP 74 -#define OCTEON_IRQ_KEY_ZERO 75 -#define OCTEON_IRQ_TIMER0 76 -#define OCTEON_IRQ_TIMER1 77 -#define OCTEON_IRQ_TIMER2 78 -#define OCTEON_IRQ_TIMER3 79 -#define OCTEON_IRQ_USB0 80 -#define OCTEON_IRQ_PCM 81 -#define OCTEON_IRQ_MPI 82 -#define OCTEON_IRQ_TWSI2 83 -#define OCTEON_IRQ_POWIQ 84 -#define OCTEON_IRQ_IPDPPTHR 85 -#define OCTEON_IRQ_MII0 86 -#define OCTEON_IRQ_BOOTDMA 87 -/* 88 - 151 represent the sources in CIU_INTX_EN1 */ -#define OCTEON_IRQ_WDOG0 88 -#define OCTEON_IRQ_WDOG1 89 -#define OCTEON_IRQ_WDOG2 90 -#define OCTEON_IRQ_WDOG3 91 -#define OCTEON_IRQ_WDOG4 92 -#define OCTEON_IRQ_WDOG5 93 -#define OCTEON_IRQ_WDOG6 94 -#define OCTEON_IRQ_WDOG7 95 -#define OCTEON_IRQ_WDOG8 96 -#define OCTEON_IRQ_WDOG9 97 -#define OCTEON_IRQ_WDOG10 98 -#define OCTEON_IRQ_WDOG11 99 -#define OCTEON_IRQ_WDOG12 100 -#define OCTEON_IRQ_WDOG13 101 -#define OCTEON_IRQ_WDOG14 102 -#define OCTEON_IRQ_WDOG15 103 -#define OCTEON_IRQ_UART2 104 -#define OCTEON_IRQ_USB1 105 -#define OCTEON_IRQ_MII1 106 -#define OCTEON_IRQ_RESERVED107 107 -#define OCTEON_IRQ_RESERVED108 108 -#define OCTEON_IRQ_RESERVED109 109 -#define OCTEON_IRQ_RESERVED110 110 -#define OCTEON_IRQ_RESERVED111 111 -#define OCTEON_IRQ_RESERVED112 112 -#define OCTEON_IRQ_RESERVED113 113 -#define OCTEON_IRQ_RESERVED114 114 -#define OCTEON_IRQ_RESERVED115 115 -#define OCTEON_IRQ_RESERVED116 116 -#define OCTEON_IRQ_RESERVED117 117 -#define OCTEON_IRQ_RESERVED118 118 -#define OCTEON_IRQ_RESERVED119 119 -#define OCTEON_IRQ_RESERVED120 120 -#define OCTEON_IRQ_RESERVED121 121 -#define OCTEON_IRQ_RESERVED122 122 -#define OCTEON_IRQ_RESERVED123 123 -#define OCTEON_IRQ_RESERVED124 124 -#define OCTEON_IRQ_RESERVED125 125 -#define OCTEON_IRQ_RESERVED126 126 -#define OCTEON_IRQ_RESERVED127 127 -#define OCTEON_IRQ_RESERVED128 128 -#define OCTEON_IRQ_RESERVED129 129 -#define OCTEON_IRQ_RESERVED130 130 -#define OCTEON_IRQ_RESERVED131 131 -#define OCTEON_IRQ_RESERVED132 132 -#define OCTEON_IRQ_RESERVED133 133 -#define OCTEON_IRQ_RESERVED134 134 -#define OCTEON_IRQ_RESERVED135 135 -#define OCTEON_IRQ_RESERVED136 136 -#define OCTEON_IRQ_RESERVED137 137 -#define OCTEON_IRQ_RESERVED138 138 -#define OCTEON_IRQ_RESERVED139 139 -#define OCTEON_IRQ_RESERVED140 140 -#define OCTEON_IRQ_RESERVED141 141 -#define OCTEON_IRQ_RESERVED142 142 -#define OCTEON_IRQ_RESERVED143 143 -#define OCTEON_IRQ_RESERVED144 144 -#define OCTEON_IRQ_RESERVED145 145 -#define OCTEON_IRQ_RESERVED146 146 -#define OCTEON_IRQ_RESERVED147 147 -#define OCTEON_IRQ_RESERVED148 148 -#define OCTEON_IRQ_RESERVED149 149 -#define OCTEON_IRQ_RESERVED150 150 -#define OCTEON_IRQ_RESERVED151 151 - -#ifdef CONFIG_PCI_MSI -/* 152 - 215 represent the MSI interrupts 0-63 */ -#define OCTEON_IRQ_MSI_BIT0 152 -#define OCTEON_IRQ_MSI_BIT1 153 -#define OCTEON_IRQ_MSI_BIT2 154 -#define OCTEON_IRQ_MSI_BIT3 155 -#define OCTEON_IRQ_MSI_BIT4 156 -#define OCTEON_IRQ_MSI_BIT5 157 -#define OCTEON_IRQ_MSI_BIT6 158 -#define OCTEON_IRQ_MSI_BIT7 159 -#define OCTEON_IRQ_MSI_BIT8 160 -#define OCTEON_IRQ_MSI_BIT9 161 -#define OCTEON_IRQ_MSI_BIT10 162 -#define OCTEON_IRQ_MSI_BIT11 163 -#define OCTEON_IRQ_MSI_BIT12 164 -#define OCTEON_IRQ_MSI_BIT13 165 -#define OCTEON_IRQ_MSI_BIT14 166 -#define OCTEON_IRQ_MSI_BIT15 167 -#define OCTEON_IRQ_MSI_BIT16 168 -#define OCTEON_IRQ_MSI_BIT17 169 -#define OCTEON_IRQ_MSI_BIT18 170 -#define OCTEON_IRQ_MSI_BIT19 171 -#define OCTEON_IRQ_MSI_BIT20 172 -#define OCTEON_IRQ_MSI_BIT21 173 -#define OCTEON_IRQ_MSI_BIT22 174 -#define OCTEON_IRQ_MSI_BIT23 175 -#define OCTEON_IRQ_MSI_BIT24 176 -#define OCTEON_IRQ_MSI_BIT25 177 -#define OCTEON_IRQ_MSI_BIT26 178 -#define OCTEON_IRQ_MSI_BIT27 179 -#define OCTEON_IRQ_MSI_BIT28 180 -#define OCTEON_IRQ_MSI_BIT29 181 -#define OCTEON_IRQ_MSI_BIT30 182 -#define OCTEON_IRQ_MSI_BIT31 183 -#define OCTEON_IRQ_MSI_BIT32 184 -#define OCTEON_IRQ_MSI_BIT33 185 -#define OCTEON_IRQ_MSI_BIT34 186 -#define OCTEON_IRQ_MSI_BIT35 187 -#define OCTEON_IRQ_MSI_BIT36 188 -#define OCTEON_IRQ_MSI_BIT37 189 -#define OCTEON_IRQ_MSI_BIT38 190 -#define OCTEON_IRQ_MSI_BIT39 191 -#define OCTEON_IRQ_MSI_BIT40 192 -#define OCTEON_IRQ_MSI_BIT41 193 -#define OCTEON_IRQ_MSI_BIT42 194 -#define OCTEON_IRQ_MSI_BIT43 195 -#define OCTEON_IRQ_MSI_BIT44 196 -#define OCTEON_IRQ_MSI_BIT45 197 -#define OCTEON_IRQ_MSI_BIT46 198 -#define OCTEON_IRQ_MSI_BIT47 199 -#define OCTEON_IRQ_MSI_BIT48 200 -#define OCTEON_IRQ_MSI_BIT49 201 -#define OCTEON_IRQ_MSI_BIT50 202 -#define OCTEON_IRQ_MSI_BIT51 203 -#define OCTEON_IRQ_MSI_BIT52 204 -#define OCTEON_IRQ_MSI_BIT53 205 -#define OCTEON_IRQ_MSI_BIT54 206 -#define OCTEON_IRQ_MSI_BIT55 207 -#define OCTEON_IRQ_MSI_BIT56 208 -#define OCTEON_IRQ_MSI_BIT57 209 -#define OCTEON_IRQ_MSI_BIT58 210 -#define OCTEON_IRQ_MSI_BIT59 211 -#define OCTEON_IRQ_MSI_BIT60 212 -#define OCTEON_IRQ_MSI_BIT61 213 -#define OCTEON_IRQ_MSI_BIT62 214 -#define OCTEON_IRQ_MSI_BIT63 215 - -#define OCTEON_IRQ_LAST 216 -#else -#define OCTEON_IRQ_LAST 152 -#endif - -#endif diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h deleted file mode 100644 index 0b2b5eb22e9b..000000000000 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005-2008 Cavium Networks, Inc - */ -#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H -#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H - - -#define CP0_CYCLE_COUNTER $9, 6 -#define CP0_CVMCTL_REG $9, 7 -#define CP0_CVMMEMCTL_REG $11,7 -#define CP0_PRID_REG $15, 0 -#define CP0_PRID_OCTEON_PASS1 0x000d0000 -#define CP0_PRID_OCTEON_CN30XX 0x000d0200 - -.macro kernel_entry_setup - # Registers set by bootloader: - # (only 32 bits set by bootloader, all addresses are physical - # addresses, and need to have the appropriate memory region set - # by the kernel - # a0 = argc - # a1 = argv (kseg0 compat addr) - # a2 = 1 if init core, zero otherwise - # a3 = address of boot descriptor block - .set push - .set arch=octeon - # Read the cavium mem control register - dmfc0 v0, CP0_CVMMEMCTL_REG - # Clear the lower 6 bits, the CVMSEG size - dins v0, $0, 0, 6 - ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE - dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register - dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register -#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED - # Disable unaligned load/store support but leave HW fixup enabled - or v0, v0, 0x5001 - xor v0, v0, 0x1001 -#else - # Disable unaligned load/store and HW fixup support - or v0, v0, 0x5001 - xor v0, v0, 0x5001 -#endif - # Read the processor ID register - mfc0 v1, CP0_PRID_REG - # Disable instruction prefetching (Octeon Pass1 errata) - or v0, v0, 0x2000 - # Skip reenable of prefetching for Octeon Pass1 - beq v1, CP0_PRID_OCTEON_PASS1, skip - nop - # Reenable instruction prefetching, not on Pass1 - xor v0, v0, 0x2000 - # Strip off pass number off of processor id - srl v1, 8 - sll v1, 8 - # CN30XX needs some extra stuff turned off for better performance - bne v1, CP0_PRID_OCTEON_CN30XX, skip - nop - # CN30XX Use random Icache replacement - or v0, v0, 0x400 - # CN30XX Disable instruction prefetching - or v0, v0, 0x2000 -skip: - # Write the cavium control register - dmtc0 v0, CP0_CVMCTL_REG - sync - # Flush dcache after config change - cache 9, 0($0) - # Get my core id - rdhwr v0, $0 - # Jump the master to kernel_entry - bne a2, zero, octeon_main_processor - nop - -#ifdef CONFIG_SMP - - # - # All cores other than the master need to wait here for SMP bootstrap - # to begin - # - - # This is the variable where the next core to boot os stored - PTR_LA t0, octeon_processor_boot -octeon_spin_wait_boot: - # Get the core id of the next to be booted - LONG_L t1, (t0) - # Keep looping if it isn't me - bne t1, v0, octeon_spin_wait_boot - nop - # Get my GP from the global variable - PTR_LA t0, octeon_processor_gp - LONG_L gp, (t0) - # Get my SP from the global variable - PTR_LA t0, octeon_processor_sp - LONG_L sp, (t0) - # Set the SP global variable to zero so the master knows we've started - LONG_S zero, (t0) -#ifdef __OCTEON__ - syncw - syncw -#else - sync -#endif - # Jump to the normal Linux SMP entry point - j smp_bootstrap - nop -#else /* CONFIG_SMP */ - - # - # Someone tried to boot SMP with a non SMP kernel. All extra cores - # will halt here. - # -octeon_wait_forever: - wait - b octeon_wait_forever - nop - -#endif /* CONFIG_SMP */ -octeon_main_processor: - .set pop -.endm - -/* - * Do SMP slave processor setup necessary before we can savely execute C code. - */ - .macro smp_slave_setup - .endm - -#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */ diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/war.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/war.h deleted file mode 100644 index c4712d7cc81d..000000000000 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/war.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - * Copyright (C) 2008 Cavium Networks - */ -#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H -#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */ diff --git a/trunk/arch/mips/include/asm/mach-generic/dma-coherence.h b/trunk/arch/mips/include/asm/mach-generic/dma-coherence.h index 36c611b6c597..76e04e7feb84 100644 --- a/trunk/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -28,34 +28,10 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) return dma_addr; } -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) { } -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { #ifdef CONFIG_DMA_COHERENT diff --git a/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h b/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h index 4c21bfca10c3..ed7e6222dc15 100644 --- a/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-ip27/dma-coherence.h @@ -38,34 +38,10 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) return dma_addr & ~(0xffUL << 56); } -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) { } -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 1; /* IP27 non-cohernet mode is unsupported */ diff --git a/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h b/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h index 7ae40f4b1c80..a5511ebb2d53 100644 --- a/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-ip32/dma-coherence.h @@ -60,34 +60,10 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) return addr; } -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) { } -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; /* IP32 is non-cohernet */ diff --git a/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h b/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h index 1c7cd27efa7b..d66979a124a8 100644 --- a/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-jazz/dma-coherence.h @@ -27,35 +27,11 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) return vdma_log2phys(dma_addr); } -static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static void plat_unmap_dma_mem(dma_addr_t dma_addr) { vdma_free(dma_addr); } -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/trunk/arch/mips/include/asm/mach-lemote/dma-coherence.h b/trunk/arch/mips/include/asm/mach-lemote/dma-coherence.h index 38fad7dfe7da..7e914777ebc4 100644 --- a/trunk/arch/mips/include/asm/mach-lemote/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-lemote/dma-coherence.h @@ -30,34 +30,10 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) return dma_addr & 0x7fffffff; } -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) { } -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - static inline int plat_device_is_coherent(struct device *dev) { return 0; diff --git a/trunk/arch/mips/include/asm/mipsregs.h b/trunk/arch/mips/include/asm/mipsregs.h index 0417516503f6..9316324d070d 100644 --- a/trunk/arch/mips/include/asm/mipsregs.h +++ b/trunk/arch/mips/include/asm/mipsregs.h @@ -1000,26 +1000,6 @@ do { \ #define read_c0_ebase() __read_32bit_c0_register($15, 1) #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -/* Cavium OCTEON (cnMIPS) */ -#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) -#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) - -#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) -#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) - -#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) -#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) -/* - * The cacheerr registers are not standardized. On OCTEON, they are - * 64 bits wide. - */ -#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) -#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) - -#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) -#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) - /* * Macros to access the floating point coprocessor control registers */ @@ -1028,8 +1008,6 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ ".set\tpop" \ : "=r" (__res)); \ diff --git a/trunk/arch/mips/include/asm/module.h b/trunk/arch/mips/include/asm/module.h index d94085a3eafb..e2e09b2cd265 100644 --- a/trunk/arch/mips/include/asm/module.h +++ b/trunk/arch/mips/include/asm/module.h @@ -116,8 +116,6 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "SB1 " #elif defined CONFIG_CPU_LOONGSON2 #define MODULE_PROC_FAMILY "LOONGSON2 " -#elif defined CONFIG_CPU_CAVIUM_OCTEON -#define MODULE_PROC_FAMILY "OCTEON " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-asm.h b/trunk/arch/mips/include/asm/octeon/cvmx-asm.h deleted file mode 100644 index b21d3fc1ef91..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-asm.h +++ /dev/null @@ -1,128 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * This is file defines ASM primitives for the executive. - */ -#ifndef __CVMX_ASM_H__ -#define __CVMX_ASM_H__ - -#include "octeon-model.h" - -/* other useful stuff */ -#define CVMX_SYNC asm volatile ("sync" : : : "memory") -/* String version of SYNCW macro for using in inline asm constructs */ -#define CVMX_SYNCW_STR "syncw\nsyncw\n" -#ifdef __OCTEON__ - -/* Deprecated, will be removed in future release */ -#define CVMX_SYNCIO asm volatile ("nop") - -#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory") - -/* Deprecated, will be removed in future release */ -#define CVMX_SYNCIOALL asm volatile ("nop") - -/* - * We actually use two syncw instructions in a row when we need a write - * memory barrier. This is because the CN3XXX series of Octeons have - * errata Core-401. This can cause a single syncw to not enforce - * ordering under very rare conditions. Even if it is rare, better safe - * than sorry. - */ -#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory") - -/* - * Define new sync instructions to be normal SYNC instructions for - * operating systems that use threads. - */ -#define CVMX_SYNCWS CVMX_SYNCW -#define CVMX_SYNCS CVMX_SYNC -#define CVMX_SYNCWS_STR CVMX_SYNCW_STR -#else -/* - * Not using a Cavium compiler, always use the slower sync so the - * assembler stays happy. - */ -/* Deprecated, will be removed in future release */ -#define CVMX_SYNCIO asm volatile ("nop") - -#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory") - -/* Deprecated, will be removed in future release */ -#define CVMX_SYNCIOALL asm volatile ("nop") - -#define CVMX_SYNCW asm volatile ("sync" : : : "memory") -#define CVMX_SYNCWS CVMX_SYNCW -#define CVMX_SYNCS CVMX_SYNC -#define CVMX_SYNCWS_STR CVMX_SYNCW_STR -#endif - -/* - * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable - * (actually old value or zero) until that byte is stored to (by this or - * another processor. Note that the value of each byte is not only - * unpredictable, but may also change again - up until the point when one - * of the cores stores to the byte. - */ -#define CVMX_PREPARE_FOR_STORE(address, offset) \ - asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ - [rbase] "d" (address)) -/* - * This is a command headed to the L2 controller to tell it to clear - * its dirty bit for a block. Basically, SW is telling HW that the - * current version of the block will not be used. - */ -#define CVMX_DONT_WRITE_BACK(address, offset) \ - asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ - [rbase] "d" (address)) - -/* flush stores, invalidate entire icache */ -#define CVMX_ICACHE_INVALIDATE \ - { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } - -/* flush stores, invalidate entire icache */ -#define CVMX_ICACHE_INVALIDATE2 \ - { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } - -/* complete prefetches, invalidate entire dcache */ -#define CVMX_DCACHE_INVALIDATE \ - { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } - - -#define CVMX_POP(result, input) \ - asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) -#define CVMX_DPOP(result, input) \ - asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) - -/* some new cop0-like stuff */ -#define CVMX_RDHWR(result, regstr) \ - asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) -#define CVMX_RDHWRNV(result, regstr) \ - asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) -#endif /* __CVMX_ASM_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/trunk/arch/mips/include/asm/octeon/cvmx-bootinfo.h deleted file mode 100644 index 692989acd8a9..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ /dev/null @@ -1,262 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Header file containing the ABI with the bootloader. - */ - -#ifndef __CVMX_BOOTINFO_H__ -#define __CVMX_BOOTINFO_H__ - -/* - * Current major and minor versions of the CVMX bootinfo block that is - * passed from the bootloader to the application. This is versioned - * so that applications can properly handle multiple bootloader - * versions. - */ -#define CVMX_BOOTINFO_MAJ_VER 1 -#define CVMX_BOOTINFO_MIN_VER 2 - -#if (CVMX_BOOTINFO_MAJ_VER == 1) -#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 -/* - * This structure is populated by the bootloader. For binary - * compatibility the only changes that should be made are - * adding members to the end of the structure, and the minor - * version should be incremented at that time. - * If an incompatible change is made, the major version - * must be incremented, and the minor version should be reset - * to 0. - */ -struct cvmx_bootinfo { - uint32_t major_version; - uint32_t minor_version; - - uint64_t stack_top; - uint64_t heap_base; - uint64_t heap_end; - uint64_t desc_vaddr; - - uint32_t exception_base_addr; - uint32_t stack_size; - uint32_t flags; - uint32_t core_mask; - /* DRAM size in megabytes */ - uint32_t dram_size; - /* physical address of free memory descriptor block*/ - uint32_t phy_mem_desc_addr; - /* used to pass flags from app to debugger */ - uint32_t debugger_flags_base_addr; - - /* CPU clock speed, in hz */ - uint32_t eclock_hz; - - /* DRAM clock speed, in hz */ - uint32_t dclock_hz; - - uint32_t reserved0; - uint16_t board_type; - uint8_t board_rev_major; - uint8_t board_rev_minor; - uint16_t reserved1; - uint8_t reserved2; - uint8_t reserved3; - char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; - uint8_t mac_addr_base[6]; - uint8_t mac_addr_count; -#if (CVMX_BOOTINFO_MIN_VER >= 1) - /* - * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different - * addresses on different boards. These are the physical - * addresses, so care must be taken to use the correct - * XKPHYS/KSEG0 addressing depending on the application's - * ABI. These values will be 0 if CF is not present. - */ - uint64_t compact_flash_common_base_addr; - uint64_t compact_flash_attribute_base_addr; - /* - * Base address of the LED display (as on EBT3000 board) - * This will be 0 if LED display not present. - */ - uint64_t led_display_base_addr; -#endif -#if (CVMX_BOOTINFO_MIN_VER >= 2) - /* DFA reference clock in hz (if applicable)*/ - uint32_t dfa_ref_clock_hz; - - /* - * flags indicating various configuration options. These - * flags supercede the 'flags' variable and should be used - * instead if available. - */ - uint32_t config_flags; -#endif - -}; - -#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) -#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1) -#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2) -#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3) -/* This flag is set if the TLB mappings are not contained in the - * 0x10000000 - 0x20000000 boot bus region. */ -#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) -#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5) - -#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ - -/* Type defines for board and chip types */ -enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_NULL = 0, - CVMX_BOARD_TYPE_SIM = 1, - CVMX_BOARD_TYPE_EBT3000 = 2, - CVMX_BOARD_TYPE_KODAMA = 3, - CVMX_BOARD_TYPE_NIAGARA = 4, - CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */ - CVMX_BOARD_TYPE_THUNDER = 6, - CVMX_BOARD_TYPE_TRANTOR = 7, - CVMX_BOARD_TYPE_EBH3000 = 8, - CVMX_BOARD_TYPE_EBH3100 = 9, - CVMX_BOARD_TYPE_HIKARI = 10, - CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11, - CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12, - CVMX_BOARD_TYPE_KBP = 13, - /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */ - CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14, - CVMX_BOARD_TYPE_EBT5800 = 15, - CVMX_BOARD_TYPE_NICPRO2 = 16, - CVMX_BOARD_TYPE_EBH5600 = 17, - CVMX_BOARD_TYPE_EBH5601 = 18, - CVMX_BOARD_TYPE_EBH5200 = 19, - CVMX_BOARD_TYPE_BBGW_REF = 20, - CVMX_BOARD_TYPE_NIC_XLE_4G = 21, - CVMX_BOARD_TYPE_EBT5600 = 22, - CVMX_BOARD_TYPE_EBH5201 = 23, - CVMX_BOARD_TYPE_MAX, - - /* - * The range from CVMX_BOARD_TYPE_MAX to - * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future - * SDK use. - */ - - /* - * Set aside a range for customer boards. These numbers are managed - * by Cavium. - */ - CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000, - CVMX_BOARD_TYPE_CUST_WSX16 = 10001, - CVMX_BOARD_TYPE_CUST_NS0216 = 10002, - CVMX_BOARD_TYPE_CUST_NB5 = 10003, - CVMX_BOARD_TYPE_CUST_WMR500 = 10004, - CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, - - /* - * Set aside a range for customer private use. The SDK won't - * use any numbers in this range. - */ - CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, - - /* The remaining range is reserved for future use. */ -}; - -enum cvmx_chip_types_enum { - CVMX_CHIP_TYPE_NULL = 0, - CVMX_CHIP_SIM_TYPE_DEPRECATED = 1, - CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2, - CVMX_CHIP_TYPE_MAX, -}; - -/* Compatability alias for NAC38 name change, planned to be removed - * from SDK 1.7 */ -#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 - -/* Functions to return string based on type */ -#define ENUM_BRD_TYPE_CASE(x) \ - case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */ -static inline const char *cvmx_board_type_to_string(enum - cvmx_board_types_enum type) -{ - switch (type) { - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) - - /* Customer boards listed here */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) - - /* Customer private range */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) - } - return "Unsupported Board"; -} - -#define ENUM_CHIP_TYPE_CASE(x) \ - case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */ -static inline const char *cvmx_chip_type_to_string(enum - cvmx_chip_types_enum type) -{ - switch (type) { - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) - ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) - } - return "Unsupported Chip"; -} - -#endif /* __CVMX_BOOTINFO_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-bootmem.h b/trunk/arch/mips/include/asm/octeon/cvmx-bootmem.h deleted file mode 100644 index 1cbe4b55889d..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ /dev/null @@ -1,288 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Simple allocate only memory allocator. Used to allocate memory at - * application start time. - */ - -#ifndef __CVMX_BOOTMEM_H__ -#define __CVMX_BOOTMEM_H__ -/* Must be multiple of 8, changing breaks ABI */ -#define CVMX_BOOTMEM_NAME_LEN 128 - -/* Can change without breaking ABI */ -#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 - -/* minimum alignment of bootmem alloced blocks */ -#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) - -/* Flags for cvmx_bootmem_phy_mem* functions */ -/* Allocate from end of block instead of beginning */ -#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0) - -/* Don't do any locking. */ -#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1) - -/* First bytes of each free physical block of memory contain this structure, - * which is used to maintain the free memory list. Since the bootloader is - * only 32 bits, there is a union providing 64 and 32 bit versions. The - * application init code converts addresses to 64 bit addresses before the - * application starts. - */ -struct cvmx_bootmem_block_header { - /* - * Note: these are referenced from assembly routines in the - * bootloader, so this structure should not be changed - * without changing those routines as well. - */ - uint64_t next_block_addr; - uint64_t size; - -}; - -/* - * Structure for named memory blocks. Number of descriptors available - * can be changed without affecting compatiblity, but name length - * changes require a bump in the bootmem descriptor version Note: This - * structure must be naturally 64 bit aligned, as a single memory - * image will be used by both 32 and 64 bit programs. - */ -struct cvmx_bootmem_named_block_desc { - /* Base address of named block */ - uint64_t base_addr; - /* - * Size actually allocated for named block (may differ from - * requested). - */ - uint64_t size; - /* name of named block */ - char name[CVMX_BOOTMEM_NAME_LEN]; -}; - -/* Current descriptor versions */ -/* CVMX bootmem descriptor major version */ -#define CVMX_BOOTMEM_DESC_MAJ_VER 3 - -/* CVMX bootmem descriptor minor version */ -#define CVMX_BOOTMEM_DESC_MIN_VER 0 - -/* First three members of cvmx_bootmem_desc_t are left in original - * positions for backwards compatibility. - */ -struct cvmx_bootmem_desc { - /* spinlock to control access to list */ - uint32_t lock; - /* flags for indicating various conditions */ - uint32_t flags; - uint64_t head_addr; - - /* Incremented when incompatible changes made */ - uint32_t major_version; - - /* - * Incremented changed when compatible changes made, reset to - * zero when major incremented. - */ - uint32_t minor_version; - - uint64_t app_data_addr; - uint64_t app_data_size; - - /* number of elements in named blocks array */ - uint32_t named_block_num_blocks; - - /* length of name array in bootmem blocks */ - uint32_t named_block_name_len; - /* address of named memory block descriptors */ - uint64_t named_block_array_addr; - -}; - -/** - * Initialize the boot alloc memory structures. This is - * normally called inside of cvmx_user_app_init() - * - * @mem_desc_ptr: Address of the free memory list - */ -extern int cvmx_bootmem_init(void *mem_desc_ptr); - -/** - * Allocate a block of memory from the free list that was passed - * to the application by the bootloader. - * This is an allocate-only algorithm, so freeing memory is not possible. - * - * @size: Size in bytes of block to allocate - * @alignment: Alignment required - must be power of 2 - * - * Returns pointer to block of memory, NULL on error - */ -extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment); - -/** - * Allocate a block of memory from the free list that was - * passed to the application by the bootloader at a specific - * address. This is an allocate-only algorithm, so - * freeing memory is not possible. Allocation will fail if - * memory cannot be allocated at the specified address. - * - * @size: Size in bytes of block to allocate - * @address: Physical address to allocate memory at. If this memory is not - * available, the allocation fails. - * @alignment: Alignment required - must be power of 2 - * Returns pointer to block of memory, NULL on error - */ -extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address, - uint64_t alignment); - -/** - * Allocate a block of memory from the free list that was - * passed to the application by the bootloader within a specified - * address range. This is an allocate-only algorithm, so - * freeing memory is not possible. Allocation will fail if - * memory cannot be allocated in the requested range. - * - * @size: Size in bytes of block to allocate - * @min_addr: defines the minimum address of the range - * @max_addr: defines the maximum address of the range - * @alignment: Alignment required - must be power of 2 - * Returns pointer to block of memory, NULL on error - */ -extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, - uint64_t min_addr, uint64_t max_addr); - -/** - * Frees a previously allocated named bootmem block. - * - * @name: name of block to free - * - * Returns 0 on failure, - * !0 on success - */ -extern int cvmx_bootmem_free_named(char *name); - -/** - * Finds a named bootmem block by name. - * - * @name: name of block to free - * - * Returns pointer to named block descriptor on success - * 0 on failure - */ -struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name); - -/** - * Allocates a block of physical memory from the free list, at - * (optional) requested address and alignment. - * - * @req_size: size of region to allocate. All requests are rounded up - * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size - * - * @address_min: Minimum address that block can occupy. - * - * @address_max: Specifies the maximum address_min (inclusive) that - * the allocation can use. - * - * @alignment: Requested alignment of the block. If this alignment - * cannot be met, the allocation fails. This must be a - * power of 2. (Note: Alignment of - * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and - * internally enforced. Requested alignments of less than - * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to - * CVMX_BOOTMEM_ALIGNMENT_SIZE.) - * - * @flags: Flags to control options for the allocation. - * - * Returns physical address of block allocated, or -1 on failure - */ -int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, - uint64_t address_max, uint64_t alignment, - uint32_t flags); - -/** - * Finds a named memory block by name. - * Also used for finding an unused entry in the named block table. - * - * @name: Name of memory block to find. If NULL pointer given, then - * finds unused descriptor, if available. - * - * @flags: Flags to control options for the allocation. - * - * Returns Pointer to memory block descriptor, NULL if not found. - * If NULL returned when name parameter is NULL, then no memory - * block descriptors are available. - */ -struct cvmx_bootmem_named_block_desc * -cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags); - -/** - * Frees a named block. - * - * @name: name of block to free - * @flags: flags for passing options - * - * Returns 0 on failure - * 1 on success - */ -int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags); - -/** - * Frees a block to the bootmem allocator list. This must - * be used with care, as the size provided must match the size - * of the block that was allocated, or the list will become - * corrupted. - * - * IMPORTANT: This is only intended to be used as part of named block - * frees and initial population of the free memory list. - * * - * - * @phy_addr: physical address of block - * @size: size of block in bytes. - * @flags: flags for passing options - * - * Returns 1 on success, - * 0 on failure - */ -int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags); - -/** - * Locks the bootmem allocator. This is useful in certain situations - * where multiple allocations must be made without being interrupted. - * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. - * - */ -void cvmx_bootmem_lock(void); - -/** - * Unlocks the bootmem allocator. This is useful in certain situations - * where multiple allocations must be made without being interrupted. - * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag. - * - */ -void cvmx_bootmem_unlock(void); - -#endif /* __CVMX_BOOTMEM_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h deleted file mode 100644 index f8f05b7764b7..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-ciu-defs.h +++ /dev/null @@ -1,1616 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_CIU_DEFS_H__ -#define __CVMX_CIU_DEFS_H__ - -#define CVMX_CIU_BIST \ - CVMX_ADD_IO_SEG(0x0001070000000730ull) -#define CVMX_CIU_DINT \ - CVMX_ADD_IO_SEG(0x0001070000000720ull) -#define CVMX_CIU_FUSE \ - CVMX_ADD_IO_SEG(0x0001070000000728ull) -#define CVMX_CIU_GSTOP \ - CVMX_ADD_IO_SEG(0x0001070000000710ull) -#define CVMX_CIU_INTX_EN0(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN0_W1C(offset) \ - CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN0_W1S(offset) \ - CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN1(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN1_W1C(offset) \ - CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN1_W1S(offset) \ - CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16)) -#define CVMX_CIU_INTX_EN4_0(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_EN4_0_W1C(offset) \ - CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_EN4_0_W1S(offset) \ - CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_EN4_1(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_EN4_1_W1C(offset) \ - CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_EN4_1_W1S(offset) \ - CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16)) -#define CVMX_CIU_INTX_SUM0(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8)) -#define CVMX_CIU_INTX_SUM4(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8)) -#define CVMX_CIU_INT_SUM1 \ - CVMX_ADD_IO_SEG(0x0001070000000108ull) -#define CVMX_CIU_MBOX_CLRX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8)) -#define CVMX_CIU_MBOX_SETX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8)) -#define CVMX_CIU_NMI \ - CVMX_ADD_IO_SEG(0x0001070000000718ull) -#define CVMX_CIU_PCI_INTA \ - CVMX_ADD_IO_SEG(0x0001070000000750ull) -#define CVMX_CIU_PP_DBG \ - CVMX_ADD_IO_SEG(0x0001070000000708ull) -#define CVMX_CIU_PP_POKEX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8)) -#define CVMX_CIU_PP_RST \ - CVMX_ADD_IO_SEG(0x0001070000000700ull) -#define CVMX_CIU_QLM_DCOK \ - CVMX_ADD_IO_SEG(0x0001070000000760ull) -#define CVMX_CIU_QLM_JTGC \ - CVMX_ADD_IO_SEG(0x0001070000000768ull) -#define CVMX_CIU_QLM_JTGD \ - CVMX_ADD_IO_SEG(0x0001070000000770ull) -#define CVMX_CIU_SOFT_BIST \ - CVMX_ADD_IO_SEG(0x0001070000000738ull) -#define CVMX_CIU_SOFT_PRST \ - CVMX_ADD_IO_SEG(0x0001070000000748ull) -#define CVMX_CIU_SOFT_PRST1 \ - CVMX_ADD_IO_SEG(0x0001070000000758ull) -#define CVMX_CIU_SOFT_RST \ - CVMX_ADD_IO_SEG(0x0001070000000740ull) -#define CVMX_CIU_TIMX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8)) -#define CVMX_CIU_WDOGX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8)) - -union cvmx_ciu_bist { - uint64_t u64; - struct cvmx_ciu_bist_s { - uint64_t reserved_4_63:60; - uint64_t bist:4; - } s; - struct cvmx_ciu_bist_s cn30xx; - struct cvmx_ciu_bist_s cn31xx; - struct cvmx_ciu_bist_s cn38xx; - struct cvmx_ciu_bist_s cn38xxp2; - struct cvmx_ciu_bist_cn50xx { - uint64_t reserved_2_63:62; - uint64_t bist:2; - } cn50xx; - struct cvmx_ciu_bist_cn52xx { - uint64_t reserved_3_63:61; - uint64_t bist:3; - } cn52xx; - struct cvmx_ciu_bist_cn52xx cn52xxp1; - struct cvmx_ciu_bist_s cn56xx; - struct cvmx_ciu_bist_s cn56xxp1; - struct cvmx_ciu_bist_s cn58xx; - struct cvmx_ciu_bist_s cn58xxp1; -}; - -union cvmx_ciu_dint { - uint64_t u64; - struct cvmx_ciu_dint_s { - uint64_t reserved_16_63:48; - uint64_t dint:16; - } s; - struct cvmx_ciu_dint_cn30xx { - uint64_t reserved_1_63:63; - uint64_t dint:1; - } cn30xx; - struct cvmx_ciu_dint_cn31xx { - uint64_t reserved_2_63:62; - uint64_t dint:2; - } cn31xx; - struct cvmx_ciu_dint_s cn38xx; - struct cvmx_ciu_dint_s cn38xxp2; - struct cvmx_ciu_dint_cn31xx cn50xx; - struct cvmx_ciu_dint_cn52xx { - uint64_t reserved_4_63:60; - uint64_t dint:4; - } cn52xx; - struct cvmx_ciu_dint_cn52xx cn52xxp1; - struct cvmx_ciu_dint_cn56xx { - uint64_t reserved_12_63:52; - uint64_t dint:12; - } cn56xx; - struct cvmx_ciu_dint_cn56xx cn56xxp1; - struct cvmx_ciu_dint_s cn58xx; - struct cvmx_ciu_dint_s cn58xxp1; -}; - -union cvmx_ciu_fuse { - uint64_t u64; - struct cvmx_ciu_fuse_s { - uint64_t reserved_16_63:48; - uint64_t fuse:16; - } s; - struct cvmx_ciu_fuse_cn30xx { - uint64_t reserved_1_63:63; - uint64_t fuse:1; - } cn30xx; - struct cvmx_ciu_fuse_cn31xx { - uint64_t reserved_2_63:62; - uint64_t fuse:2; - } cn31xx; - struct cvmx_ciu_fuse_s cn38xx; - struct cvmx_ciu_fuse_s cn38xxp2; - struct cvmx_ciu_fuse_cn31xx cn50xx; - struct cvmx_ciu_fuse_cn52xx { - uint64_t reserved_4_63:60; - uint64_t fuse:4; - } cn52xx; - struct cvmx_ciu_fuse_cn52xx cn52xxp1; - struct cvmx_ciu_fuse_cn56xx { - uint64_t reserved_12_63:52; - uint64_t fuse:12; - } cn56xx; - struct cvmx_ciu_fuse_cn56xx cn56xxp1; - struct cvmx_ciu_fuse_s cn58xx; - struct cvmx_ciu_fuse_s cn58xxp1; -}; - -union cvmx_ciu_gstop { - uint64_t u64; - struct cvmx_ciu_gstop_s { - uint64_t reserved_1_63:63; - uint64_t gstop:1; - } s; - struct cvmx_ciu_gstop_s cn30xx; - struct cvmx_ciu_gstop_s cn31xx; - struct cvmx_ciu_gstop_s cn38xx; - struct cvmx_ciu_gstop_s cn38xxp2; - struct cvmx_ciu_gstop_s cn50xx; - struct cvmx_ciu_gstop_s cn52xx; - struct cvmx_ciu_gstop_s cn52xxp1; - struct cvmx_ciu_gstop_s cn56xx; - struct cvmx_ciu_gstop_s cn56xxp1; - struct cvmx_ciu_gstop_s cn58xx; - struct cvmx_ciu_gstop_s cn58xxp1; -}; - -union cvmx_ciu_intx_en0 { - uint64_t u64; - struct cvmx_ciu_intx_en0_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en0_cn30xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn30xx; - struct cvmx_ciu_intx_en0_cn31xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn31xx; - struct cvmx_ciu_intx_en0_cn38xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn38xx; - struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; - struct cvmx_ciu_intx_en0_cn30xx cn50xx; - struct cvmx_ciu_intx_en0_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; - struct cvmx_ciu_intx_en0_cn56xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn56xx; - struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en0_cn38xx cn58xx; - struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; -}; - -union cvmx_ciu_intx_en0_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en0_w1c_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en0_w1c_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en0_w1c_s cn56xx; - struct cvmx_ciu_intx_en0_w1c_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en0_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en0_w1s_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en0_w1s_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en0_w1s_s cn56xx; - struct cvmx_ciu_intx_en0_w1s_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en1 { - uint64_t u64; - struct cvmx_ciu_intx_en1_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en1_cn30xx { - uint64_t reserved_1_63:63; - uint64_t wdog:1; - } cn30xx; - struct cvmx_ciu_intx_en1_cn31xx { - uint64_t reserved_2_63:62; - uint64_t wdog:2; - } cn31xx; - struct cvmx_ciu_intx_en1_cn38xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn38xx; - struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; - struct cvmx_ciu_intx_en1_cn31xx cn50xx; - struct cvmx_ciu_intx_en1_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en1_cn52xxp1 { - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xxp1; - struct cvmx_ciu_intx_en1_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en1_cn38xx cn58xx; - struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; -}; - -union cvmx_ciu_intx_en1_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en1_w1c_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en1_w1c_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en1_w1c_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en1_w1c_cn58xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en1_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en1_w1s_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en1_w1s_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en1_w1s_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en1_w1s_cn58xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en4_0 { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en4_0_cn50xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn50xx; - struct cvmx_ciu_intx_en4_0_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; - struct cvmx_ciu_intx_en4_0_cn56xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn56xx; - struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en4_0_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; - struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; -}; - -union cvmx_ciu_intx_en4_0_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_w1c_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en4_0_w1c_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; - struct cvmx_ciu_intx_en4_0_w1c_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en4_0_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en4_0_w1s_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_en4_0_w1s_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; - struct cvmx_ciu_intx_en4_0_w1s_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t reserved_44_44:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en4_1 { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en4_1_cn50xx { - uint64_t reserved_2_63:62; - uint64_t wdog:2; - } cn50xx; - struct cvmx_ciu_intx_en4_1_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en4_1_cn52xxp1 { - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xxp1; - struct cvmx_ciu_intx_en4_1_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; - struct cvmx_ciu_intx_en4_1_cn58xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn58xx; - struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; -}; - -union cvmx_ciu_intx_en4_1_w1c { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_w1c_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en4_1_w1c_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en4_1_w1c_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en4_1_w1c_cn58xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn58xx; -}; - -union cvmx_ciu_intx_en4_1_w1s { - uint64_t u64; - struct cvmx_ciu_intx_en4_1_w1s_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_intx_en4_1_w1s_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_intx_en4_1_w1s_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_intx_en4_1_w1s_cn58xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn58xx; -}; - -union cvmx_ciu_intx_sum0 { - uint64_t u64; - struct cvmx_ciu_intx_sum0_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_sum0_cn30xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn30xx; - struct cvmx_ciu_intx_sum0_cn31xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn31xx; - struct cvmx_ciu_intx_sum0_cn38xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn38xx; - struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; - struct cvmx_ciu_intx_sum0_cn30xx cn50xx; - struct cvmx_ciu_intx_sum0_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; - struct cvmx_ciu_intx_sum0_cn56xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn56xx; - struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; - struct cvmx_ciu_intx_sum0_cn38xx cn58xx; - struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; -}; - -union cvmx_ciu_intx_sum4 { - uint64_t u64; - struct cvmx_ciu_intx_sum4_s { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } s; - struct cvmx_ciu_intx_sum4_cn50xx { - uint64_t reserved_59_63:5; - uint64_t mpi:1; - uint64_t pcm:1; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t reserved_47_47:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn50xx; - struct cvmx_ciu_intx_sum4_cn52xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t reserved_51_51:1; - uint64_t ipd_drp:1; - uint64_t reserved_49_49:1; - uint64_t gmx_drp:1; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn52xx; - struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; - struct cvmx_ciu_intx_sum4_cn56xx { - uint64_t bootdma:1; - uint64_t mii:1; - uint64_t ipdppthr:1; - uint64_t powiq:1; - uint64_t twsi2:1; - uint64_t reserved_57_58:2; - uint64_t usb:1; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn56xx; - struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; - struct cvmx_ciu_intx_sum4_cn58xx { - uint64_t reserved_56_63:8; - uint64_t timer:4; - uint64_t key_zero:1; - uint64_t ipd_drp:1; - uint64_t gmx_drp:2; - uint64_t trace:1; - uint64_t rml:1; - uint64_t twsi:1; - uint64_t wdog_sum:1; - uint64_t pci_msi:4; - uint64_t pci_int:4; - uint64_t uart:2; - uint64_t mbox:2; - uint64_t gpio:16; - uint64_t workq:16; - } cn58xx; - struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; -}; - -union cvmx_ciu_int_sum1 { - uint64_t u64; - struct cvmx_ciu_int_sum1_s { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t wdog:16; - } s; - struct cvmx_ciu_int_sum1_cn30xx { - uint64_t reserved_1_63:63; - uint64_t wdog:1; - } cn30xx; - struct cvmx_ciu_int_sum1_cn31xx { - uint64_t reserved_2_63:62; - uint64_t wdog:2; - } cn31xx; - struct cvmx_ciu_int_sum1_cn38xx { - uint64_t reserved_16_63:48; - uint64_t wdog:16; - } cn38xx; - struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; - struct cvmx_ciu_int_sum1_cn31xx cn50xx; - struct cvmx_ciu_int_sum1_cn52xx { - uint64_t reserved_20_63:44; - uint64_t nand:1; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xx; - struct cvmx_ciu_int_sum1_cn52xxp1 { - uint64_t reserved_19_63:45; - uint64_t mii1:1; - uint64_t usb1:1; - uint64_t uart2:1; - uint64_t reserved_4_15:12; - uint64_t wdog:4; - } cn52xxp1; - struct cvmx_ciu_int_sum1_cn56xx { - uint64_t reserved_12_63:52; - uint64_t wdog:12; - } cn56xx; - struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; - struct cvmx_ciu_int_sum1_cn38xx cn58xx; - struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; -}; - -union cvmx_ciu_mbox_clrx { - uint64_t u64; - struct cvmx_ciu_mbox_clrx_s { - uint64_t reserved_32_63:32; - uint64_t bits:32; - } s; - struct cvmx_ciu_mbox_clrx_s cn30xx; - struct cvmx_ciu_mbox_clrx_s cn31xx; - struct cvmx_ciu_mbox_clrx_s cn38xx; - struct cvmx_ciu_mbox_clrx_s cn38xxp2; - struct cvmx_ciu_mbox_clrx_s cn50xx; - struct cvmx_ciu_mbox_clrx_s cn52xx; - struct cvmx_ciu_mbox_clrx_s cn52xxp1; - struct cvmx_ciu_mbox_clrx_s cn56xx; - struct cvmx_ciu_mbox_clrx_s cn56xxp1; - struct cvmx_ciu_mbox_clrx_s cn58xx; - struct cvmx_ciu_mbox_clrx_s cn58xxp1; -}; - -union cvmx_ciu_mbox_setx { - uint64_t u64; - struct cvmx_ciu_mbox_setx_s { - uint64_t reserved_32_63:32; - uint64_t bits:32; - } s; - struct cvmx_ciu_mbox_setx_s cn30xx; - struct cvmx_ciu_mbox_setx_s cn31xx; - struct cvmx_ciu_mbox_setx_s cn38xx; - struct cvmx_ciu_mbox_setx_s cn38xxp2; - struct cvmx_ciu_mbox_setx_s cn50xx; - struct cvmx_ciu_mbox_setx_s cn52xx; - struct cvmx_ciu_mbox_setx_s cn52xxp1; - struct cvmx_ciu_mbox_setx_s cn56xx; - struct cvmx_ciu_mbox_setx_s cn56xxp1; - struct cvmx_ciu_mbox_setx_s cn58xx; - struct cvmx_ciu_mbox_setx_s cn58xxp1; -}; - -union cvmx_ciu_nmi { - uint64_t u64; - struct cvmx_ciu_nmi_s { - uint64_t reserved_16_63:48; - uint64_t nmi:16; - } s; - struct cvmx_ciu_nmi_cn30xx { - uint64_t reserved_1_63:63; - uint64_t nmi:1; - } cn30xx; - struct cvmx_ciu_nmi_cn31xx { - uint64_t reserved_2_63:62; - uint64_t nmi:2; - } cn31xx; - struct cvmx_ciu_nmi_s cn38xx; - struct cvmx_ciu_nmi_s cn38xxp2; - struct cvmx_ciu_nmi_cn31xx cn50xx; - struct cvmx_ciu_nmi_cn52xx { - uint64_t reserved_4_63:60; - uint64_t nmi:4; - } cn52xx; - struct cvmx_ciu_nmi_cn52xx cn52xxp1; - struct cvmx_ciu_nmi_cn56xx { - uint64_t reserved_12_63:52; - uint64_t nmi:12; - } cn56xx; - struct cvmx_ciu_nmi_cn56xx cn56xxp1; - struct cvmx_ciu_nmi_s cn58xx; - struct cvmx_ciu_nmi_s cn58xxp1; -}; - -union cvmx_ciu_pci_inta { - uint64_t u64; - struct cvmx_ciu_pci_inta_s { - uint64_t reserved_2_63:62; - uint64_t intr:2; - } s; - struct cvmx_ciu_pci_inta_s cn30xx; - struct cvmx_ciu_pci_inta_s cn31xx; - struct cvmx_ciu_pci_inta_s cn38xx; - struct cvmx_ciu_pci_inta_s cn38xxp2; - struct cvmx_ciu_pci_inta_s cn50xx; - struct cvmx_ciu_pci_inta_s cn52xx; - struct cvmx_ciu_pci_inta_s cn52xxp1; - struct cvmx_ciu_pci_inta_s cn56xx; - struct cvmx_ciu_pci_inta_s cn56xxp1; - struct cvmx_ciu_pci_inta_s cn58xx; - struct cvmx_ciu_pci_inta_s cn58xxp1; -}; - -union cvmx_ciu_pp_dbg { - uint64_t u64; - struct cvmx_ciu_pp_dbg_s { - uint64_t reserved_16_63:48; - uint64_t ppdbg:16; - } s; - struct cvmx_ciu_pp_dbg_cn30xx { - uint64_t reserved_1_63:63; - uint64_t ppdbg:1; - } cn30xx; - struct cvmx_ciu_pp_dbg_cn31xx { - uint64_t reserved_2_63:62; - uint64_t ppdbg:2; - } cn31xx; - struct cvmx_ciu_pp_dbg_s cn38xx; - struct cvmx_ciu_pp_dbg_s cn38xxp2; - struct cvmx_ciu_pp_dbg_cn31xx cn50xx; - struct cvmx_ciu_pp_dbg_cn52xx { - uint64_t reserved_4_63:60; - uint64_t ppdbg:4; - } cn52xx; - struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; - struct cvmx_ciu_pp_dbg_cn56xx { - uint64_t reserved_12_63:52; - uint64_t ppdbg:12; - } cn56xx; - struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; - struct cvmx_ciu_pp_dbg_s cn58xx; - struct cvmx_ciu_pp_dbg_s cn58xxp1; -}; - -union cvmx_ciu_pp_pokex { - uint64_t u64; - struct cvmx_ciu_pp_pokex_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_ciu_pp_pokex_s cn30xx; - struct cvmx_ciu_pp_pokex_s cn31xx; - struct cvmx_ciu_pp_pokex_s cn38xx; - struct cvmx_ciu_pp_pokex_s cn38xxp2; - struct cvmx_ciu_pp_pokex_s cn50xx; - struct cvmx_ciu_pp_pokex_s cn52xx; - struct cvmx_ciu_pp_pokex_s cn52xxp1; - struct cvmx_ciu_pp_pokex_s cn56xx; - struct cvmx_ciu_pp_pokex_s cn56xxp1; - struct cvmx_ciu_pp_pokex_s cn58xx; - struct cvmx_ciu_pp_pokex_s cn58xxp1; -}; - -union cvmx_ciu_pp_rst { - uint64_t u64; - struct cvmx_ciu_pp_rst_s { - uint64_t reserved_16_63:48; - uint64_t rst:15; - uint64_t rst0:1; - } s; - struct cvmx_ciu_pp_rst_cn30xx { - uint64_t reserved_1_63:63; - uint64_t rst0:1; - } cn30xx; - struct cvmx_ciu_pp_rst_cn31xx { - uint64_t reserved_2_63:62; - uint64_t rst:1; - uint64_t rst0:1; - } cn31xx; - struct cvmx_ciu_pp_rst_s cn38xx; - struct cvmx_ciu_pp_rst_s cn38xxp2; - struct cvmx_ciu_pp_rst_cn31xx cn50xx; - struct cvmx_ciu_pp_rst_cn52xx { - uint64_t reserved_4_63:60; - uint64_t rst:3; - uint64_t rst0:1; - } cn52xx; - struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; - struct cvmx_ciu_pp_rst_cn56xx { - uint64_t reserved_12_63:52; - uint64_t rst:11; - uint64_t rst0:1; - } cn56xx; - struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; - struct cvmx_ciu_pp_rst_s cn58xx; - struct cvmx_ciu_pp_rst_s cn58xxp1; -}; - -union cvmx_ciu_qlm_dcok { - uint64_t u64; - struct cvmx_ciu_qlm_dcok_s { - uint64_t reserved_4_63:60; - uint64_t qlm_dcok:4; - } s; - struct cvmx_ciu_qlm_dcok_cn52xx { - uint64_t reserved_2_63:62; - uint64_t qlm_dcok:2; - } cn52xx; - struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_dcok_s cn56xx; - struct cvmx_ciu_qlm_dcok_s cn56xxp1; -}; - -union cvmx_ciu_qlm_jtgc { - uint64_t u64; - struct cvmx_ciu_qlm_jtgc_s { - uint64_t reserved_11_63:53; - uint64_t clk_div:3; - uint64_t reserved_6_7:2; - uint64_t mux_sel:2; - uint64_t bypass:4; - } s; - struct cvmx_ciu_qlm_jtgc_cn52xx { - uint64_t reserved_11_63:53; - uint64_t clk_div:3; - uint64_t reserved_5_7:3; - uint64_t mux_sel:1; - uint64_t reserved_2_3:2; - uint64_t bypass:2; - } cn52xx; - struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgc_s cn56xx; - struct cvmx_ciu_qlm_jtgc_s cn56xxp1; -}; - -union cvmx_ciu_qlm_jtgd { - uint64_t u64; - struct cvmx_ciu_qlm_jtgd_s { - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_44_60:17; - uint64_t select:4; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; - } s; - struct cvmx_ciu_qlm_jtgd_cn52xx { - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_42_60:19; - uint64_t select:2; - uint64_t reserved_37_39:3; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; - } cn52xx; - struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; - struct cvmx_ciu_qlm_jtgd_s cn56xx; - struct cvmx_ciu_qlm_jtgd_cn56xxp1 { - uint64_t capture:1; - uint64_t shift:1; - uint64_t update:1; - uint64_t reserved_37_60:24; - uint64_t shft_cnt:5; - uint64_t shft_reg:32; - } cn56xxp1; -}; - -union cvmx_ciu_soft_bist { - uint64_t u64; - struct cvmx_ciu_soft_bist_s { - uint64_t reserved_1_63:63; - uint64_t soft_bist:1; - } s; - struct cvmx_ciu_soft_bist_s cn30xx; - struct cvmx_ciu_soft_bist_s cn31xx; - struct cvmx_ciu_soft_bist_s cn38xx; - struct cvmx_ciu_soft_bist_s cn38xxp2; - struct cvmx_ciu_soft_bist_s cn50xx; - struct cvmx_ciu_soft_bist_s cn52xx; - struct cvmx_ciu_soft_bist_s cn52xxp1; - struct cvmx_ciu_soft_bist_s cn56xx; - struct cvmx_ciu_soft_bist_s cn56xxp1; - struct cvmx_ciu_soft_bist_s cn58xx; - struct cvmx_ciu_soft_bist_s cn58xxp1; -}; - -union cvmx_ciu_soft_prst { - uint64_t u64; - struct cvmx_ciu_soft_prst_s { - uint64_t reserved_3_63:61; - uint64_t host64:1; - uint64_t npi:1; - uint64_t soft_prst:1; - } s; - struct cvmx_ciu_soft_prst_s cn30xx; - struct cvmx_ciu_soft_prst_s cn31xx; - struct cvmx_ciu_soft_prst_s cn38xx; - struct cvmx_ciu_soft_prst_s cn38xxp2; - struct cvmx_ciu_soft_prst_s cn50xx; - struct cvmx_ciu_soft_prst_cn52xx { - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; - } cn52xx; - struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; - struct cvmx_ciu_soft_prst_cn52xx cn56xx; - struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; - struct cvmx_ciu_soft_prst_s cn58xx; - struct cvmx_ciu_soft_prst_s cn58xxp1; -}; - -union cvmx_ciu_soft_prst1 { - uint64_t u64; - struct cvmx_ciu_soft_prst1_s { - uint64_t reserved_1_63:63; - uint64_t soft_prst:1; - } s; - struct cvmx_ciu_soft_prst1_s cn52xx; - struct cvmx_ciu_soft_prst1_s cn52xxp1; - struct cvmx_ciu_soft_prst1_s cn56xx; - struct cvmx_ciu_soft_prst1_s cn56xxp1; -}; - -union cvmx_ciu_soft_rst { - uint64_t u64; - struct cvmx_ciu_soft_rst_s { - uint64_t reserved_1_63:63; - uint64_t soft_rst:1; - } s; - struct cvmx_ciu_soft_rst_s cn30xx; - struct cvmx_ciu_soft_rst_s cn31xx; - struct cvmx_ciu_soft_rst_s cn38xx; - struct cvmx_ciu_soft_rst_s cn38xxp2; - struct cvmx_ciu_soft_rst_s cn50xx; - struct cvmx_ciu_soft_rst_s cn52xx; - struct cvmx_ciu_soft_rst_s cn52xxp1; - struct cvmx_ciu_soft_rst_s cn56xx; - struct cvmx_ciu_soft_rst_s cn56xxp1; - struct cvmx_ciu_soft_rst_s cn58xx; - struct cvmx_ciu_soft_rst_s cn58xxp1; -}; - -union cvmx_ciu_timx { - uint64_t u64; - struct cvmx_ciu_timx_s { - uint64_t reserved_37_63:27; - uint64_t one_shot:1; - uint64_t len:36; - } s; - struct cvmx_ciu_timx_s cn30xx; - struct cvmx_ciu_timx_s cn31xx; - struct cvmx_ciu_timx_s cn38xx; - struct cvmx_ciu_timx_s cn38xxp2; - struct cvmx_ciu_timx_s cn50xx; - struct cvmx_ciu_timx_s cn52xx; - struct cvmx_ciu_timx_s cn52xxp1; - struct cvmx_ciu_timx_s cn56xx; - struct cvmx_ciu_timx_s cn56xxp1; - struct cvmx_ciu_timx_s cn58xx; - struct cvmx_ciu_timx_s cn58xxp1; -}; - -union cvmx_ciu_wdogx { - uint64_t u64; - struct cvmx_ciu_wdogx_s { - uint64_t reserved_46_63:18; - uint64_t gstopen:1; - uint64_t dstop:1; - uint64_t cnt:24; - uint64_t len:16; - uint64_t state:2; - uint64_t mode:2; - } s; - struct cvmx_ciu_wdogx_s cn30xx; - struct cvmx_ciu_wdogx_s cn31xx; - struct cvmx_ciu_wdogx_s cn38xx; - struct cvmx_ciu_wdogx_s cn38xxp2; - struct cvmx_ciu_wdogx_s cn50xx; - struct cvmx_ciu_wdogx_s cn52xx; - struct cvmx_ciu_wdogx_s cn52xxp1; - struct cvmx_ciu_wdogx_s cn56xx; - struct cvmx_ciu_wdogx_s cn56xxp1; - struct cvmx_ciu_wdogx_s cn58xx; - struct cvmx_ciu_wdogx_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h deleted file mode 100644 index 5fdd6ba48a05..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-gpio-defs.h +++ /dev/null @@ -1,219 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_GPIO_DEFS_H__ -#define __CVMX_GPIO_DEFS_H__ - -#define CVMX_GPIO_BIT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) -#define CVMX_GPIO_BOOT_ENA \ - CVMX_ADD_IO_SEG(0x00010700000008A8ull) -#define CVMX_GPIO_CLK_GENX(offset) \ - CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) -#define CVMX_GPIO_DBG_ENA \ - CVMX_ADD_IO_SEG(0x00010700000008A0ull) -#define CVMX_GPIO_INT_CLR \ - CVMX_ADD_IO_SEG(0x0001070000000898ull) -#define CVMX_GPIO_RX_DAT \ - CVMX_ADD_IO_SEG(0x0001070000000880ull) -#define CVMX_GPIO_TX_CLR \ - CVMX_ADD_IO_SEG(0x0001070000000890ull) -#define CVMX_GPIO_TX_SET \ - CVMX_ADD_IO_SEG(0x0001070000000888ull) -#define CVMX_GPIO_XBIT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16) - -union cvmx_gpio_bit_cfgx { - uint64_t u64; - struct cvmx_gpio_bit_cfgx_s { - uint64_t reserved_15_63:49; - uint64_t clk_gen:1; - uint64_t clk_sel:2; - uint64_t fil_sel:4; - uint64_t fil_cnt:4; - uint64_t int_type:1; - uint64_t int_en:1; - uint64_t rx_xor:1; - uint64_t tx_oe:1; - } s; - struct cvmx_gpio_bit_cfgx_cn30xx { - uint64_t reserved_12_63:52; - uint64_t fil_sel:4; - uint64_t fil_cnt:4; - uint64_t int_type:1; - uint64_t int_en:1; - uint64_t rx_xor:1; - uint64_t tx_oe:1; - } cn30xx; - struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; - struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; - struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; - struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; - struct cvmx_gpio_bit_cfgx_s cn52xx; - struct cvmx_gpio_bit_cfgx_s cn52xxp1; - struct cvmx_gpio_bit_cfgx_s cn56xx; - struct cvmx_gpio_bit_cfgx_s cn56xxp1; - struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; - struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; -}; - -union cvmx_gpio_boot_ena { - uint64_t u64; - struct cvmx_gpio_boot_ena_s { - uint64_t reserved_12_63:52; - uint64_t boot_ena:4; - uint64_t reserved_0_7:8; - } s; - struct cvmx_gpio_boot_ena_s cn30xx; - struct cvmx_gpio_boot_ena_s cn31xx; - struct cvmx_gpio_boot_ena_s cn50xx; -}; - -union cvmx_gpio_clk_genx { - uint64_t u64; - struct cvmx_gpio_clk_genx_s { - uint64_t reserved_32_63:32; - uint64_t n:32; - } s; - struct cvmx_gpio_clk_genx_s cn52xx; - struct cvmx_gpio_clk_genx_s cn52xxp1; - struct cvmx_gpio_clk_genx_s cn56xx; - struct cvmx_gpio_clk_genx_s cn56xxp1; -}; - -union cvmx_gpio_dbg_ena { - uint64_t u64; - struct cvmx_gpio_dbg_ena_s { - uint64_t reserved_21_63:43; - uint64_t dbg_ena:21; - } s; - struct cvmx_gpio_dbg_ena_s cn30xx; - struct cvmx_gpio_dbg_ena_s cn31xx; - struct cvmx_gpio_dbg_ena_s cn50xx; -}; - -union cvmx_gpio_int_clr { - uint64_t u64; - struct cvmx_gpio_int_clr_s { - uint64_t reserved_16_63:48; - uint64_t type:16; - } s; - struct cvmx_gpio_int_clr_s cn30xx; - struct cvmx_gpio_int_clr_s cn31xx; - struct cvmx_gpio_int_clr_s cn38xx; - struct cvmx_gpio_int_clr_s cn38xxp2; - struct cvmx_gpio_int_clr_s cn50xx; - struct cvmx_gpio_int_clr_s cn52xx; - struct cvmx_gpio_int_clr_s cn52xxp1; - struct cvmx_gpio_int_clr_s cn56xx; - struct cvmx_gpio_int_clr_s cn56xxp1; - struct cvmx_gpio_int_clr_s cn58xx; - struct cvmx_gpio_int_clr_s cn58xxp1; -}; - -union cvmx_gpio_rx_dat { - uint64_t u64; - struct cvmx_gpio_rx_dat_s { - uint64_t reserved_24_63:40; - uint64_t dat:24; - } s; - struct cvmx_gpio_rx_dat_s cn30xx; - struct cvmx_gpio_rx_dat_s cn31xx; - struct cvmx_gpio_rx_dat_cn38xx { - uint64_t reserved_16_63:48; - uint64_t dat:16; - } cn38xx; - struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; - struct cvmx_gpio_rx_dat_s cn50xx; - struct cvmx_gpio_rx_dat_cn38xx cn52xx; - struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; - struct cvmx_gpio_rx_dat_cn38xx cn56xx; - struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; - struct cvmx_gpio_rx_dat_cn38xx cn58xx; - struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; -}; - -union cvmx_gpio_tx_clr { - uint64_t u64; - struct cvmx_gpio_tx_clr_s { - uint64_t reserved_24_63:40; - uint64_t clr:24; - } s; - struct cvmx_gpio_tx_clr_s cn30xx; - struct cvmx_gpio_tx_clr_s cn31xx; - struct cvmx_gpio_tx_clr_cn38xx { - uint64_t reserved_16_63:48; - uint64_t clr:16; - } cn38xx; - struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; - struct cvmx_gpio_tx_clr_s cn50xx; - struct cvmx_gpio_tx_clr_cn38xx cn52xx; - struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; - struct cvmx_gpio_tx_clr_cn38xx cn56xx; - struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; - struct cvmx_gpio_tx_clr_cn38xx cn58xx; - struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; -}; - -union cvmx_gpio_tx_set { - uint64_t u64; - struct cvmx_gpio_tx_set_s { - uint64_t reserved_24_63:40; - uint64_t set:24; - } s; - struct cvmx_gpio_tx_set_s cn30xx; - struct cvmx_gpio_tx_set_s cn31xx; - struct cvmx_gpio_tx_set_cn38xx { - uint64_t reserved_16_63:48; - uint64_t set:16; - } cn38xx; - struct cvmx_gpio_tx_set_cn38xx cn38xxp2; - struct cvmx_gpio_tx_set_s cn50xx; - struct cvmx_gpio_tx_set_cn38xx cn52xx; - struct cvmx_gpio_tx_set_cn38xx cn52xxp1; - struct cvmx_gpio_tx_set_cn38xx cn56xx; - struct cvmx_gpio_tx_set_cn38xx cn56xxp1; - struct cvmx_gpio_tx_set_cn38xx cn58xx; - struct cvmx_gpio_tx_set_cn38xx cn58xxp1; -}; - -union cvmx_gpio_xbit_cfgx { - uint64_t u64; - struct cvmx_gpio_xbit_cfgx_s { - uint64_t reserved_12_63:52; - uint64_t fil_sel:4; - uint64_t fil_cnt:4; - uint64_t reserved_2_3:2; - uint64_t rx_xor:1; - uint64_t tx_oe:1; - } s; - struct cvmx_gpio_xbit_cfgx_s cn30xx; - struct cvmx_gpio_xbit_cfgx_s cn31xx; - struct cvmx_gpio_xbit_cfgx_s cn50xx; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h deleted file mode 100644 index 0ee36baec500..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-iob-defs.h +++ /dev/null @@ -1,530 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_IOB_DEFS_H__ -#define __CVMX_IOB_DEFS_H__ - -#define CVMX_IOB_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800F00007F8ull) -#define CVMX_IOB_CTL_STATUS \ - CVMX_ADD_IO_SEG(0x00011800F0000050ull) -#define CVMX_IOB_DWB_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000028ull) -#define CVMX_IOB_FAU_TIMEOUT \ - CVMX_ADD_IO_SEG(0x00011800F0000000ull) -#define CVMX_IOB_I2C_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000010ull) -#define CVMX_IOB_INB_CONTROL_MATCH \ - CVMX_ADD_IO_SEG(0x00011800F0000078ull) -#define CVMX_IOB_INB_CONTROL_MATCH_ENB \ - CVMX_ADD_IO_SEG(0x00011800F0000088ull) -#define CVMX_IOB_INB_DATA_MATCH \ - CVMX_ADD_IO_SEG(0x00011800F0000070ull) -#define CVMX_IOB_INB_DATA_MATCH_ENB \ - CVMX_ADD_IO_SEG(0x00011800F0000080ull) -#define CVMX_IOB_INT_ENB \ - CVMX_ADD_IO_SEG(0x00011800F0000060ull) -#define CVMX_IOB_INT_SUM \ - CVMX_ADD_IO_SEG(0x00011800F0000058ull) -#define CVMX_IOB_N2C_L2C_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000020ull) -#define CVMX_IOB_N2C_RSP_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000008ull) -#define CVMX_IOB_OUTB_COM_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000040ull) -#define CVMX_IOB_OUTB_CONTROL_MATCH \ - CVMX_ADD_IO_SEG(0x00011800F0000098ull) -#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \ - CVMX_ADD_IO_SEG(0x00011800F00000A8ull) -#define CVMX_IOB_OUTB_DATA_MATCH \ - CVMX_ADD_IO_SEG(0x00011800F0000090ull) -#define CVMX_IOB_OUTB_DATA_MATCH_ENB \ - CVMX_ADD_IO_SEG(0x00011800F00000A0ull) -#define CVMX_IOB_OUTB_FPA_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000048ull) -#define CVMX_IOB_OUTB_REQ_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000038ull) -#define CVMX_IOB_P2C_REQ_PRI_CNT \ - CVMX_ADD_IO_SEG(0x00011800F0000018ull) -#define CVMX_IOB_PKT_ERR \ - CVMX_ADD_IO_SEG(0x00011800F0000068ull) - -union cvmx_iob_bist_status { - uint64_t u64; - struct cvmx_iob_bist_status_s { - uint64_t reserved_18_63:46; - uint64_t icnrcb:1; - uint64_t icr0:1; - uint64_t icr1:1; - uint64_t icnr1:1; - uint64_t icnr0:1; - uint64_t ibdr0:1; - uint64_t ibdr1:1; - uint64_t ibr0:1; - uint64_t ibr1:1; - uint64_t icnrt:1; - uint64_t ibrq0:1; - uint64_t ibrq1:1; - uint64_t icrn0:1; - uint64_t icrn1:1; - uint64_t icrp0:1; - uint64_t icrp1:1; - uint64_t ibd:1; - uint64_t icd:1; - } s; - struct cvmx_iob_bist_status_s cn30xx; - struct cvmx_iob_bist_status_s cn31xx; - struct cvmx_iob_bist_status_s cn38xx; - struct cvmx_iob_bist_status_s cn38xxp2; - struct cvmx_iob_bist_status_s cn50xx; - struct cvmx_iob_bist_status_s cn52xx; - struct cvmx_iob_bist_status_s cn52xxp1; - struct cvmx_iob_bist_status_s cn56xx; - struct cvmx_iob_bist_status_s cn56xxp1; - struct cvmx_iob_bist_status_s cn58xx; - struct cvmx_iob_bist_status_s cn58xxp1; -}; - -union cvmx_iob_ctl_status { - uint64_t u64; - struct cvmx_iob_ctl_status_s { - uint64_t reserved_5_63:59; - uint64_t outb_mat:1; - uint64_t inb_mat:1; - uint64_t pko_enb:1; - uint64_t dwb_enb:1; - uint64_t fau_end:1; - } s; - struct cvmx_iob_ctl_status_s cn30xx; - struct cvmx_iob_ctl_status_s cn31xx; - struct cvmx_iob_ctl_status_s cn38xx; - struct cvmx_iob_ctl_status_s cn38xxp2; - struct cvmx_iob_ctl_status_s cn50xx; - struct cvmx_iob_ctl_status_s cn52xx; - struct cvmx_iob_ctl_status_s cn52xxp1; - struct cvmx_iob_ctl_status_s cn56xx; - struct cvmx_iob_ctl_status_s cn56xxp1; - struct cvmx_iob_ctl_status_s cn58xx; - struct cvmx_iob_ctl_status_s cn58xxp1; -}; - -union cvmx_iob_dwb_pri_cnt { - uint64_t u64; - struct cvmx_iob_dwb_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_dwb_pri_cnt_s cn38xx; - struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; - struct cvmx_iob_dwb_pri_cnt_s cn52xx; - struct cvmx_iob_dwb_pri_cnt_s cn52xxp1; - struct cvmx_iob_dwb_pri_cnt_s cn56xx; - struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; - struct cvmx_iob_dwb_pri_cnt_s cn58xx; - struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_fau_timeout { - uint64_t u64; - struct cvmx_iob_fau_timeout_s { - uint64_t reserved_13_63:51; - uint64_t tout_enb:1; - uint64_t tout_val:12; - } s; - struct cvmx_iob_fau_timeout_s cn30xx; - struct cvmx_iob_fau_timeout_s cn31xx; - struct cvmx_iob_fau_timeout_s cn38xx; - struct cvmx_iob_fau_timeout_s cn38xxp2; - struct cvmx_iob_fau_timeout_s cn50xx; - struct cvmx_iob_fau_timeout_s cn52xx; - struct cvmx_iob_fau_timeout_s cn52xxp1; - struct cvmx_iob_fau_timeout_s cn56xx; - struct cvmx_iob_fau_timeout_s cn56xxp1; - struct cvmx_iob_fau_timeout_s cn58xx; - struct cvmx_iob_fau_timeout_s cn58xxp1; -}; - -union cvmx_iob_i2c_pri_cnt { - uint64_t u64; - struct cvmx_iob_i2c_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_i2c_pri_cnt_s cn38xx; - struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; - struct cvmx_iob_i2c_pri_cnt_s cn52xx; - struct cvmx_iob_i2c_pri_cnt_s cn52xxp1; - struct cvmx_iob_i2c_pri_cnt_s cn56xx; - struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; - struct cvmx_iob_i2c_pri_cnt_s cn58xx; - struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_inb_control_match { - uint64_t u64; - struct cvmx_iob_inb_control_match_s { - uint64_t reserved_29_63:35; - uint64_t mask:8; - uint64_t opc:4; - uint64_t dst:9; - uint64_t src:8; - } s; - struct cvmx_iob_inb_control_match_s cn30xx; - struct cvmx_iob_inb_control_match_s cn31xx; - struct cvmx_iob_inb_control_match_s cn38xx; - struct cvmx_iob_inb_control_match_s cn38xxp2; - struct cvmx_iob_inb_control_match_s cn50xx; - struct cvmx_iob_inb_control_match_s cn52xx; - struct cvmx_iob_inb_control_match_s cn52xxp1; - struct cvmx_iob_inb_control_match_s cn56xx; - struct cvmx_iob_inb_control_match_s cn56xxp1; - struct cvmx_iob_inb_control_match_s cn58xx; - struct cvmx_iob_inb_control_match_s cn58xxp1; -}; - -union cvmx_iob_inb_control_match_enb { - uint64_t u64; - struct cvmx_iob_inb_control_match_enb_s { - uint64_t reserved_29_63:35; - uint64_t mask:8; - uint64_t opc:4; - uint64_t dst:9; - uint64_t src:8; - } s; - struct cvmx_iob_inb_control_match_enb_s cn30xx; - struct cvmx_iob_inb_control_match_enb_s cn31xx; - struct cvmx_iob_inb_control_match_enb_s cn38xx; - struct cvmx_iob_inb_control_match_enb_s cn38xxp2; - struct cvmx_iob_inb_control_match_enb_s cn50xx; - struct cvmx_iob_inb_control_match_enb_s cn52xx; - struct cvmx_iob_inb_control_match_enb_s cn52xxp1; - struct cvmx_iob_inb_control_match_enb_s cn56xx; - struct cvmx_iob_inb_control_match_enb_s cn56xxp1; - struct cvmx_iob_inb_control_match_enb_s cn58xx; - struct cvmx_iob_inb_control_match_enb_s cn58xxp1; -}; - -union cvmx_iob_inb_data_match { - uint64_t u64; - struct cvmx_iob_inb_data_match_s { - uint64_t data:64; - } s; - struct cvmx_iob_inb_data_match_s cn30xx; - struct cvmx_iob_inb_data_match_s cn31xx; - struct cvmx_iob_inb_data_match_s cn38xx; - struct cvmx_iob_inb_data_match_s cn38xxp2; - struct cvmx_iob_inb_data_match_s cn50xx; - struct cvmx_iob_inb_data_match_s cn52xx; - struct cvmx_iob_inb_data_match_s cn52xxp1; - struct cvmx_iob_inb_data_match_s cn56xx; - struct cvmx_iob_inb_data_match_s cn56xxp1; - struct cvmx_iob_inb_data_match_s cn58xx; - struct cvmx_iob_inb_data_match_s cn58xxp1; -}; - -union cvmx_iob_inb_data_match_enb { - uint64_t u64; - struct cvmx_iob_inb_data_match_enb_s { - uint64_t data:64; - } s; - struct cvmx_iob_inb_data_match_enb_s cn30xx; - struct cvmx_iob_inb_data_match_enb_s cn31xx; - struct cvmx_iob_inb_data_match_enb_s cn38xx; - struct cvmx_iob_inb_data_match_enb_s cn38xxp2; - struct cvmx_iob_inb_data_match_enb_s cn50xx; - struct cvmx_iob_inb_data_match_enb_s cn52xx; - struct cvmx_iob_inb_data_match_enb_s cn52xxp1; - struct cvmx_iob_inb_data_match_enb_s cn56xx; - struct cvmx_iob_inb_data_match_enb_s cn56xxp1; - struct cvmx_iob_inb_data_match_enb_s cn58xx; - struct cvmx_iob_inb_data_match_enb_s cn58xxp1; -}; - -union cvmx_iob_int_enb { - uint64_t u64; - struct cvmx_iob_int_enb_s { - uint64_t reserved_6_63:58; - uint64_t p_dat:1; - uint64_t np_dat:1; - uint64_t p_eop:1; - uint64_t p_sop:1; - uint64_t np_eop:1; - uint64_t np_sop:1; - } s; - struct cvmx_iob_int_enb_cn30xx { - uint64_t reserved_4_63:60; - uint64_t p_eop:1; - uint64_t p_sop:1; - uint64_t np_eop:1; - uint64_t np_sop:1; - } cn30xx; - struct cvmx_iob_int_enb_cn30xx cn31xx; - struct cvmx_iob_int_enb_cn30xx cn38xx; - struct cvmx_iob_int_enb_cn30xx cn38xxp2; - struct cvmx_iob_int_enb_s cn50xx; - struct cvmx_iob_int_enb_s cn52xx; - struct cvmx_iob_int_enb_s cn52xxp1; - struct cvmx_iob_int_enb_s cn56xx; - struct cvmx_iob_int_enb_s cn56xxp1; - struct cvmx_iob_int_enb_s cn58xx; - struct cvmx_iob_int_enb_s cn58xxp1; -}; - -union cvmx_iob_int_sum { - uint64_t u64; - struct cvmx_iob_int_sum_s { - uint64_t reserved_6_63:58; - uint64_t p_dat:1; - uint64_t np_dat:1; - uint64_t p_eop:1; - uint64_t p_sop:1; - uint64_t np_eop:1; - uint64_t np_sop:1; - } s; - struct cvmx_iob_int_sum_cn30xx { - uint64_t reserved_4_63:60; - uint64_t p_eop:1; - uint64_t p_sop:1; - uint64_t np_eop:1; - uint64_t np_sop:1; - } cn30xx; - struct cvmx_iob_int_sum_cn30xx cn31xx; - struct cvmx_iob_int_sum_cn30xx cn38xx; - struct cvmx_iob_int_sum_cn30xx cn38xxp2; - struct cvmx_iob_int_sum_s cn50xx; - struct cvmx_iob_int_sum_s cn52xx; - struct cvmx_iob_int_sum_s cn52xxp1; - struct cvmx_iob_int_sum_s cn56xx; - struct cvmx_iob_int_sum_s cn56xxp1; - struct cvmx_iob_int_sum_s cn58xx; - struct cvmx_iob_int_sum_s cn58xxp1; -}; - -union cvmx_iob_n2c_l2c_pri_cnt { - uint64_t u64; - struct cvmx_iob_n2c_l2c_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; - struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_n2c_rsp_pri_cnt { - uint64_t u64; - struct cvmx_iob_n2c_rsp_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; - struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_outb_com_pri_cnt { - uint64_t u64; - struct cvmx_iob_outb_com_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_outb_com_pri_cnt_s cn38xx; - struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; - struct cvmx_iob_outb_com_pri_cnt_s cn52xx; - struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1; - struct cvmx_iob_outb_com_pri_cnt_s cn56xx; - struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; - struct cvmx_iob_outb_com_pri_cnt_s cn58xx; - struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_outb_control_match { - uint64_t u64; - struct cvmx_iob_outb_control_match_s { - uint64_t reserved_26_63:38; - uint64_t mask:8; - uint64_t eot:1; - uint64_t dst:8; - uint64_t src:9; - } s; - struct cvmx_iob_outb_control_match_s cn30xx; - struct cvmx_iob_outb_control_match_s cn31xx; - struct cvmx_iob_outb_control_match_s cn38xx; - struct cvmx_iob_outb_control_match_s cn38xxp2; - struct cvmx_iob_outb_control_match_s cn50xx; - struct cvmx_iob_outb_control_match_s cn52xx; - struct cvmx_iob_outb_control_match_s cn52xxp1; - struct cvmx_iob_outb_control_match_s cn56xx; - struct cvmx_iob_outb_control_match_s cn56xxp1; - struct cvmx_iob_outb_control_match_s cn58xx; - struct cvmx_iob_outb_control_match_s cn58xxp1; -}; - -union cvmx_iob_outb_control_match_enb { - uint64_t u64; - struct cvmx_iob_outb_control_match_enb_s { - uint64_t reserved_26_63:38; - uint64_t mask:8; - uint64_t eot:1; - uint64_t dst:8; - uint64_t src:9; - } s; - struct cvmx_iob_outb_control_match_enb_s cn30xx; - struct cvmx_iob_outb_control_match_enb_s cn31xx; - struct cvmx_iob_outb_control_match_enb_s cn38xx; - struct cvmx_iob_outb_control_match_enb_s cn38xxp2; - struct cvmx_iob_outb_control_match_enb_s cn50xx; - struct cvmx_iob_outb_control_match_enb_s cn52xx; - struct cvmx_iob_outb_control_match_enb_s cn52xxp1; - struct cvmx_iob_outb_control_match_enb_s cn56xx; - struct cvmx_iob_outb_control_match_enb_s cn56xxp1; - struct cvmx_iob_outb_control_match_enb_s cn58xx; - struct cvmx_iob_outb_control_match_enb_s cn58xxp1; -}; - -union cvmx_iob_outb_data_match { - uint64_t u64; - struct cvmx_iob_outb_data_match_s { - uint64_t data:64; - } s; - struct cvmx_iob_outb_data_match_s cn30xx; - struct cvmx_iob_outb_data_match_s cn31xx; - struct cvmx_iob_outb_data_match_s cn38xx; - struct cvmx_iob_outb_data_match_s cn38xxp2; - struct cvmx_iob_outb_data_match_s cn50xx; - struct cvmx_iob_outb_data_match_s cn52xx; - struct cvmx_iob_outb_data_match_s cn52xxp1; - struct cvmx_iob_outb_data_match_s cn56xx; - struct cvmx_iob_outb_data_match_s cn56xxp1; - struct cvmx_iob_outb_data_match_s cn58xx; - struct cvmx_iob_outb_data_match_s cn58xxp1; -}; - -union cvmx_iob_outb_data_match_enb { - uint64_t u64; - struct cvmx_iob_outb_data_match_enb_s { - uint64_t data:64; - } s; - struct cvmx_iob_outb_data_match_enb_s cn30xx; - struct cvmx_iob_outb_data_match_enb_s cn31xx; - struct cvmx_iob_outb_data_match_enb_s cn38xx; - struct cvmx_iob_outb_data_match_enb_s cn38xxp2; - struct cvmx_iob_outb_data_match_enb_s cn50xx; - struct cvmx_iob_outb_data_match_enb_s cn52xx; - struct cvmx_iob_outb_data_match_enb_s cn52xxp1; - struct cvmx_iob_outb_data_match_enb_s cn56xx; - struct cvmx_iob_outb_data_match_enb_s cn56xxp1; - struct cvmx_iob_outb_data_match_enb_s cn58xx; - struct cvmx_iob_outb_data_match_enb_s cn58xxp1; -}; - -union cvmx_iob_outb_fpa_pri_cnt { - uint64_t u64; - struct cvmx_iob_outb_fpa_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; - struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1; - struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; - struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; - struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_outb_req_pri_cnt { - uint64_t u64; - struct cvmx_iob_outb_req_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_outb_req_pri_cnt_s cn38xx; - struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; - struct cvmx_iob_outb_req_pri_cnt_s cn52xx; - struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1; - struct cvmx_iob_outb_req_pri_cnt_s cn56xx; - struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; - struct cvmx_iob_outb_req_pri_cnt_s cn58xx; - struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_p2c_req_pri_cnt { - uint64_t u64; - struct cvmx_iob_p2c_req_pri_cnt_s { - uint64_t reserved_16_63:48; - uint64_t cnt_enb:1; - uint64_t cnt_val:15; - } s; - struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; - struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; - struct cvmx_iob_p2c_req_pri_cnt_s cn52xx; - struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1; - struct cvmx_iob_p2c_req_pri_cnt_s cn56xx; - struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; - struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; - struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; -}; - -union cvmx_iob_pkt_err { - uint64_t u64; - struct cvmx_iob_pkt_err_s { - uint64_t reserved_6_63:58; - uint64_t port:6; - } s; - struct cvmx_iob_pkt_err_s cn30xx; - struct cvmx_iob_pkt_err_s cn31xx; - struct cvmx_iob_pkt_err_s cn38xx; - struct cvmx_iob_pkt_err_s cn38xxp2; - struct cvmx_iob_pkt_err_s cn50xx; - struct cvmx_iob_pkt_err_s cn52xx; - struct cvmx_iob_pkt_err_s cn52xxp1; - struct cvmx_iob_pkt_err_s cn56xx; - struct cvmx_iob_pkt_err_s cn56xxp1; - struct cvmx_iob_pkt_err_s cn58xx; - struct cvmx_iob_pkt_err_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h deleted file mode 100644 index f8b8fc657d2c..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-ipd-defs.h +++ /dev/null @@ -1,877 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_IPD_DEFS_H__ -#define __CVMX_IPD_DEFS_H__ - -#define CVMX_IPD_1ST_MBUFF_SKIP \ - CVMX_ADD_IO_SEG(0x00014F0000000000ull) -#define CVMX_IPD_1st_NEXT_PTR_BACK \ - CVMX_ADD_IO_SEG(0x00014F0000000150ull) -#define CVMX_IPD_2nd_NEXT_PTR_BACK \ - CVMX_ADD_IO_SEG(0x00014F0000000158ull) -#define CVMX_IPD_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00014F00000007F8ull) -#define CVMX_IPD_BP_PRT_RED_END \ - CVMX_ADD_IO_SEG(0x00014F0000000328ull) -#define CVMX_IPD_CLK_COUNT \ - CVMX_ADD_IO_SEG(0x00014F0000000338ull) -#define CVMX_IPD_CTL_STATUS \ - CVMX_ADD_IO_SEG(0x00014F0000000018ull) -#define CVMX_IPD_INT_ENB \ - CVMX_ADD_IO_SEG(0x00014F0000000160ull) -#define CVMX_IPD_INT_SUM \ - CVMX_ADD_IO_SEG(0x00014F0000000168ull) -#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \ - CVMX_ADD_IO_SEG(0x00014F0000000008ull) -#define CVMX_IPD_PACKET_MBUFF_SIZE \ - CVMX_ADD_IO_SEG(0x00014F0000000010ull) -#define CVMX_IPD_PKT_PTR_VALID \ - CVMX_ADD_IO_SEG(0x00014F0000000358ull) -#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8)) -#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36) -#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36) -#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \ - CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8)) -#define CVMX_IPD_PORT_QOS_INTX(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8)) -#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8)) -#define CVMX_IPD_PORT_QOS_X_CNT(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8)) -#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \ - CVMX_ADD_IO_SEG(0x00014F0000000348ull) -#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \ - CVMX_ADD_IO_SEG(0x00014F0000000350ull) -#define CVMX_IPD_PTR_COUNT \ - CVMX_ADD_IO_SEG(0x00014F0000000320ull) -#define CVMX_IPD_PWP_PTR_FIFO_CTL \ - CVMX_ADD_IO_SEG(0x00014F0000000340ull) -#define CVMX_IPD_QOS0_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F0000000178ull) -#define CVMX_IPD_QOS1_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F0000000180ull) -#define CVMX_IPD_QOS2_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F0000000188ull) -#define CVMX_IPD_QOS3_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F0000000190ull) -#define CVMX_IPD_QOS4_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F0000000198ull) -#define CVMX_IPD_QOS5_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F00000001A0ull) -#define CVMX_IPD_QOS6_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F00000001A8ull) -#define CVMX_IPD_QOS7_RED_MARKS \ - CVMX_ADD_IO_SEG(0x00014F00000001B0ull) -#define CVMX_IPD_QOSX_RED_MARKS(offset) \ - CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8)) -#define CVMX_IPD_QUE0_FREE_PAGE_CNT \ - CVMX_ADD_IO_SEG(0x00014F0000000330ull) -#define CVMX_IPD_RED_PORT_ENABLE \ - CVMX_ADD_IO_SEG(0x00014F00000002D8ull) -#define CVMX_IPD_RED_PORT_ENABLE2 \ - CVMX_ADD_IO_SEG(0x00014F00000003A8ull) -#define CVMX_IPD_RED_QUE0_PARAM \ - CVMX_ADD_IO_SEG(0x00014F00000002E0ull) -#define CVMX_IPD_RED_QUE1_PARAM \ - CVMX_ADD_IO_SEG(0x00014F00000002E8ull) -#define CVMX_IPD_RED_QUE2_PARAM \ - CVMX_ADD_IO_SEG(0x00014F00000002F0ull) -#define CVMX_IPD_RED_QUE3_PARAM \ - CVMX_ADD_IO_SEG(0x00014F00000002F8ull) -#define CVMX_IPD_RED_QUE4_PARAM \ - CVMX_ADD_IO_SEG(0x00014F0000000300ull) -#define CVMX_IPD_RED_QUE5_PARAM \ - CVMX_ADD_IO_SEG(0x00014F0000000308ull) -#define CVMX_IPD_RED_QUE6_PARAM \ - CVMX_ADD_IO_SEG(0x00014F0000000310ull) -#define CVMX_IPD_RED_QUE7_PARAM \ - CVMX_ADD_IO_SEG(0x00014F0000000318ull) -#define CVMX_IPD_RED_QUEX_PARAM(offset) \ - CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8)) -#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \ - CVMX_ADD_IO_SEG(0x00014F0000000148ull) -#define CVMX_IPD_SUB_PORT_FCS \ - CVMX_ADD_IO_SEG(0x00014F0000000170ull) -#define CVMX_IPD_SUB_PORT_QOS_CNT \ - CVMX_ADD_IO_SEG(0x00014F0000000800ull) -#define CVMX_IPD_WQE_FPA_QUEUE \ - CVMX_ADD_IO_SEG(0x00014F0000000020ull) -#define CVMX_IPD_WQE_PTR_VALID \ - CVMX_ADD_IO_SEG(0x00014F0000000360ull) - -union cvmx_ipd_1st_mbuff_skip { - uint64_t u64; - struct cvmx_ipd_1st_mbuff_skip_s { - uint64_t reserved_6_63:58; - uint64_t skip_sz:6; - } s; - struct cvmx_ipd_1st_mbuff_skip_s cn30xx; - struct cvmx_ipd_1st_mbuff_skip_s cn31xx; - struct cvmx_ipd_1st_mbuff_skip_s cn38xx; - struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2; - struct cvmx_ipd_1st_mbuff_skip_s cn50xx; - struct cvmx_ipd_1st_mbuff_skip_s cn52xx; - struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1; - struct cvmx_ipd_1st_mbuff_skip_s cn56xx; - struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; - struct cvmx_ipd_1st_mbuff_skip_s cn58xx; - struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; -}; - -union cvmx_ipd_1st_next_ptr_back { - uint64_t u64; - struct cvmx_ipd_1st_next_ptr_back_s { - uint64_t reserved_4_63:60; - uint64_t back:4; - } s; - struct cvmx_ipd_1st_next_ptr_back_s cn30xx; - struct cvmx_ipd_1st_next_ptr_back_s cn31xx; - struct cvmx_ipd_1st_next_ptr_back_s cn38xx; - struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2; - struct cvmx_ipd_1st_next_ptr_back_s cn50xx; - struct cvmx_ipd_1st_next_ptr_back_s cn52xx; - struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1; - struct cvmx_ipd_1st_next_ptr_back_s cn56xx; - struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; - struct cvmx_ipd_1st_next_ptr_back_s cn58xx; - struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; -}; - -union cvmx_ipd_2nd_next_ptr_back { - uint64_t u64; - struct cvmx_ipd_2nd_next_ptr_back_s { - uint64_t reserved_4_63:60; - uint64_t back:4; - } s; - struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn38xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2; - struct cvmx_ipd_2nd_next_ptr_back_s cn50xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn52xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1; - struct cvmx_ipd_2nd_next_ptr_back_s cn56xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; - struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; - struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; -}; - -union cvmx_ipd_bist_status { - uint64_t u64; - struct cvmx_ipd_bist_status_s { - uint64_t reserved_18_63:46; - uint64_t csr_mem:1; - uint64_t csr_ncmd:1; - uint64_t pwq_wqed:1; - uint64_t pwq_wp1:1; - uint64_t pwq_pow:1; - uint64_t ipq_pbe1:1; - uint64_t ipq_pbe0:1; - uint64_t pbm3:1; - uint64_t pbm2:1; - uint64_t pbm1:1; - uint64_t pbm0:1; - uint64_t pbm_word:1; - uint64_t pwq1:1; - uint64_t pwq0:1; - uint64_t prc_off:1; - uint64_t ipd_old:1; - uint64_t ipd_new:1; - uint64_t pwp:1; - } s; - struct cvmx_ipd_bist_status_cn30xx { - uint64_t reserved_16_63:48; - uint64_t pwq_wqed:1; - uint64_t pwq_wp1:1; - uint64_t pwq_pow:1; - uint64_t ipq_pbe1:1; - uint64_t ipq_pbe0:1; - uint64_t pbm3:1; - uint64_t pbm2:1; - uint64_t pbm1:1; - uint64_t pbm0:1; - uint64_t pbm_word:1; - uint64_t pwq1:1; - uint64_t pwq0:1; - uint64_t prc_off:1; - uint64_t ipd_old:1; - uint64_t ipd_new:1; - uint64_t pwp:1; - } cn30xx; - struct cvmx_ipd_bist_status_cn30xx cn31xx; - struct cvmx_ipd_bist_status_cn30xx cn38xx; - struct cvmx_ipd_bist_status_cn30xx cn38xxp2; - struct cvmx_ipd_bist_status_cn30xx cn50xx; - struct cvmx_ipd_bist_status_s cn52xx; - struct cvmx_ipd_bist_status_s cn52xxp1; - struct cvmx_ipd_bist_status_s cn56xx; - struct cvmx_ipd_bist_status_s cn56xxp1; - struct cvmx_ipd_bist_status_cn30xx cn58xx; - struct cvmx_ipd_bist_status_cn30xx cn58xxp1; -}; - -union cvmx_ipd_bp_prt_red_end { - uint64_t u64; - struct cvmx_ipd_bp_prt_red_end_s { - uint64_t reserved_40_63:24; - uint64_t prt_enb:40; - } s; - struct cvmx_ipd_bp_prt_red_end_cn30xx { - uint64_t reserved_36_63:28; - uint64_t prt_enb:36; - } cn30xx; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; - struct cvmx_ipd_bp_prt_red_end_s cn52xx; - struct cvmx_ipd_bp_prt_red_end_s cn52xxp1; - struct cvmx_ipd_bp_prt_red_end_s cn56xx; - struct cvmx_ipd_bp_prt_red_end_s cn56xxp1; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; - struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; -}; - -union cvmx_ipd_clk_count { - uint64_t u64; - struct cvmx_ipd_clk_count_s { - uint64_t clk_cnt:64; - } s; - struct cvmx_ipd_clk_count_s cn30xx; - struct cvmx_ipd_clk_count_s cn31xx; - struct cvmx_ipd_clk_count_s cn38xx; - struct cvmx_ipd_clk_count_s cn38xxp2; - struct cvmx_ipd_clk_count_s cn50xx; - struct cvmx_ipd_clk_count_s cn52xx; - struct cvmx_ipd_clk_count_s cn52xxp1; - struct cvmx_ipd_clk_count_s cn56xx; - struct cvmx_ipd_clk_count_s cn56xxp1; - struct cvmx_ipd_clk_count_s cn58xx; - struct cvmx_ipd_clk_count_s cn58xxp1; -}; - -union cvmx_ipd_ctl_status { - uint64_t u64; - struct cvmx_ipd_ctl_status_s { - uint64_t reserved_15_63:49; - uint64_t no_wptr:1; - uint64_t pq_apkt:1; - uint64_t pq_nabuf:1; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } s; - struct cvmx_ipd_ctl_status_cn30xx { - uint64_t reserved_10_63:54; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn30xx; - struct cvmx_ipd_ctl_status_cn30xx cn31xx; - struct cvmx_ipd_ctl_status_cn30xx cn38xx; - struct cvmx_ipd_ctl_status_cn38xxp2 { - uint64_t reserved_9_63:55; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn38xxp2; - struct cvmx_ipd_ctl_status_s cn50xx; - struct cvmx_ipd_ctl_status_s cn52xx; - struct cvmx_ipd_ctl_status_s cn52xxp1; - struct cvmx_ipd_ctl_status_s cn56xx; - struct cvmx_ipd_ctl_status_s cn56xxp1; - struct cvmx_ipd_ctl_status_cn58xx { - uint64_t reserved_12_63:52; - uint64_t ipd_full:1; - uint64_t pkt_off:1; - uint64_t len_m8:1; - uint64_t reset:1; - uint64_t addpkt:1; - uint64_t naddbuf:1; - uint64_t pkt_lend:1; - uint64_t wqe_lend:1; - uint64_t pbp_en:1; - uint64_t opc_mode:2; - uint64_t ipd_en:1; - } cn58xx; - struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; -}; - -union cvmx_ipd_int_enb { - uint64_t u64; - struct cvmx_ipd_int_enb_s { - uint64_t reserved_12_63:52; - uint64_t pq_sub:1; - uint64_t pq_add:1; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } s; - struct cvmx_ipd_int_enb_cn30xx { - uint64_t reserved_5_63:59; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } cn30xx; - struct cvmx_ipd_int_enb_cn30xx cn31xx; - struct cvmx_ipd_int_enb_cn38xx { - uint64_t reserved_10_63:54; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } cn38xx; - struct cvmx_ipd_int_enb_cn30xx cn38xxp2; - struct cvmx_ipd_int_enb_cn38xx cn50xx; - struct cvmx_ipd_int_enb_s cn52xx; - struct cvmx_ipd_int_enb_s cn52xxp1; - struct cvmx_ipd_int_enb_s cn56xx; - struct cvmx_ipd_int_enb_s cn56xxp1; - struct cvmx_ipd_int_enb_cn38xx cn58xx; - struct cvmx_ipd_int_enb_cn38xx cn58xxp1; -}; - -union cvmx_ipd_int_sum { - uint64_t u64; - struct cvmx_ipd_int_sum_s { - uint64_t reserved_12_63:52; - uint64_t pq_sub:1; - uint64_t pq_add:1; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } s; - struct cvmx_ipd_int_sum_cn30xx { - uint64_t reserved_5_63:59; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } cn30xx; - struct cvmx_ipd_int_sum_cn30xx cn31xx; - struct cvmx_ipd_int_sum_cn38xx { - uint64_t reserved_10_63:54; - uint64_t bc_ovr:1; - uint64_t d_coll:1; - uint64_t c_coll:1; - uint64_t cc_ovr:1; - uint64_t dc_ovr:1; - uint64_t bp_sub:1; - uint64_t prc_par3:1; - uint64_t prc_par2:1; - uint64_t prc_par1:1; - uint64_t prc_par0:1; - } cn38xx; - struct cvmx_ipd_int_sum_cn30xx cn38xxp2; - struct cvmx_ipd_int_sum_cn38xx cn50xx; - struct cvmx_ipd_int_sum_s cn52xx; - struct cvmx_ipd_int_sum_s cn52xxp1; - struct cvmx_ipd_int_sum_s cn56xx; - struct cvmx_ipd_int_sum_s cn56xxp1; - struct cvmx_ipd_int_sum_cn38xx cn58xx; - struct cvmx_ipd_int_sum_cn38xx cn58xxp1; -}; - -union cvmx_ipd_not_1st_mbuff_skip { - uint64_t u64; - struct cvmx_ipd_not_1st_mbuff_skip_s { - uint64_t reserved_6_63:58; - uint64_t skip_sz:6; - } s; - struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2; - struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1; - struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; - struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; - struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; -}; - -union cvmx_ipd_packet_mbuff_size { - uint64_t u64; - struct cvmx_ipd_packet_mbuff_size_s { - uint64_t reserved_12_63:52; - uint64_t mb_size:12; - } s; - struct cvmx_ipd_packet_mbuff_size_s cn30xx; - struct cvmx_ipd_packet_mbuff_size_s cn31xx; - struct cvmx_ipd_packet_mbuff_size_s cn38xx; - struct cvmx_ipd_packet_mbuff_size_s cn38xxp2; - struct cvmx_ipd_packet_mbuff_size_s cn50xx; - struct cvmx_ipd_packet_mbuff_size_s cn52xx; - struct cvmx_ipd_packet_mbuff_size_s cn52xxp1; - struct cvmx_ipd_packet_mbuff_size_s cn56xx; - struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; - struct cvmx_ipd_packet_mbuff_size_s cn58xx; - struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; -}; - -union cvmx_ipd_pkt_ptr_valid { - uint64_t u64; - struct cvmx_ipd_pkt_ptr_valid_s { - uint64_t reserved_29_63:35; - uint64_t ptr:29; - } s; - struct cvmx_ipd_pkt_ptr_valid_s cn30xx; - struct cvmx_ipd_pkt_ptr_valid_s cn31xx; - struct cvmx_ipd_pkt_ptr_valid_s cn38xx; - struct cvmx_ipd_pkt_ptr_valid_s cn50xx; - struct cvmx_ipd_pkt_ptr_valid_s cn52xx; - struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1; - struct cvmx_ipd_pkt_ptr_valid_s cn56xx; - struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; - struct cvmx_ipd_pkt_ptr_valid_s cn58xx; - struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; -}; - -union cvmx_ipd_portx_bp_page_cnt { - uint64_t u64; - struct cvmx_ipd_portx_bp_page_cnt_s { - uint64_t reserved_18_63:46; - uint64_t bp_enb:1; - uint64_t page_cnt:17; - } s; - struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn38xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2; - struct cvmx_ipd_portx_bp_page_cnt_s cn50xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn52xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1; - struct cvmx_ipd_portx_bp_page_cnt_s cn56xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; - struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; - struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; -}; - -union cvmx_ipd_portx_bp_page_cnt2 { - uint64_t u64; - struct cvmx_ipd_portx_bp_page_cnt2_s { - uint64_t reserved_18_63:46; - uint64_t bp_enb:1; - uint64_t page_cnt:17; - } s; - struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; - struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; - struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; - struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; -}; - -union cvmx_ipd_port_bp_counters2_pairx { - uint64_t u64; - struct cvmx_ipd_port_bp_counters2_pairx_s { - uint64_t reserved_25_63:39; - uint64_t cnt_val:25; - } s; - struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; - struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; - struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; - struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; -}; - -union cvmx_ipd_port_bp_counters_pairx { - uint64_t u64; - struct cvmx_ipd_port_bp_counters_pairx_s { - uint64_t reserved_25_63:39; - uint64_t cnt_val:25; - } s; - struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn38xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2; - struct cvmx_ipd_port_bp_counters_pairx_s cn50xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn52xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1; - struct cvmx_ipd_port_bp_counters_pairx_s cn56xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; - struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; - struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; -}; - -union cvmx_ipd_port_qos_x_cnt { - uint64_t u64; - struct cvmx_ipd_port_qos_x_cnt_s { - uint64_t wmark:32; - uint64_t cnt:32; - } s; - struct cvmx_ipd_port_qos_x_cnt_s cn52xx; - struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; - struct cvmx_ipd_port_qos_x_cnt_s cn56xx; - struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; -}; - -union cvmx_ipd_port_qos_intx { - uint64_t u64; - struct cvmx_ipd_port_qos_intx_s { - uint64_t intr:64; - } s; - struct cvmx_ipd_port_qos_intx_s cn52xx; - struct cvmx_ipd_port_qos_intx_s cn52xxp1; - struct cvmx_ipd_port_qos_intx_s cn56xx; - struct cvmx_ipd_port_qos_intx_s cn56xxp1; -}; - -union cvmx_ipd_port_qos_int_enbx { - uint64_t u64; - struct cvmx_ipd_port_qos_int_enbx_s { - uint64_t enb:64; - } s; - struct cvmx_ipd_port_qos_int_enbx_s cn52xx; - struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; - struct cvmx_ipd_port_qos_int_enbx_s cn56xx; - struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; -}; - -union cvmx_ipd_prc_hold_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { - uint64_t reserved_39_63:25; - uint64_t max_pkt:3; - uint64_t praddr:3; - uint64_t ptr:29; - uint64_t cena:1; - uint64_t raddr:3; - } s; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; - struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; -}; - -union cvmx_ipd_prc_port_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { - uint64_t reserved_44_63:20; - uint64_t max_pkt:7; - uint64_t ptr:29; - uint64_t cena:1; - uint64_t raddr:7; - } s; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; - struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; -}; - -union cvmx_ipd_ptr_count { - uint64_t u64; - struct cvmx_ipd_ptr_count_s { - uint64_t reserved_19_63:45; - uint64_t pktv_cnt:1; - uint64_t wqev_cnt:1; - uint64_t pfif_cnt:3; - uint64_t pkt_pcnt:7; - uint64_t wqe_pcnt:7; - } s; - struct cvmx_ipd_ptr_count_s cn30xx; - struct cvmx_ipd_ptr_count_s cn31xx; - struct cvmx_ipd_ptr_count_s cn38xx; - struct cvmx_ipd_ptr_count_s cn38xxp2; - struct cvmx_ipd_ptr_count_s cn50xx; - struct cvmx_ipd_ptr_count_s cn52xx; - struct cvmx_ipd_ptr_count_s cn52xxp1; - struct cvmx_ipd_ptr_count_s cn56xx; - struct cvmx_ipd_ptr_count_s cn56xxp1; - struct cvmx_ipd_ptr_count_s cn58xx; - struct cvmx_ipd_ptr_count_s cn58xxp1; -}; - -union cvmx_ipd_pwp_ptr_fifo_ctl { - uint64_t u64; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s { - uint64_t reserved_61_63:3; - uint64_t max_cnts:7; - uint64_t wraddr:8; - uint64_t praddr:8; - uint64_t ptr:29; - uint64_t cena:1; - uint64_t raddr:8; - } s; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; - struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; -}; - -union cvmx_ipd_qosx_red_marks { - uint64_t u64; - struct cvmx_ipd_qosx_red_marks_s { - uint64_t drop:32; - uint64_t pass:32; - } s; - struct cvmx_ipd_qosx_red_marks_s cn30xx; - struct cvmx_ipd_qosx_red_marks_s cn31xx; - struct cvmx_ipd_qosx_red_marks_s cn38xx; - struct cvmx_ipd_qosx_red_marks_s cn38xxp2; - struct cvmx_ipd_qosx_red_marks_s cn50xx; - struct cvmx_ipd_qosx_red_marks_s cn52xx; - struct cvmx_ipd_qosx_red_marks_s cn52xxp1; - struct cvmx_ipd_qosx_red_marks_s cn56xx; - struct cvmx_ipd_qosx_red_marks_s cn56xxp1; - struct cvmx_ipd_qosx_red_marks_s cn58xx; - struct cvmx_ipd_qosx_red_marks_s cn58xxp1; -}; - -union cvmx_ipd_que0_free_page_cnt { - uint64_t u64; - struct cvmx_ipd_que0_free_page_cnt_s { - uint64_t reserved_32_63:32; - uint64_t q0_pcnt:32; - } s; - struct cvmx_ipd_que0_free_page_cnt_s cn30xx; - struct cvmx_ipd_que0_free_page_cnt_s cn31xx; - struct cvmx_ipd_que0_free_page_cnt_s cn38xx; - struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2; - struct cvmx_ipd_que0_free_page_cnt_s cn50xx; - struct cvmx_ipd_que0_free_page_cnt_s cn52xx; - struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1; - struct cvmx_ipd_que0_free_page_cnt_s cn56xx; - struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; - struct cvmx_ipd_que0_free_page_cnt_s cn58xx; - struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; -}; - -union cvmx_ipd_red_port_enable { - uint64_t u64; - struct cvmx_ipd_red_port_enable_s { - uint64_t prb_dly:14; - uint64_t avg_dly:14; - uint64_t prt_enb:36; - } s; - struct cvmx_ipd_red_port_enable_s cn30xx; - struct cvmx_ipd_red_port_enable_s cn31xx; - struct cvmx_ipd_red_port_enable_s cn38xx; - struct cvmx_ipd_red_port_enable_s cn38xxp2; - struct cvmx_ipd_red_port_enable_s cn50xx; - struct cvmx_ipd_red_port_enable_s cn52xx; - struct cvmx_ipd_red_port_enable_s cn52xxp1; - struct cvmx_ipd_red_port_enable_s cn56xx; - struct cvmx_ipd_red_port_enable_s cn56xxp1; - struct cvmx_ipd_red_port_enable_s cn58xx; - struct cvmx_ipd_red_port_enable_s cn58xxp1; -}; - -union cvmx_ipd_red_port_enable2 { - uint64_t u64; - struct cvmx_ipd_red_port_enable2_s { - uint64_t reserved_4_63:60; - uint64_t prt_enb:4; - } s; - struct cvmx_ipd_red_port_enable2_s cn52xx; - struct cvmx_ipd_red_port_enable2_s cn52xxp1; - struct cvmx_ipd_red_port_enable2_s cn56xx; - struct cvmx_ipd_red_port_enable2_s cn56xxp1; -}; - -union cvmx_ipd_red_quex_param { - uint64_t u64; - struct cvmx_ipd_red_quex_param_s { - uint64_t reserved_49_63:15; - uint64_t use_pcnt:1; - uint64_t new_con:8; - uint64_t avg_con:8; - uint64_t prb_con:32; - } s; - struct cvmx_ipd_red_quex_param_s cn30xx; - struct cvmx_ipd_red_quex_param_s cn31xx; - struct cvmx_ipd_red_quex_param_s cn38xx; - struct cvmx_ipd_red_quex_param_s cn38xxp2; - struct cvmx_ipd_red_quex_param_s cn50xx; - struct cvmx_ipd_red_quex_param_s cn52xx; - struct cvmx_ipd_red_quex_param_s cn52xxp1; - struct cvmx_ipd_red_quex_param_s cn56xx; - struct cvmx_ipd_red_quex_param_s cn56xxp1; - struct cvmx_ipd_red_quex_param_s cn58xx; - struct cvmx_ipd_red_quex_param_s cn58xxp1; -}; - -union cvmx_ipd_sub_port_bp_page_cnt { - uint64_t u64; - struct cvmx_ipd_sub_port_bp_page_cnt_s { - uint64_t reserved_31_63:33; - uint64_t port:6; - uint64_t page_cnt:25; - } s; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; - struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; -}; - -union cvmx_ipd_sub_port_fcs { - uint64_t u64; - struct cvmx_ipd_sub_port_fcs_s { - uint64_t reserved_40_63:24; - uint64_t port_bit2:4; - uint64_t reserved_32_35:4; - uint64_t port_bit:32; - } s; - struct cvmx_ipd_sub_port_fcs_cn30xx { - uint64_t reserved_3_63:61; - uint64_t port_bit:3; - } cn30xx; - struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; - struct cvmx_ipd_sub_port_fcs_cn38xx { - uint64_t reserved_32_63:32; - uint64_t port_bit:32; - } cn38xx; - struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; - struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; - struct cvmx_ipd_sub_port_fcs_s cn52xx; - struct cvmx_ipd_sub_port_fcs_s cn52xxp1; - struct cvmx_ipd_sub_port_fcs_s cn56xx; - struct cvmx_ipd_sub_port_fcs_s cn56xxp1; - struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; - struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; -}; - -union cvmx_ipd_sub_port_qos_cnt { - uint64_t u64; - struct cvmx_ipd_sub_port_qos_cnt_s { - uint64_t reserved_41_63:23; - uint64_t port_qos:9; - uint64_t cnt:32; - } s; - struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; - struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; - struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; - struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; -}; - -union cvmx_ipd_wqe_fpa_queue { - uint64_t u64; - struct cvmx_ipd_wqe_fpa_queue_s { - uint64_t reserved_3_63:61; - uint64_t wqe_pool:3; - } s; - struct cvmx_ipd_wqe_fpa_queue_s cn30xx; - struct cvmx_ipd_wqe_fpa_queue_s cn31xx; - struct cvmx_ipd_wqe_fpa_queue_s cn38xx; - struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2; - struct cvmx_ipd_wqe_fpa_queue_s cn50xx; - struct cvmx_ipd_wqe_fpa_queue_s cn52xx; - struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1; - struct cvmx_ipd_wqe_fpa_queue_s cn56xx; - struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; - struct cvmx_ipd_wqe_fpa_queue_s cn58xx; - struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; -}; - -union cvmx_ipd_wqe_ptr_valid { - uint64_t u64; - struct cvmx_ipd_wqe_ptr_valid_s { - uint64_t reserved_29_63:35; - uint64_t ptr:29; - } s; - struct cvmx_ipd_wqe_ptr_valid_s cn30xx; - struct cvmx_ipd_wqe_ptr_valid_s cn31xx; - struct cvmx_ipd_wqe_ptr_valid_s cn38xx; - struct cvmx_ipd_wqe_ptr_valid_s cn50xx; - struct cvmx_ipd_wqe_ptr_valid_s cn52xx; - struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1; - struct cvmx_ipd_wqe_ptr_valid_s cn56xx; - struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; - struct cvmx_ipd_wqe_ptr_valid_s cn58xx; - struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h deleted file mode 100644 index 337583842b51..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2c-defs.h +++ /dev/null @@ -1,963 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_L2C_DEFS_H__ -#define __CVMX_L2C_DEFS_H__ - -#define CVMX_L2C_BST0 \ - CVMX_ADD_IO_SEG(0x00011800800007F8ull) -#define CVMX_L2C_BST1 \ - CVMX_ADD_IO_SEG(0x00011800800007F0ull) -#define CVMX_L2C_BST2 \ - CVMX_ADD_IO_SEG(0x00011800800007E8ull) -#define CVMX_L2C_CFG \ - CVMX_ADD_IO_SEG(0x0001180080000000ull) -#define CVMX_L2C_DBG \ - CVMX_ADD_IO_SEG(0x0001180080000030ull) -#define CVMX_L2C_DUT \ - CVMX_ADD_IO_SEG(0x0001180080000050ull) -#define CVMX_L2C_GRPWRR0 \ - CVMX_ADD_IO_SEG(0x00011800800000C8ull) -#define CVMX_L2C_GRPWRR1 \ - CVMX_ADD_IO_SEG(0x00011800800000D0ull) -#define CVMX_L2C_INT_EN \ - CVMX_ADD_IO_SEG(0x0001180080000100ull) -#define CVMX_L2C_INT_STAT \ - CVMX_ADD_IO_SEG(0x00011800800000F8ull) -#define CVMX_L2C_LCKBASE \ - CVMX_ADD_IO_SEG(0x0001180080000058ull) -#define CVMX_L2C_LCKOFF \ - CVMX_ADD_IO_SEG(0x0001180080000060ull) -#define CVMX_L2C_LFB0 \ - CVMX_ADD_IO_SEG(0x0001180080000038ull) -#define CVMX_L2C_LFB1 \ - CVMX_ADD_IO_SEG(0x0001180080000040ull) -#define CVMX_L2C_LFB2 \ - CVMX_ADD_IO_SEG(0x0001180080000048ull) -#define CVMX_L2C_LFB3 \ - CVMX_ADD_IO_SEG(0x00011800800000B8ull) -#define CVMX_L2C_OOB \ - CVMX_ADD_IO_SEG(0x00011800800000D8ull) -#define CVMX_L2C_OOB1 \ - CVMX_ADD_IO_SEG(0x00011800800000E0ull) -#define CVMX_L2C_OOB2 \ - CVMX_ADD_IO_SEG(0x00011800800000E8ull) -#define CVMX_L2C_OOB3 \ - CVMX_ADD_IO_SEG(0x00011800800000F0ull) -#define CVMX_L2C_PFC0 \ - CVMX_ADD_IO_SEG(0x0001180080000098ull) -#define CVMX_L2C_PFC1 \ - CVMX_ADD_IO_SEG(0x00011800800000A0ull) -#define CVMX_L2C_PFC2 \ - CVMX_ADD_IO_SEG(0x00011800800000A8ull) -#define CVMX_L2C_PFC3 \ - CVMX_ADD_IO_SEG(0x00011800800000B0ull) -#define CVMX_L2C_PFCTL \ - CVMX_ADD_IO_SEG(0x0001180080000090ull) -#define CVMX_L2C_PFCX(offset) \ - CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8)) -#define CVMX_L2C_PPGRP \ - CVMX_ADD_IO_SEG(0x00011800800000C0ull) -#define CVMX_L2C_SPAR0 \ - CVMX_ADD_IO_SEG(0x0001180080000068ull) -#define CVMX_L2C_SPAR1 \ - CVMX_ADD_IO_SEG(0x0001180080000070ull) -#define CVMX_L2C_SPAR2 \ - CVMX_ADD_IO_SEG(0x0001180080000078ull) -#define CVMX_L2C_SPAR3 \ - CVMX_ADD_IO_SEG(0x0001180080000080ull) -#define CVMX_L2C_SPAR4 \ - CVMX_ADD_IO_SEG(0x0001180080000088ull) - -union cvmx_l2c_bst0 { - uint64_t u64; - struct cvmx_l2c_bst0_s { - uint64_t reserved_24_63:40; - uint64_t dtbnk:1; - uint64_t wlb_msk:4; - uint64_t dtcnt:13; - uint64_t dt:1; - uint64_t stin_msk:1; - uint64_t wlb_dat:4; - } s; - struct cvmx_l2c_bst0_cn30xx { - uint64_t reserved_23_63:41; - uint64_t wlb_msk:4; - uint64_t reserved_15_18:4; - uint64_t dtcnt:9; - uint64_t dt:1; - uint64_t reserved_4_4:1; - uint64_t wlb_dat:4; - } cn30xx; - struct cvmx_l2c_bst0_cn31xx { - uint64_t reserved_23_63:41; - uint64_t wlb_msk:4; - uint64_t reserved_16_18:3; - uint64_t dtcnt:10; - uint64_t dt:1; - uint64_t stin_msk:1; - uint64_t wlb_dat:4; - } cn31xx; - struct cvmx_l2c_bst0_cn38xx { - uint64_t reserved_19_63:45; - uint64_t dtcnt:13; - uint64_t dt:1; - uint64_t stin_msk:1; - uint64_t wlb_dat:4; - } cn38xx; - struct cvmx_l2c_bst0_cn38xx cn38xxp2; - struct cvmx_l2c_bst0_cn50xx { - uint64_t reserved_24_63:40; - uint64_t dtbnk:1; - uint64_t wlb_msk:4; - uint64_t reserved_16_18:3; - uint64_t dtcnt:10; - uint64_t dt:1; - uint64_t stin_msk:1; - uint64_t wlb_dat:4; - } cn50xx; - struct cvmx_l2c_bst0_cn50xx cn52xx; - struct cvmx_l2c_bst0_cn50xx cn52xxp1; - struct cvmx_l2c_bst0_s cn56xx; - struct cvmx_l2c_bst0_s cn56xxp1; - struct cvmx_l2c_bst0_s cn58xx; - struct cvmx_l2c_bst0_s cn58xxp1; -}; - -union cvmx_l2c_bst1 { - uint64_t u64; - struct cvmx_l2c_bst1_s { - uint64_t reserved_9_63:55; - uint64_t l2t:9; - } s; - struct cvmx_l2c_bst1_cn30xx { - uint64_t reserved_16_63:48; - uint64_t vwdf:4; - uint64_t lrf:2; - uint64_t vab_vwcf:1; - uint64_t reserved_5_8:4; - uint64_t l2t:5; - } cn30xx; - struct cvmx_l2c_bst1_cn30xx cn31xx; - struct cvmx_l2c_bst1_cn38xx { - uint64_t reserved_16_63:48; - uint64_t vwdf:4; - uint64_t lrf:2; - uint64_t vab_vwcf:1; - uint64_t l2t:9; - } cn38xx; - struct cvmx_l2c_bst1_cn38xx cn38xxp2; - struct cvmx_l2c_bst1_cn38xx cn50xx; - struct cvmx_l2c_bst1_cn52xx { - uint64_t reserved_19_63:45; - uint64_t plc2:1; - uint64_t plc1:1; - uint64_t plc0:1; - uint64_t vwdf:4; - uint64_t reserved_11_11:1; - uint64_t ilc:1; - uint64_t vab_vwcf:1; - uint64_t l2t:9; - } cn52xx; - struct cvmx_l2c_bst1_cn52xx cn52xxp1; - struct cvmx_l2c_bst1_cn56xx { - uint64_t reserved_24_63:40; - uint64_t plc2:1; - uint64_t plc1:1; - uint64_t plc0:1; - uint64_t ilc:1; - uint64_t vwdf1:4; - uint64_t vwdf0:4; - uint64_t vab_vwcf1:1; - uint64_t reserved_10_10:1; - uint64_t vab_vwcf0:1; - uint64_t l2t:9; - } cn56xx; - struct cvmx_l2c_bst1_cn56xx cn56xxp1; - struct cvmx_l2c_bst1_cn38xx cn58xx; - struct cvmx_l2c_bst1_cn38xx cn58xxp1; -}; - -union cvmx_l2c_bst2 { - uint64_t u64; - struct cvmx_l2c_bst2_s { - uint64_t reserved_16_63:48; - uint64_t mrb:4; - uint64_t reserved_4_11:8; - uint64_t ipcbst:1; - uint64_t picbst:1; - uint64_t xrdmsk:1; - uint64_t xrddat:1; - } s; - struct cvmx_l2c_bst2_cn30xx { - uint64_t reserved_16_63:48; - uint64_t mrb:4; - uint64_t rmdf:4; - uint64_t reserved_4_7:4; - uint64_t ipcbst:1; - uint64_t reserved_2_2:1; - uint64_t xrdmsk:1; - uint64_t xrddat:1; - } cn30xx; - struct cvmx_l2c_bst2_cn30xx cn31xx; - struct cvmx_l2c_bst2_cn38xx { - uint64_t reserved_16_63:48; - uint64_t mrb:4; - uint64_t rmdf:4; - uint64_t rhdf:4; - uint64_t ipcbst:1; - uint64_t picbst:1; - uint64_t xrdmsk:1; - uint64_t xrddat:1; - } cn38xx; - struct cvmx_l2c_bst2_cn38xx cn38xxp2; - struct cvmx_l2c_bst2_cn30xx cn50xx; - struct cvmx_l2c_bst2_cn30xx cn52xx; - struct cvmx_l2c_bst2_cn30xx cn52xxp1; - struct cvmx_l2c_bst2_cn56xx { - uint64_t reserved_16_63:48; - uint64_t mrb:4; - uint64_t rmdb:4; - uint64_t rhdb:4; - uint64_t ipcbst:1; - uint64_t picbst:1; - uint64_t xrdmsk:1; - uint64_t xrddat:1; - } cn56xx; - struct cvmx_l2c_bst2_cn56xx cn56xxp1; - struct cvmx_l2c_bst2_cn56xx cn58xx; - struct cvmx_l2c_bst2_cn56xx cn58xxp1; -}; - -union cvmx_l2c_cfg { - uint64_t u64; - struct cvmx_l2c_cfg_s { - uint64_t reserved_20_63:44; - uint64_t bstrun:1; - uint64_t lbist:1; - uint64_t xor_bank:1; - uint64_t dpres1:1; - uint64_t dpres0:1; - uint64_t dfill_dis:1; - uint64_t fpexp:4; - uint64_t fpempty:1; - uint64_t fpen:1; - uint64_t idxalias:1; - uint64_t mwf_crd:4; - uint64_t rsp_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t lrf_arb_mode:1; - } s; - struct cvmx_l2c_cfg_cn30xx { - uint64_t reserved_14_63:50; - uint64_t fpexp:4; - uint64_t fpempty:1; - uint64_t fpen:1; - uint64_t idxalias:1; - uint64_t mwf_crd:4; - uint64_t rsp_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t lrf_arb_mode:1; - } cn30xx; - struct cvmx_l2c_cfg_cn30xx cn31xx; - struct cvmx_l2c_cfg_cn30xx cn38xx; - struct cvmx_l2c_cfg_cn30xx cn38xxp2; - struct cvmx_l2c_cfg_cn50xx { - uint64_t reserved_20_63:44; - uint64_t bstrun:1; - uint64_t lbist:1; - uint64_t reserved_14_17:4; - uint64_t fpexp:4; - uint64_t fpempty:1; - uint64_t fpen:1; - uint64_t idxalias:1; - uint64_t mwf_crd:4; - uint64_t rsp_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t lrf_arb_mode:1; - } cn50xx; - struct cvmx_l2c_cfg_cn50xx cn52xx; - struct cvmx_l2c_cfg_cn50xx cn52xxp1; - struct cvmx_l2c_cfg_s cn56xx; - struct cvmx_l2c_cfg_s cn56xxp1; - struct cvmx_l2c_cfg_cn58xx { - uint64_t reserved_20_63:44; - uint64_t bstrun:1; - uint64_t lbist:1; - uint64_t reserved_15_17:3; - uint64_t dfill_dis:1; - uint64_t fpexp:4; - uint64_t fpempty:1; - uint64_t fpen:1; - uint64_t idxalias:1; - uint64_t mwf_crd:4; - uint64_t rsp_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t lrf_arb_mode:1; - } cn58xx; - struct cvmx_l2c_cfg_cn58xxp1 { - uint64_t reserved_15_63:49; - uint64_t dfill_dis:1; - uint64_t fpexp:4; - uint64_t fpempty:1; - uint64_t fpen:1; - uint64_t idxalias:1; - uint64_t mwf_crd:4; - uint64_t rsp_arb_mode:1; - uint64_t rfb_arb_mode:1; - uint64_t lrf_arb_mode:1; - } cn58xxp1; -}; - -union cvmx_l2c_dbg { - uint64_t u64; - struct cvmx_l2c_dbg_s { - uint64_t reserved_15_63:49; - uint64_t lfb_enum:4; - uint64_t lfb_dmp:1; - uint64_t ppnum:4; - uint64_t set:3; - uint64_t finv:1; - uint64_t l2d:1; - uint64_t l2t:1; - } s; - struct cvmx_l2c_dbg_cn30xx { - uint64_t reserved_13_63:51; - uint64_t lfb_enum:2; - uint64_t lfb_dmp:1; - uint64_t reserved_5_9:5; - uint64_t set:2; - uint64_t finv:1; - uint64_t l2d:1; - uint64_t l2t:1; - } cn30xx; - struct cvmx_l2c_dbg_cn31xx { - uint64_t reserved_14_63:50; - uint64_t lfb_enum:3; - uint64_t lfb_dmp:1; - uint64_t reserved_7_9:3; - uint64_t ppnum:1; - uint64_t reserved_5_5:1; - uint64_t set:2; - uint64_t finv:1; - uint64_t l2d:1; - uint64_t l2t:1; - } cn31xx; - struct cvmx_l2c_dbg_s cn38xx; - struct cvmx_l2c_dbg_s cn38xxp2; - struct cvmx_l2c_dbg_cn50xx { - uint64_t reserved_14_63:50; - uint64_t lfb_enum:3; - uint64_t lfb_dmp:1; - uint64_t reserved_7_9:3; - uint64_t ppnum:1; - uint64_t set:3; - uint64_t finv:1; - uint64_t l2d:1; - uint64_t l2t:1; - } cn50xx; - struct cvmx_l2c_dbg_cn52xx { - uint64_t reserved_14_63:50; - uint64_t lfb_enum:3; - uint64_t lfb_dmp:1; - uint64_t reserved_8_9:2; - uint64_t ppnum:2; - uint64_t set:3; - uint64_t finv:1; - uint64_t l2d:1; - uint64_t l2t:1; - } cn52xx; - struct cvmx_l2c_dbg_cn52xx cn52xxp1; - struct cvmx_l2c_dbg_s cn56xx; - struct cvmx_l2c_dbg_s cn56xxp1; - struct cvmx_l2c_dbg_s cn58xx; - struct cvmx_l2c_dbg_s cn58xxp1; -}; - -union cvmx_l2c_dut { - uint64_t u64; - struct cvmx_l2c_dut_s { - uint64_t reserved_32_63:32; - uint64_t dtena:1; - uint64_t reserved_30_30:1; - uint64_t dt_vld:1; - uint64_t dt_tag:29; - } s; - struct cvmx_l2c_dut_s cn30xx; - struct cvmx_l2c_dut_s cn31xx; - struct cvmx_l2c_dut_s cn38xx; - struct cvmx_l2c_dut_s cn38xxp2; - struct cvmx_l2c_dut_s cn50xx; - struct cvmx_l2c_dut_s cn52xx; - struct cvmx_l2c_dut_s cn52xxp1; - struct cvmx_l2c_dut_s cn56xx; - struct cvmx_l2c_dut_s cn56xxp1; - struct cvmx_l2c_dut_s cn58xx; - struct cvmx_l2c_dut_s cn58xxp1; -}; - -union cvmx_l2c_grpwrr0 { - uint64_t u64; - struct cvmx_l2c_grpwrr0_s { - uint64_t plc1rmsk:32; - uint64_t plc0rmsk:32; - } s; - struct cvmx_l2c_grpwrr0_s cn52xx; - struct cvmx_l2c_grpwrr0_s cn52xxp1; - struct cvmx_l2c_grpwrr0_s cn56xx; - struct cvmx_l2c_grpwrr0_s cn56xxp1; -}; - -union cvmx_l2c_grpwrr1 { - uint64_t u64; - struct cvmx_l2c_grpwrr1_s { - uint64_t ilcrmsk:32; - uint64_t plc2rmsk:32; - } s; - struct cvmx_l2c_grpwrr1_s cn52xx; - struct cvmx_l2c_grpwrr1_s cn52xxp1; - struct cvmx_l2c_grpwrr1_s cn56xx; - struct cvmx_l2c_grpwrr1_s cn56xxp1; -}; - -union cvmx_l2c_int_en { - uint64_t u64; - struct cvmx_l2c_int_en_s { - uint64_t reserved_9_63:55; - uint64_t lck2ena:1; - uint64_t lckena:1; - uint64_t l2ddeden:1; - uint64_t l2dsecen:1; - uint64_t l2tdeden:1; - uint64_t l2tsecen:1; - uint64_t oob3en:1; - uint64_t oob2en:1; - uint64_t oob1en:1; - } s; - struct cvmx_l2c_int_en_s cn52xx; - struct cvmx_l2c_int_en_s cn52xxp1; - struct cvmx_l2c_int_en_s cn56xx; - struct cvmx_l2c_int_en_s cn56xxp1; -}; - -union cvmx_l2c_int_stat { - uint64_t u64; - struct cvmx_l2c_int_stat_s { - uint64_t reserved_9_63:55; - uint64_t lck2:1; - uint64_t lck:1; - uint64_t l2dded:1; - uint64_t l2dsec:1; - uint64_t l2tded:1; - uint64_t l2tsec:1; - uint64_t oob3:1; - uint64_t oob2:1; - uint64_t oob1:1; - } s; - struct cvmx_l2c_int_stat_s cn52xx; - struct cvmx_l2c_int_stat_s cn52xxp1; - struct cvmx_l2c_int_stat_s cn56xx; - struct cvmx_l2c_int_stat_s cn56xxp1; -}; - -union cvmx_l2c_lckbase { - uint64_t u64; - struct cvmx_l2c_lckbase_s { - uint64_t reserved_31_63:33; - uint64_t lck_base:27; - uint64_t reserved_1_3:3; - uint64_t lck_ena:1; - } s; - struct cvmx_l2c_lckbase_s cn30xx; - struct cvmx_l2c_lckbase_s cn31xx; - struct cvmx_l2c_lckbase_s cn38xx; - struct cvmx_l2c_lckbase_s cn38xxp2; - struct cvmx_l2c_lckbase_s cn50xx; - struct cvmx_l2c_lckbase_s cn52xx; - struct cvmx_l2c_lckbase_s cn52xxp1; - struct cvmx_l2c_lckbase_s cn56xx; - struct cvmx_l2c_lckbase_s cn56xxp1; - struct cvmx_l2c_lckbase_s cn58xx; - struct cvmx_l2c_lckbase_s cn58xxp1; -}; - -union cvmx_l2c_lckoff { - uint64_t u64; - struct cvmx_l2c_lckoff_s { - uint64_t reserved_10_63:54; - uint64_t lck_offset:10; - } s; - struct cvmx_l2c_lckoff_s cn30xx; - struct cvmx_l2c_lckoff_s cn31xx; - struct cvmx_l2c_lckoff_s cn38xx; - struct cvmx_l2c_lckoff_s cn38xxp2; - struct cvmx_l2c_lckoff_s cn50xx; - struct cvmx_l2c_lckoff_s cn52xx; - struct cvmx_l2c_lckoff_s cn52xxp1; - struct cvmx_l2c_lckoff_s cn56xx; - struct cvmx_l2c_lckoff_s cn56xxp1; - struct cvmx_l2c_lckoff_s cn58xx; - struct cvmx_l2c_lckoff_s cn58xxp1; -}; - -union cvmx_l2c_lfb0 { - uint64_t u64; - struct cvmx_l2c_lfb0_s { - uint64_t reserved_32_63:32; - uint64_t stcpnd:1; - uint64_t stpnd:1; - uint64_t stinv:1; - uint64_t stcfl:1; - uint64_t vam:1; - uint64_t inxt:4; - uint64_t itl:1; - uint64_t ihd:1; - uint64_t set:3; - uint64_t vabnum:4; - uint64_t sid:9; - uint64_t cmd:4; - uint64_t vld:1; - } s; - struct cvmx_l2c_lfb0_cn30xx { - uint64_t reserved_32_63:32; - uint64_t stcpnd:1; - uint64_t stpnd:1; - uint64_t stinv:1; - uint64_t stcfl:1; - uint64_t vam:1; - uint64_t reserved_25_26:2; - uint64_t inxt:2; - uint64_t itl:1; - uint64_t ihd:1; - uint64_t reserved_20_20:1; - uint64_t set:2; - uint64_t reserved_16_17:2; - uint64_t vabnum:2; - uint64_t sid:9; - uint64_t cmd:4; - uint64_t vld:1; - } cn30xx; - struct cvmx_l2c_lfb0_cn31xx { - uint64_t reserved_32_63:32; - uint64_t stcpnd:1; - uint64_t stpnd:1; - uint64_t stinv:1; - uint64_t stcfl:1; - uint64_t vam:1; - uint64_t reserved_26_26:1; - uint64_t inxt:3; - uint64_t itl:1; - uint64_t ihd:1; - uint64_t reserved_20_20:1; - uint64_t set:2; - uint64_t reserved_17_17:1; - uint64_t vabnum:3; - uint64_t sid:9; - uint64_t cmd:4; - uint64_t vld:1; - } cn31xx; - struct cvmx_l2c_lfb0_s cn38xx; - struct cvmx_l2c_lfb0_s cn38xxp2; - struct cvmx_l2c_lfb0_cn50xx { - uint64_t reserved_32_63:32; - uint64_t stcpnd:1; - uint64_t stpnd:1; - uint64_t stinv:1; - uint64_t stcfl:1; - uint64_t vam:1; - uint64_t reserved_26_26:1; - uint64_t inxt:3; - uint64_t itl:1; - uint64_t ihd:1; - uint64_t set:3; - uint64_t reserved_17_17:1; - uint64_t vabnum:3; - uint64_t sid:9; - uint64_t cmd:4; - uint64_t vld:1; - } cn50xx; - struct cvmx_l2c_lfb0_cn50xx cn52xx; - struct cvmx_l2c_lfb0_cn50xx cn52xxp1; - struct cvmx_l2c_lfb0_s cn56xx; - struct cvmx_l2c_lfb0_s cn56xxp1; - struct cvmx_l2c_lfb0_s cn58xx; - struct cvmx_l2c_lfb0_s cn58xxp1; -}; - -union cvmx_l2c_lfb1 { - uint64_t u64; - struct cvmx_l2c_lfb1_s { - uint64_t reserved_19_63:45; - uint64_t dsgoing:1; - uint64_t bid:2; - uint64_t wtrsp:1; - uint64_t wtdw:1; - uint64_t wtdq:1; - uint64_t wtwhp:1; - uint64_t wtwhf:1; - uint64_t wtwrm:1; - uint64_t wtstm:1; - uint64_t wtrda:1; - uint64_t wtstdt:1; - uint64_t wtstrsp:1; - uint64_t wtstrsc:1; - uint64_t wtvtm:1; - uint64_t wtmfl:1; - uint64_t prbrty:1; - uint64_t wtprb:1; - uint64_t vld:1; - } s; - struct cvmx_l2c_lfb1_s cn30xx; - struct cvmx_l2c_lfb1_s cn31xx; - struct cvmx_l2c_lfb1_s cn38xx; - struct cvmx_l2c_lfb1_s cn38xxp2; - struct cvmx_l2c_lfb1_s cn50xx; - struct cvmx_l2c_lfb1_s cn52xx; - struct cvmx_l2c_lfb1_s cn52xxp1; - struct cvmx_l2c_lfb1_s cn56xx; - struct cvmx_l2c_lfb1_s cn56xxp1; - struct cvmx_l2c_lfb1_s cn58xx; - struct cvmx_l2c_lfb1_s cn58xxp1; -}; - -union cvmx_l2c_lfb2 { - uint64_t u64; - struct cvmx_l2c_lfb2_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_l2c_lfb2_cn30xx { - uint64_t reserved_27_63:37; - uint64_t lfb_tag:19; - uint64_t lfb_idx:8; - } cn30xx; - struct cvmx_l2c_lfb2_cn31xx { - uint64_t reserved_27_63:37; - uint64_t lfb_tag:17; - uint64_t lfb_idx:10; - } cn31xx; - struct cvmx_l2c_lfb2_cn31xx cn38xx; - struct cvmx_l2c_lfb2_cn31xx cn38xxp2; - struct cvmx_l2c_lfb2_cn50xx { - uint64_t reserved_27_63:37; - uint64_t lfb_tag:20; - uint64_t lfb_idx:7; - } cn50xx; - struct cvmx_l2c_lfb2_cn52xx { - uint64_t reserved_27_63:37; - uint64_t lfb_tag:18; - uint64_t lfb_idx:9; - } cn52xx; - struct cvmx_l2c_lfb2_cn52xx cn52xxp1; - struct cvmx_l2c_lfb2_cn56xx { - uint64_t reserved_27_63:37; - uint64_t lfb_tag:16; - uint64_t lfb_idx:11; - } cn56xx; - struct cvmx_l2c_lfb2_cn56xx cn56xxp1; - struct cvmx_l2c_lfb2_cn56xx cn58xx; - struct cvmx_l2c_lfb2_cn56xx cn58xxp1; -}; - -union cvmx_l2c_lfb3 { - uint64_t u64; - struct cvmx_l2c_lfb3_s { - uint64_t reserved_5_63:59; - uint64_t stpartdis:1; - uint64_t lfb_hwm:4; - } s; - struct cvmx_l2c_lfb3_cn30xx { - uint64_t reserved_5_63:59; - uint64_t stpartdis:1; - uint64_t reserved_2_3:2; - uint64_t lfb_hwm:2; - } cn30xx; - struct cvmx_l2c_lfb3_cn31xx { - uint64_t reserved_5_63:59; - uint64_t stpartdis:1; - uint64_t reserved_3_3:1; - uint64_t lfb_hwm:3; - } cn31xx; - struct cvmx_l2c_lfb3_s cn38xx; - struct cvmx_l2c_lfb3_s cn38xxp2; - struct cvmx_l2c_lfb3_cn31xx cn50xx; - struct cvmx_l2c_lfb3_cn31xx cn52xx; - struct cvmx_l2c_lfb3_cn31xx cn52xxp1; - struct cvmx_l2c_lfb3_s cn56xx; - struct cvmx_l2c_lfb3_s cn56xxp1; - struct cvmx_l2c_lfb3_s cn58xx; - struct cvmx_l2c_lfb3_s cn58xxp1; -}; - -union cvmx_l2c_oob { - uint64_t u64; - struct cvmx_l2c_oob_s { - uint64_t reserved_2_63:62; - uint64_t dwbena:1; - uint64_t stena:1; - } s; - struct cvmx_l2c_oob_s cn52xx; - struct cvmx_l2c_oob_s cn52xxp1; - struct cvmx_l2c_oob_s cn56xx; - struct cvmx_l2c_oob_s cn56xxp1; -}; - -union cvmx_l2c_oob1 { - uint64_t u64; - struct cvmx_l2c_oob1_s { - uint64_t fadr:27; - uint64_t fsrc:1; - uint64_t reserved_34_35:2; - uint64_t sadr:14; - uint64_t reserved_14_19:6; - uint64_t size:14; - } s; - struct cvmx_l2c_oob1_s cn52xx; - struct cvmx_l2c_oob1_s cn52xxp1; - struct cvmx_l2c_oob1_s cn56xx; - struct cvmx_l2c_oob1_s cn56xxp1; -}; - -union cvmx_l2c_oob2 { - uint64_t u64; - struct cvmx_l2c_oob2_s { - uint64_t fadr:27; - uint64_t fsrc:1; - uint64_t reserved_34_35:2; - uint64_t sadr:14; - uint64_t reserved_14_19:6; - uint64_t size:14; - } s; - struct cvmx_l2c_oob2_s cn52xx; - struct cvmx_l2c_oob2_s cn52xxp1; - struct cvmx_l2c_oob2_s cn56xx; - struct cvmx_l2c_oob2_s cn56xxp1; -}; - -union cvmx_l2c_oob3 { - uint64_t u64; - struct cvmx_l2c_oob3_s { - uint64_t fadr:27; - uint64_t fsrc:1; - uint64_t reserved_34_35:2; - uint64_t sadr:14; - uint64_t reserved_14_19:6; - uint64_t size:14; - } s; - struct cvmx_l2c_oob3_s cn52xx; - struct cvmx_l2c_oob3_s cn52xxp1; - struct cvmx_l2c_oob3_s cn56xx; - struct cvmx_l2c_oob3_s cn56xxp1; -}; - -union cvmx_l2c_pfcx { - uint64_t u64; - struct cvmx_l2c_pfcx_s { - uint64_t reserved_36_63:28; - uint64_t pfcnt0:36; - } s; - struct cvmx_l2c_pfcx_s cn30xx; - struct cvmx_l2c_pfcx_s cn31xx; - struct cvmx_l2c_pfcx_s cn38xx; - struct cvmx_l2c_pfcx_s cn38xxp2; - struct cvmx_l2c_pfcx_s cn50xx; - struct cvmx_l2c_pfcx_s cn52xx; - struct cvmx_l2c_pfcx_s cn52xxp1; - struct cvmx_l2c_pfcx_s cn56xx; - struct cvmx_l2c_pfcx_s cn56xxp1; - struct cvmx_l2c_pfcx_s cn58xx; - struct cvmx_l2c_pfcx_s cn58xxp1; -}; - -union cvmx_l2c_pfctl { - uint64_t u64; - struct cvmx_l2c_pfctl_s { - uint64_t reserved_36_63:28; - uint64_t cnt3rdclr:1; - uint64_t cnt2rdclr:1; - uint64_t cnt1rdclr:1; - uint64_t cnt0rdclr:1; - uint64_t cnt3ena:1; - uint64_t cnt3clr:1; - uint64_t cnt3sel:6; - uint64_t cnt2ena:1; - uint64_t cnt2clr:1; - uint64_t cnt2sel:6; - uint64_t cnt1ena:1; - uint64_t cnt1clr:1; - uint64_t cnt1sel:6; - uint64_t cnt0ena:1; - uint64_t cnt0clr:1; - uint64_t cnt0sel:6; - } s; - struct cvmx_l2c_pfctl_s cn30xx; - struct cvmx_l2c_pfctl_s cn31xx; - struct cvmx_l2c_pfctl_s cn38xx; - struct cvmx_l2c_pfctl_s cn38xxp2; - struct cvmx_l2c_pfctl_s cn50xx; - struct cvmx_l2c_pfctl_s cn52xx; - struct cvmx_l2c_pfctl_s cn52xxp1; - struct cvmx_l2c_pfctl_s cn56xx; - struct cvmx_l2c_pfctl_s cn56xxp1; - struct cvmx_l2c_pfctl_s cn58xx; - struct cvmx_l2c_pfctl_s cn58xxp1; -}; - -union cvmx_l2c_ppgrp { - uint64_t u64; - struct cvmx_l2c_ppgrp_s { - uint64_t reserved_24_63:40; - uint64_t pp11grp:2; - uint64_t pp10grp:2; - uint64_t pp9grp:2; - uint64_t pp8grp:2; - uint64_t pp7grp:2; - uint64_t pp6grp:2; - uint64_t pp5grp:2; - uint64_t pp4grp:2; - uint64_t pp3grp:2; - uint64_t pp2grp:2; - uint64_t pp1grp:2; - uint64_t pp0grp:2; - } s; - struct cvmx_l2c_ppgrp_cn52xx { - uint64_t reserved_8_63:56; - uint64_t pp3grp:2; - uint64_t pp2grp:2; - uint64_t pp1grp:2; - uint64_t pp0grp:2; - } cn52xx; - struct cvmx_l2c_ppgrp_cn52xx cn52xxp1; - struct cvmx_l2c_ppgrp_s cn56xx; - struct cvmx_l2c_ppgrp_s cn56xxp1; -}; - -union cvmx_l2c_spar0 { - uint64_t u64; - struct cvmx_l2c_spar0_s { - uint64_t reserved_32_63:32; - uint64_t umsk3:8; - uint64_t umsk2:8; - uint64_t umsk1:8; - uint64_t umsk0:8; - } s; - struct cvmx_l2c_spar0_cn30xx { - uint64_t reserved_4_63:60; - uint64_t umsk0:4; - } cn30xx; - struct cvmx_l2c_spar0_cn31xx { - uint64_t reserved_12_63:52; - uint64_t umsk1:4; - uint64_t reserved_4_7:4; - uint64_t umsk0:4; - } cn31xx; - struct cvmx_l2c_spar0_s cn38xx; - struct cvmx_l2c_spar0_s cn38xxp2; - struct cvmx_l2c_spar0_cn50xx { - uint64_t reserved_16_63:48; - uint64_t umsk1:8; - uint64_t umsk0:8; - } cn50xx; - struct cvmx_l2c_spar0_s cn52xx; - struct cvmx_l2c_spar0_s cn52xxp1; - struct cvmx_l2c_spar0_s cn56xx; - struct cvmx_l2c_spar0_s cn56xxp1; - struct cvmx_l2c_spar0_s cn58xx; - struct cvmx_l2c_spar0_s cn58xxp1; -}; - -union cvmx_l2c_spar1 { - uint64_t u64; - struct cvmx_l2c_spar1_s { - uint64_t reserved_32_63:32; - uint64_t umsk7:8; - uint64_t umsk6:8; - uint64_t umsk5:8; - uint64_t umsk4:8; - } s; - struct cvmx_l2c_spar1_s cn38xx; - struct cvmx_l2c_spar1_s cn38xxp2; - struct cvmx_l2c_spar1_s cn56xx; - struct cvmx_l2c_spar1_s cn56xxp1; - struct cvmx_l2c_spar1_s cn58xx; - struct cvmx_l2c_spar1_s cn58xxp1; -}; - -union cvmx_l2c_spar2 { - uint64_t u64; - struct cvmx_l2c_spar2_s { - uint64_t reserved_32_63:32; - uint64_t umsk11:8; - uint64_t umsk10:8; - uint64_t umsk9:8; - uint64_t umsk8:8; - } s; - struct cvmx_l2c_spar2_s cn38xx; - struct cvmx_l2c_spar2_s cn38xxp2; - struct cvmx_l2c_spar2_s cn56xx; - struct cvmx_l2c_spar2_s cn56xxp1; - struct cvmx_l2c_spar2_s cn58xx; - struct cvmx_l2c_spar2_s cn58xxp1; -}; - -union cvmx_l2c_spar3 { - uint64_t u64; - struct cvmx_l2c_spar3_s { - uint64_t reserved_32_63:32; - uint64_t umsk15:8; - uint64_t umsk14:8; - uint64_t umsk13:8; - uint64_t umsk12:8; - } s; - struct cvmx_l2c_spar3_s cn38xx; - struct cvmx_l2c_spar3_s cn38xxp2; - struct cvmx_l2c_spar3_s cn58xx; - struct cvmx_l2c_spar3_s cn58xxp1; -}; - -union cvmx_l2c_spar4 { - uint64_t u64; - struct cvmx_l2c_spar4_s { - uint64_t reserved_8_63:56; - uint64_t umskiob:8; - } s; - struct cvmx_l2c_spar4_cn30xx { - uint64_t reserved_4_63:60; - uint64_t umskiob:4; - } cn30xx; - struct cvmx_l2c_spar4_cn30xx cn31xx; - struct cvmx_l2c_spar4_s cn38xx; - struct cvmx_l2c_spar4_s cn38xxp2; - struct cvmx_l2c_spar4_s cn50xx; - struct cvmx_l2c_spar4_s cn52xx; - struct cvmx_l2c_spar4_s cn52xxp1; - struct cvmx_l2c_spar4_s cn56xx; - struct cvmx_l2c_spar4_s cn56xxp1; - struct cvmx_l2c_spar4_s cn58xx; - struct cvmx_l2c_spar4_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h deleted file mode 100644 index 2a8c0902ea50..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2c.h +++ /dev/null @@ -1,325 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Interface to the Level 2 Cache (L2C) control, measurement, and debugging - * facilities. - */ - -#ifndef __CVMX_L2C_H__ -#define __CVMX_L2C_H__ - -/* Deprecated macro, use function */ -#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() - -/* Deprecated macro, use function */ -#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() - -/* Deprecated macro, use function */ -#define CVMX_L2_SETS cvmx_l2c_get_num_sets() - -#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ -#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) - -/* Defines for index aliasing computations */ -#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \ - (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) - -#define CVMX_L2C_ALIAS_MASK \ - (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - -union cvmx_l2c_tag { - uint64_t u64; - struct { - uint64_t reserved:28; - uint64_t V:1; /* Line valid */ - uint64_t D:1; /* Line dirty */ - uint64_t L:1; /* Line locked */ - uint64_t U:1; /* Use, LRU eviction */ - uint64_t addr:32; /* Phys mem (not all bits valid) */ - } s; -}; - - /* L2C Performance Counter events. */ -enum cvmx_l2c_event { - CVMX_L2C_EVENT_CYCLES = 0, - CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, - CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, - CVMX_L2C_EVENT_DATA_MISS = 3, - CVMX_L2C_EVENT_DATA_HIT = 4, - CVMX_L2C_EVENT_MISS = 5, - CVMX_L2C_EVENT_HIT = 6, - CVMX_L2C_EVENT_VICTIM_HIT = 7, - CVMX_L2C_EVENT_INDEX_CONFLICT = 8, - CVMX_L2C_EVENT_TAG_PROBE = 9, - CVMX_L2C_EVENT_TAG_UPDATE = 10, - CVMX_L2C_EVENT_TAG_COMPLETE = 11, - CVMX_L2C_EVENT_TAG_DIRTY = 12, - CVMX_L2C_EVENT_DATA_STORE_NOP = 13, - CVMX_L2C_EVENT_DATA_STORE_READ = 14, - CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, - CVMX_L2C_EVENT_FILL_DATA_VALID = 16, - CVMX_L2C_EVENT_WRITE_REQUEST = 17, - CVMX_L2C_EVENT_READ_REQUEST = 18, - CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, - CVMX_L2C_EVENT_XMC_NOP = 20, - CVMX_L2C_EVENT_XMC_LDT = 21, - CVMX_L2C_EVENT_XMC_LDI = 22, - CVMX_L2C_EVENT_XMC_LDD = 23, - CVMX_L2C_EVENT_XMC_STF = 24, - CVMX_L2C_EVENT_XMC_STT = 25, - CVMX_L2C_EVENT_XMC_STP = 26, - CVMX_L2C_EVENT_XMC_STC = 27, - CVMX_L2C_EVENT_XMC_DWB = 28, - CVMX_L2C_EVENT_XMC_PL2 = 29, - CVMX_L2C_EVENT_XMC_PSL1 = 30, - CVMX_L2C_EVENT_XMC_IOBLD = 31, - CVMX_L2C_EVENT_XMC_IOBST = 32, - CVMX_L2C_EVENT_XMC_IOBDMA = 33, - CVMX_L2C_EVENT_XMC_IOBRSP = 34, - CVMX_L2C_EVENT_XMC_BUS_VALID = 35, - CVMX_L2C_EVENT_XMC_MEM_DATA = 36, - CVMX_L2C_EVENT_XMC_REFL_DATA = 37, - CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, - CVMX_L2C_EVENT_RSC_NOP = 39, - CVMX_L2C_EVENT_RSC_STDN = 40, - CVMX_L2C_EVENT_RSC_FILL = 41, - CVMX_L2C_EVENT_RSC_REFL = 42, - CVMX_L2C_EVENT_RSC_STIN = 43, - CVMX_L2C_EVENT_RSC_SCIN = 44, - CVMX_L2C_EVENT_RSC_SCFL = 45, - CVMX_L2C_EVENT_RSC_SCDN = 46, - CVMX_L2C_EVENT_RSC_DATA_VALID = 47, - CVMX_L2C_EVENT_RSC_VALID_FILL = 48, - CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, - CVMX_L2C_EVENT_RSC_VALID_REFL = 50, - CVMX_L2C_EVENT_LRF_REQ = 51, - CVMX_L2C_EVENT_DT_RD_ALLOC = 52, - CVMX_L2C_EVENT_DT_WR_INVAL = 53 -}; - -/** - * Configure one of the four L2 Cache performance counters to capture event - * occurences. - * - * @counter: The counter to configure. Range 0..3. - * @event: The type of L2 Cache event occurrence to count. - * @clear_on_read: When asserted, any read of the performance counter - * clears the counter. - * - * The routine does not clear the counter. - */ -void cvmx_l2c_config_perf(uint32_t counter, - enum cvmx_l2c_event event, uint32_t clear_on_read); -/** - * Read the given L2 Cache performance counter. The counter must be configured - * before reading, but this routine does not enforce this requirement. - * - * @counter: The counter to configure. Range 0..3. - * - * Returns The current counter value. - */ -uint64_t cvmx_l2c_read_perf(uint32_t counter); - -/** - * Return the L2 Cache way partitioning for a given core. - * - * @core: The core processor of interest. - * - * Returns The mask specifying the partitioning. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error - */ -int cvmx_l2c_get_core_way_partition(uint32_t core); - -/** - * Partitions the L2 cache for a core - * - * @core: The core that the partitioning applies to. - * - * @mask: The partitioning of the ways expressed as a binary mask. A 0 - * bit allows the core to evict cache lines from a way, while a - * 1 bit blocks the core from evicting any lines from that - * way. There must be at least one allowed way (0 bit) in the - * mask. - * - * If any ways are blocked for all cores and the HW blocks, then those - * ways will never have any cache lines evicted from them. All cores - * and the hardware blocks are free to read from all ways regardless - * of the partitioning. - */ -int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); - -/** - * Return the L2 Cache way partitioning for the hw blocks. - * - * Returns The mask specifying the reserved way. 0 bits in mask indicates - * the cache 'ways' that a core can evict from. - * -1 on error - */ -int cvmx_l2c_get_hw_way_partition(void); - -/** - * Partitions the L2 cache for the hardware blocks. - * - * @mask: The partitioning of the ways expressed as a binary mask. A 0 - * bit allows the core to evict cache lines from a way, while a - * 1 bit blocks the core from evicting any lines from that - * way. There must be at least one allowed way (0 bit) in the - * mask. - * - * If any ways are blocked for all cores and the HW blocks, then those - * ways will never have any cache lines evicted from them. All cores - * and the hardware blocks are free to read from all ways regardless - * of the partitioning. - */ -int cvmx_l2c_set_hw_way_partition(uint32_t mask); - -/** - * Locks a line in the L2 cache at the specified physical address - * - * @addr: physical address of line to lock - * - * Returns 0 on success, - * 1 if line not locked. - */ -int cvmx_l2c_lock_line(uint64_t addr); - -/** - * Locks a specified memory region in the L2 cache. - * - * Note that if not all lines can be locked, that means that all - * but one of the ways (associations) available to the locking - * core are locked. Having only 1 association available for - * normal caching may have a significant adverse affect on performance. - * Care should be taken to ensure that enough of the L2 cache is left - * unlocked to allow for normal caching of DRAM. - * - * @start: Physical address of the start of the region to lock - * @len: Length (in bytes) of region to lock - * - * Returns Number of requested lines that where not locked. - * 0 on success (all locked) - */ -int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); - -/** - * Unlock and flush a cache line from the L2 cache. - * IMPORTANT: Must only be run by one core at a time due to use - * of L2C debug features. - * Note that this function will flush a matching but unlocked cache line. - * (If address is not in L2, no lines are flushed.) - * - * @address: Physical address to unlock - * - * Returns 0: line not unlocked - * 1: line unlocked - */ -int cvmx_l2c_unlock_line(uint64_t address); - -/** - * Unlocks a region of memory that is locked in the L2 cache - * - * @start: start physical address - * @len: length (in bytes) to unlock - * - * Returns Number of locked lines that the call unlocked - */ -int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); - -/** - * Read the L2 controller tag for a given location in L2 - * - * @association: - * Which association to read line from - * @index: Which way to read from. - * - * Returns l2c tag structure for line requested. - */ -union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); - -/* Wrapper around deprecated old function name */ -static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, - uint32_t index) -{ - return cvmx_l2c_get_tag(association, index); -} - -/** - * Returns the cache index for a given physical address - * - * @addr: physical address - * - * Returns L2 cache index - */ -uint32_t cvmx_l2c_address_to_index(uint64_t addr); - -/** - * Flushes (and unlocks) the entire L2 cache. - * IMPORTANT: Must only be run by one core at a time due to use - * of L2C debug features. - */ -void cvmx_l2c_flush(void); - -/** - * - * Returns Returns the size of the L2 cache in bytes, - * -1 on error (unrecognized model) - */ -int cvmx_l2c_get_cache_size_bytes(void); - -/** - * Return the number of sets in the L2 Cache - * - * Returns - */ -int cvmx_l2c_get_num_sets(void); - -/** - * Return log base 2 of the number of sets in the L2 cache - * Returns - */ -int cvmx_l2c_get_set_bits(void); -/** - * Return the number of associations in the L2 Cache - * - * Returns - */ -int cvmx_l2c_get_num_assoc(void); - -/** - * Flush a line from the L2 cache - * This should only be called from one core at a time, as this routine - * sets the core to the 'debug' core in order to flush the line. - * - * @assoc: Association (or way) to flush - * @index: Index to flush - */ -void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); - -#endif /* __CVMX_L2C_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h deleted file mode 100644 index d7102d455e1b..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2d-defs.h +++ /dev/null @@ -1,369 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_L2D_DEFS_H__ -#define __CVMX_L2D_DEFS_H__ - -#define CVMX_L2D_BST0 \ - CVMX_ADD_IO_SEG(0x0001180080000780ull) -#define CVMX_L2D_BST1 \ - CVMX_ADD_IO_SEG(0x0001180080000788ull) -#define CVMX_L2D_BST2 \ - CVMX_ADD_IO_SEG(0x0001180080000790ull) -#define CVMX_L2D_BST3 \ - CVMX_ADD_IO_SEG(0x0001180080000798ull) -#define CVMX_L2D_ERR \ - CVMX_ADD_IO_SEG(0x0001180080000010ull) -#define CVMX_L2D_FADR \ - CVMX_ADD_IO_SEG(0x0001180080000018ull) -#define CVMX_L2D_FSYN0 \ - CVMX_ADD_IO_SEG(0x0001180080000020ull) -#define CVMX_L2D_FSYN1 \ - CVMX_ADD_IO_SEG(0x0001180080000028ull) -#define CVMX_L2D_FUS0 \ - CVMX_ADD_IO_SEG(0x00011800800007A0ull) -#define CVMX_L2D_FUS1 \ - CVMX_ADD_IO_SEG(0x00011800800007A8ull) -#define CVMX_L2D_FUS2 \ - CVMX_ADD_IO_SEG(0x00011800800007B0ull) -#define CVMX_L2D_FUS3 \ - CVMX_ADD_IO_SEG(0x00011800800007B8ull) - -union cvmx_l2d_bst0 { - uint64_t u64; - struct cvmx_l2d_bst0_s { - uint64_t reserved_35_63:29; - uint64_t ftl:1; - uint64_t q0stat:34; - } s; - struct cvmx_l2d_bst0_s cn30xx; - struct cvmx_l2d_bst0_s cn31xx; - struct cvmx_l2d_bst0_s cn38xx; - struct cvmx_l2d_bst0_s cn38xxp2; - struct cvmx_l2d_bst0_s cn50xx; - struct cvmx_l2d_bst0_s cn52xx; - struct cvmx_l2d_bst0_s cn52xxp1; - struct cvmx_l2d_bst0_s cn56xx; - struct cvmx_l2d_bst0_s cn56xxp1; - struct cvmx_l2d_bst0_s cn58xx; - struct cvmx_l2d_bst0_s cn58xxp1; -}; - -union cvmx_l2d_bst1 { - uint64_t u64; - struct cvmx_l2d_bst1_s { - uint64_t reserved_34_63:30; - uint64_t q1stat:34; - } s; - struct cvmx_l2d_bst1_s cn30xx; - struct cvmx_l2d_bst1_s cn31xx; - struct cvmx_l2d_bst1_s cn38xx; - struct cvmx_l2d_bst1_s cn38xxp2; - struct cvmx_l2d_bst1_s cn50xx; - struct cvmx_l2d_bst1_s cn52xx; - struct cvmx_l2d_bst1_s cn52xxp1; - struct cvmx_l2d_bst1_s cn56xx; - struct cvmx_l2d_bst1_s cn56xxp1; - struct cvmx_l2d_bst1_s cn58xx; - struct cvmx_l2d_bst1_s cn58xxp1; -}; - -union cvmx_l2d_bst2 { - uint64_t u64; - struct cvmx_l2d_bst2_s { - uint64_t reserved_34_63:30; - uint64_t q2stat:34; - } s; - struct cvmx_l2d_bst2_s cn30xx; - struct cvmx_l2d_bst2_s cn31xx; - struct cvmx_l2d_bst2_s cn38xx; - struct cvmx_l2d_bst2_s cn38xxp2; - struct cvmx_l2d_bst2_s cn50xx; - struct cvmx_l2d_bst2_s cn52xx; - struct cvmx_l2d_bst2_s cn52xxp1; - struct cvmx_l2d_bst2_s cn56xx; - struct cvmx_l2d_bst2_s cn56xxp1; - struct cvmx_l2d_bst2_s cn58xx; - struct cvmx_l2d_bst2_s cn58xxp1; -}; - -union cvmx_l2d_bst3 { - uint64_t u64; - struct cvmx_l2d_bst3_s { - uint64_t reserved_34_63:30; - uint64_t q3stat:34; - } s; - struct cvmx_l2d_bst3_s cn30xx; - struct cvmx_l2d_bst3_s cn31xx; - struct cvmx_l2d_bst3_s cn38xx; - struct cvmx_l2d_bst3_s cn38xxp2; - struct cvmx_l2d_bst3_s cn50xx; - struct cvmx_l2d_bst3_s cn52xx; - struct cvmx_l2d_bst3_s cn52xxp1; - struct cvmx_l2d_bst3_s cn56xx; - struct cvmx_l2d_bst3_s cn56xxp1; - struct cvmx_l2d_bst3_s cn58xx; - struct cvmx_l2d_bst3_s cn58xxp1; -}; - -union cvmx_l2d_err { - uint64_t u64; - struct cvmx_l2d_err_s { - uint64_t reserved_6_63:58; - uint64_t bmhclsel:1; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } s; - struct cvmx_l2d_err_s cn30xx; - struct cvmx_l2d_err_s cn31xx; - struct cvmx_l2d_err_s cn38xx; - struct cvmx_l2d_err_s cn38xxp2; - struct cvmx_l2d_err_s cn50xx; - struct cvmx_l2d_err_s cn52xx; - struct cvmx_l2d_err_s cn52xxp1; - struct cvmx_l2d_err_s cn56xx; - struct cvmx_l2d_err_s cn56xxp1; - struct cvmx_l2d_err_s cn58xx; - struct cvmx_l2d_err_s cn58xxp1; -}; - -union cvmx_l2d_fadr { - uint64_t u64; - struct cvmx_l2d_fadr_s { - uint64_t reserved_19_63:45; - uint64_t fadru:1; - uint64_t fowmsk:4; - uint64_t fset:3; - uint64_t fadr:11; - } s; - struct cvmx_l2d_fadr_cn30xx { - uint64_t reserved_18_63:46; - uint64_t fowmsk:4; - uint64_t reserved_13_13:1; - uint64_t fset:2; - uint64_t reserved_9_10:2; - uint64_t fadr:9; - } cn30xx; - struct cvmx_l2d_fadr_cn31xx { - uint64_t reserved_18_63:46; - uint64_t fowmsk:4; - uint64_t reserved_13_13:1; - uint64_t fset:2; - uint64_t reserved_10_10:1; - uint64_t fadr:10; - } cn31xx; - struct cvmx_l2d_fadr_cn38xx { - uint64_t reserved_18_63:46; - uint64_t fowmsk:4; - uint64_t fset:3; - uint64_t fadr:11; - } cn38xx; - struct cvmx_l2d_fadr_cn38xx cn38xxp2; - struct cvmx_l2d_fadr_cn50xx { - uint64_t reserved_18_63:46; - uint64_t fowmsk:4; - uint64_t fset:3; - uint64_t reserved_8_10:3; - uint64_t fadr:8; - } cn50xx; - struct cvmx_l2d_fadr_cn52xx { - uint64_t reserved_18_63:46; - uint64_t fowmsk:4; - uint64_t fset:3; - uint64_t reserved_10_10:1; - uint64_t fadr:10; - } cn52xx; - struct cvmx_l2d_fadr_cn52xx cn52xxp1; - struct cvmx_l2d_fadr_s cn56xx; - struct cvmx_l2d_fadr_s cn56xxp1; - struct cvmx_l2d_fadr_s cn58xx; - struct cvmx_l2d_fadr_s cn58xxp1; -}; - -union cvmx_l2d_fsyn0 { - uint64_t u64; - struct cvmx_l2d_fsyn0_s { - uint64_t reserved_20_63:44; - uint64_t fsyn_ow1:10; - uint64_t fsyn_ow0:10; - } s; - struct cvmx_l2d_fsyn0_s cn30xx; - struct cvmx_l2d_fsyn0_s cn31xx; - struct cvmx_l2d_fsyn0_s cn38xx; - struct cvmx_l2d_fsyn0_s cn38xxp2; - struct cvmx_l2d_fsyn0_s cn50xx; - struct cvmx_l2d_fsyn0_s cn52xx; - struct cvmx_l2d_fsyn0_s cn52xxp1; - struct cvmx_l2d_fsyn0_s cn56xx; - struct cvmx_l2d_fsyn0_s cn56xxp1; - struct cvmx_l2d_fsyn0_s cn58xx; - struct cvmx_l2d_fsyn0_s cn58xxp1; -}; - -union cvmx_l2d_fsyn1 { - uint64_t u64; - struct cvmx_l2d_fsyn1_s { - uint64_t reserved_20_63:44; - uint64_t fsyn_ow3:10; - uint64_t fsyn_ow2:10; - } s; - struct cvmx_l2d_fsyn1_s cn30xx; - struct cvmx_l2d_fsyn1_s cn31xx; - struct cvmx_l2d_fsyn1_s cn38xx; - struct cvmx_l2d_fsyn1_s cn38xxp2; - struct cvmx_l2d_fsyn1_s cn50xx; - struct cvmx_l2d_fsyn1_s cn52xx; - struct cvmx_l2d_fsyn1_s cn52xxp1; - struct cvmx_l2d_fsyn1_s cn56xx; - struct cvmx_l2d_fsyn1_s cn56xxp1; - struct cvmx_l2d_fsyn1_s cn58xx; - struct cvmx_l2d_fsyn1_s cn58xxp1; -}; - -union cvmx_l2d_fus0 { - uint64_t u64; - struct cvmx_l2d_fus0_s { - uint64_t reserved_34_63:30; - uint64_t q0fus:34; - } s; - struct cvmx_l2d_fus0_s cn30xx; - struct cvmx_l2d_fus0_s cn31xx; - struct cvmx_l2d_fus0_s cn38xx; - struct cvmx_l2d_fus0_s cn38xxp2; - struct cvmx_l2d_fus0_s cn50xx; - struct cvmx_l2d_fus0_s cn52xx; - struct cvmx_l2d_fus0_s cn52xxp1; - struct cvmx_l2d_fus0_s cn56xx; - struct cvmx_l2d_fus0_s cn56xxp1; - struct cvmx_l2d_fus0_s cn58xx; - struct cvmx_l2d_fus0_s cn58xxp1; -}; - -union cvmx_l2d_fus1 { - uint64_t u64; - struct cvmx_l2d_fus1_s { - uint64_t reserved_34_63:30; - uint64_t q1fus:34; - } s; - struct cvmx_l2d_fus1_s cn30xx; - struct cvmx_l2d_fus1_s cn31xx; - struct cvmx_l2d_fus1_s cn38xx; - struct cvmx_l2d_fus1_s cn38xxp2; - struct cvmx_l2d_fus1_s cn50xx; - struct cvmx_l2d_fus1_s cn52xx; - struct cvmx_l2d_fus1_s cn52xxp1; - struct cvmx_l2d_fus1_s cn56xx; - struct cvmx_l2d_fus1_s cn56xxp1; - struct cvmx_l2d_fus1_s cn58xx; - struct cvmx_l2d_fus1_s cn58xxp1; -}; - -union cvmx_l2d_fus2 { - uint64_t u64; - struct cvmx_l2d_fus2_s { - uint64_t reserved_34_63:30; - uint64_t q2fus:34; - } s; - struct cvmx_l2d_fus2_s cn30xx; - struct cvmx_l2d_fus2_s cn31xx; - struct cvmx_l2d_fus2_s cn38xx; - struct cvmx_l2d_fus2_s cn38xxp2; - struct cvmx_l2d_fus2_s cn50xx; - struct cvmx_l2d_fus2_s cn52xx; - struct cvmx_l2d_fus2_s cn52xxp1; - struct cvmx_l2d_fus2_s cn56xx; - struct cvmx_l2d_fus2_s cn56xxp1; - struct cvmx_l2d_fus2_s cn58xx; - struct cvmx_l2d_fus2_s cn58xxp1; -}; - -union cvmx_l2d_fus3 { - uint64_t u64; - struct cvmx_l2d_fus3_s { - uint64_t reserved_40_63:24; - uint64_t ema_ctl:3; - uint64_t reserved_34_36:3; - uint64_t q3fus:34; - } s; - struct cvmx_l2d_fus3_cn30xx { - uint64_t reserved_35_63:29; - uint64_t crip_64k:1; - uint64_t q3fus:34; - } cn30xx; - struct cvmx_l2d_fus3_cn31xx { - uint64_t reserved_35_63:29; - uint64_t crip_128k:1; - uint64_t q3fus:34; - } cn31xx; - struct cvmx_l2d_fus3_cn38xx { - uint64_t reserved_36_63:28; - uint64_t crip_256k:1; - uint64_t crip_512k:1; - uint64_t q3fus:34; - } cn38xx; - struct cvmx_l2d_fus3_cn38xx cn38xxp2; - struct cvmx_l2d_fus3_cn50xx { - uint64_t reserved_40_63:24; - uint64_t ema_ctl:3; - uint64_t reserved_36_36:1; - uint64_t crip_32k:1; - uint64_t crip_64k:1; - uint64_t q3fus:34; - } cn50xx; - struct cvmx_l2d_fus3_cn52xx { - uint64_t reserved_40_63:24; - uint64_t ema_ctl:3; - uint64_t reserved_36_36:1; - uint64_t crip_128k:1; - uint64_t crip_256k:1; - uint64_t q3fus:34; - } cn52xx; - struct cvmx_l2d_fus3_cn52xx cn52xxp1; - struct cvmx_l2d_fus3_cn56xx { - uint64_t reserved_40_63:24; - uint64_t ema_ctl:3; - uint64_t reserved_36_36:1; - uint64_t crip_512k:1; - uint64_t crip_1024k:1; - uint64_t q3fus:34; - } cn56xx; - struct cvmx_l2d_fus3_cn56xx cn56xxp1; - struct cvmx_l2d_fus3_cn58xx { - uint64_t reserved_39_63:25; - uint64_t ema_ctl:2; - uint64_t reserved_36_36:1; - uint64_t crip_512k:1; - uint64_t crip_1024k:1; - uint64_t q3fus:34; - } cn58xx; - struct cvmx_l2d_fus3_cn58xx cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h deleted file mode 100644 index 2639a3f5ffc2..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ /dev/null @@ -1,141 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_L2T_DEFS_H__ -#define __CVMX_L2T_DEFS_H__ - -#define CVMX_L2T_ERR \ - CVMX_ADD_IO_SEG(0x0001180080000008ull) - -union cvmx_l2t_err { - uint64_t u64; - struct cvmx_l2t_err_s { - uint64_t reserved_29_63:35; - uint64_t fadru:1; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t fset:3; - uint64_t fadr:10; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } s; - struct cvmx_l2t_err_cn30xx { - uint64_t reserved_28_63:36; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t reserved_23_23:1; - uint64_t fset:2; - uint64_t reserved_19_20:2; - uint64_t fadr:8; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } cn30xx; - struct cvmx_l2t_err_cn31xx { - uint64_t reserved_28_63:36; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t reserved_23_23:1; - uint64_t fset:2; - uint64_t reserved_20_20:1; - uint64_t fadr:9; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } cn31xx; - struct cvmx_l2t_err_cn38xx { - uint64_t reserved_28_63:36; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t fset:3; - uint64_t fadr:10; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } cn38xx; - struct cvmx_l2t_err_cn38xx cn38xxp2; - struct cvmx_l2t_err_cn50xx { - uint64_t reserved_28_63:36; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t fset:3; - uint64_t reserved_18_20:3; - uint64_t fadr:7; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } cn50xx; - struct cvmx_l2t_err_cn52xx { - uint64_t reserved_28_63:36; - uint64_t lck_intena2:1; - uint64_t lckerr2:1; - uint64_t lck_intena:1; - uint64_t lckerr:1; - uint64_t fset:3; - uint64_t reserved_20_20:1; - uint64_t fadr:9; - uint64_t fsyn:6; - uint64_t ded_err:1; - uint64_t sec_err:1; - uint64_t ded_intena:1; - uint64_t sec_intena:1; - uint64_t ecc_ena:1; - } cn52xx; - struct cvmx_l2t_err_cn52xx cn52xxp1; - struct cvmx_l2t_err_s cn56xx; - struct cvmx_l2t_err_s cn56xxp1; - struct cvmx_l2t_err_s cn58xx; - struct cvmx_l2t_err_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h deleted file mode 100644 index 16f174a4dadf..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-led-defs.h +++ /dev/null @@ -1,240 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_LED_DEFS_H__ -#define __CVMX_LED_DEFS_H__ - -#define CVMX_LED_BLINK \ - CVMX_ADD_IO_SEG(0x0001180000001A48ull) -#define CVMX_LED_CLK_PHASE \ - CVMX_ADD_IO_SEG(0x0001180000001A08ull) -#define CVMX_LED_CYLON \ - CVMX_ADD_IO_SEG(0x0001180000001AF8ull) -#define CVMX_LED_DBG \ - CVMX_ADD_IO_SEG(0x0001180000001A18ull) -#define CVMX_LED_EN \ - CVMX_ADD_IO_SEG(0x0001180000001A00ull) -#define CVMX_LED_POLARITY \ - CVMX_ADD_IO_SEG(0x0001180000001A50ull) -#define CVMX_LED_PRT \ - CVMX_ADD_IO_SEG(0x0001180000001A10ull) -#define CVMX_LED_PRT_FMT \ - CVMX_ADD_IO_SEG(0x0001180000001A30ull) -#define CVMX_LED_PRT_STATUSX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8)) -#define CVMX_LED_UDD_CNTX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8)) -#define CVMX_LED_UDD_DATX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8)) -#define CVMX_LED_UDD_DAT_CLRX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16)) -#define CVMX_LED_UDD_DAT_SETX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16)) - -union cvmx_led_blink { - uint64_t u64; - struct cvmx_led_blink_s { - uint64_t reserved_8_63:56; - uint64_t rate:8; - } s; - struct cvmx_led_blink_s cn38xx; - struct cvmx_led_blink_s cn38xxp2; - struct cvmx_led_blink_s cn56xx; - struct cvmx_led_blink_s cn56xxp1; - struct cvmx_led_blink_s cn58xx; - struct cvmx_led_blink_s cn58xxp1; -}; - -union cvmx_led_clk_phase { - uint64_t u64; - struct cvmx_led_clk_phase_s { - uint64_t reserved_7_63:57; - uint64_t phase:7; - } s; - struct cvmx_led_clk_phase_s cn38xx; - struct cvmx_led_clk_phase_s cn38xxp2; - struct cvmx_led_clk_phase_s cn56xx; - struct cvmx_led_clk_phase_s cn56xxp1; - struct cvmx_led_clk_phase_s cn58xx; - struct cvmx_led_clk_phase_s cn58xxp1; -}; - -union cvmx_led_cylon { - uint64_t u64; - struct cvmx_led_cylon_s { - uint64_t reserved_16_63:48; - uint64_t rate:16; - } s; - struct cvmx_led_cylon_s cn38xx; - struct cvmx_led_cylon_s cn38xxp2; - struct cvmx_led_cylon_s cn56xx; - struct cvmx_led_cylon_s cn56xxp1; - struct cvmx_led_cylon_s cn58xx; - struct cvmx_led_cylon_s cn58xxp1; -}; - -union cvmx_led_dbg { - uint64_t u64; - struct cvmx_led_dbg_s { - uint64_t reserved_1_63:63; - uint64_t dbg_en:1; - } s; - struct cvmx_led_dbg_s cn38xx; - struct cvmx_led_dbg_s cn38xxp2; - struct cvmx_led_dbg_s cn56xx; - struct cvmx_led_dbg_s cn56xxp1; - struct cvmx_led_dbg_s cn58xx; - struct cvmx_led_dbg_s cn58xxp1; -}; - -union cvmx_led_en { - uint64_t u64; - struct cvmx_led_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_led_en_s cn38xx; - struct cvmx_led_en_s cn38xxp2; - struct cvmx_led_en_s cn56xx; - struct cvmx_led_en_s cn56xxp1; - struct cvmx_led_en_s cn58xx; - struct cvmx_led_en_s cn58xxp1; -}; - -union cvmx_led_polarity { - uint64_t u64; - struct cvmx_led_polarity_s { - uint64_t reserved_1_63:63; - uint64_t polarity:1; - } s; - struct cvmx_led_polarity_s cn38xx; - struct cvmx_led_polarity_s cn38xxp2; - struct cvmx_led_polarity_s cn56xx; - struct cvmx_led_polarity_s cn56xxp1; - struct cvmx_led_polarity_s cn58xx; - struct cvmx_led_polarity_s cn58xxp1; -}; - -union cvmx_led_prt { - uint64_t u64; - struct cvmx_led_prt_s { - uint64_t reserved_8_63:56; - uint64_t prt_en:8; - } s; - struct cvmx_led_prt_s cn38xx; - struct cvmx_led_prt_s cn38xxp2; - struct cvmx_led_prt_s cn56xx; - struct cvmx_led_prt_s cn56xxp1; - struct cvmx_led_prt_s cn58xx; - struct cvmx_led_prt_s cn58xxp1; -}; - -union cvmx_led_prt_fmt { - uint64_t u64; - struct cvmx_led_prt_fmt_s { - uint64_t reserved_4_63:60; - uint64_t format:4; - } s; - struct cvmx_led_prt_fmt_s cn38xx; - struct cvmx_led_prt_fmt_s cn38xxp2; - struct cvmx_led_prt_fmt_s cn56xx; - struct cvmx_led_prt_fmt_s cn56xxp1; - struct cvmx_led_prt_fmt_s cn58xx; - struct cvmx_led_prt_fmt_s cn58xxp1; -}; - -union cvmx_led_prt_statusx { - uint64_t u64; - struct cvmx_led_prt_statusx_s { - uint64_t reserved_6_63:58; - uint64_t status:6; - } s; - struct cvmx_led_prt_statusx_s cn38xx; - struct cvmx_led_prt_statusx_s cn38xxp2; - struct cvmx_led_prt_statusx_s cn56xx; - struct cvmx_led_prt_statusx_s cn56xxp1; - struct cvmx_led_prt_statusx_s cn58xx; - struct cvmx_led_prt_statusx_s cn58xxp1; -}; - -union cvmx_led_udd_cntx { - uint64_t u64; - struct cvmx_led_udd_cntx_s { - uint64_t reserved_6_63:58; - uint64_t cnt:6; - } s; - struct cvmx_led_udd_cntx_s cn38xx; - struct cvmx_led_udd_cntx_s cn38xxp2; - struct cvmx_led_udd_cntx_s cn56xx; - struct cvmx_led_udd_cntx_s cn56xxp1; - struct cvmx_led_udd_cntx_s cn58xx; - struct cvmx_led_udd_cntx_s cn58xxp1; -}; - -union cvmx_led_udd_datx { - uint64_t u64; - struct cvmx_led_udd_datx_s { - uint64_t reserved_32_63:32; - uint64_t dat:32; - } s; - struct cvmx_led_udd_datx_s cn38xx; - struct cvmx_led_udd_datx_s cn38xxp2; - struct cvmx_led_udd_datx_s cn56xx; - struct cvmx_led_udd_datx_s cn56xxp1; - struct cvmx_led_udd_datx_s cn58xx; - struct cvmx_led_udd_datx_s cn58xxp1; -}; - -union cvmx_led_udd_dat_clrx { - uint64_t u64; - struct cvmx_led_udd_dat_clrx_s { - uint64_t reserved_32_63:32; - uint64_t clr:32; - } s; - struct cvmx_led_udd_dat_clrx_s cn38xx; - struct cvmx_led_udd_dat_clrx_s cn38xxp2; - struct cvmx_led_udd_dat_clrx_s cn56xx; - struct cvmx_led_udd_dat_clrx_s cn56xxp1; - struct cvmx_led_udd_dat_clrx_s cn58xx; - struct cvmx_led_udd_dat_clrx_s cn58xxp1; -}; - -union cvmx_led_udd_dat_setx { - uint64_t u64; - struct cvmx_led_udd_dat_setx_s { - uint64_t reserved_32_63:32; - uint64_t set:32; - } s; - struct cvmx_led_udd_dat_setx_s cn38xx; - struct cvmx_led_udd_dat_setx_s cn38xxp2; - struct cvmx_led_udd_dat_setx_s cn56xx; - struct cvmx_led_udd_dat_setx_s cn56xxp1; - struct cvmx_led_udd_dat_setx_s cn58xx; - struct cvmx_led_udd_dat_setx_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h deleted file mode 100644 index 6555f0530988..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-mio-defs.h +++ /dev/null @@ -1,2004 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_MIO_DEFS_H__ -#define __CVMX_MIO_DEFS_H__ - -#define CVMX_MIO_BOOT_BIST_STAT \ - CVMX_ADD_IO_SEG(0x00011800000000F8ull) -#define CVMX_MIO_BOOT_COMP \ - CVMX_ADD_IO_SEG(0x00011800000000B8ull) -#define CVMX_MIO_BOOT_DMA_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8)) -#define CVMX_MIO_BOOT_DMA_INTX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8)) -#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8)) -#define CVMX_MIO_BOOT_DMA_TIMX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8)) -#define CVMX_MIO_BOOT_ERR \ - CVMX_ADD_IO_SEG(0x00011800000000A0ull) -#define CVMX_MIO_BOOT_INT \ - CVMX_ADD_IO_SEG(0x00011800000000A8ull) -#define CVMX_MIO_BOOT_LOC_ADR \ - CVMX_ADD_IO_SEG(0x0001180000000090ull) -#define CVMX_MIO_BOOT_LOC_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8)) -#define CVMX_MIO_BOOT_LOC_DAT \ - CVMX_ADD_IO_SEG(0x0001180000000098ull) -#define CVMX_MIO_BOOT_PIN_DEFS \ - CVMX_ADD_IO_SEG(0x00011800000000C0ull) -#define CVMX_MIO_BOOT_REG_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8)) -#define CVMX_MIO_BOOT_REG_TIMX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8)) -#define CVMX_MIO_BOOT_THR \ - CVMX_ADD_IO_SEG(0x00011800000000B0ull) -#define CVMX_MIO_FUS_BNK_DATX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8)) -#define CVMX_MIO_FUS_DAT0 \ - CVMX_ADD_IO_SEG(0x0001180000001400ull) -#define CVMX_MIO_FUS_DAT1 \ - CVMX_ADD_IO_SEG(0x0001180000001408ull) -#define CVMX_MIO_FUS_DAT2 \ - CVMX_ADD_IO_SEG(0x0001180000001410ull) -#define CVMX_MIO_FUS_DAT3 \ - CVMX_ADD_IO_SEG(0x0001180000001418ull) -#define CVMX_MIO_FUS_EMA \ - CVMX_ADD_IO_SEG(0x0001180000001550ull) -#define CVMX_MIO_FUS_PDF \ - CVMX_ADD_IO_SEG(0x0001180000001420ull) -#define CVMX_MIO_FUS_PLL \ - CVMX_ADD_IO_SEG(0x0001180000001580ull) -#define CVMX_MIO_FUS_PROG \ - CVMX_ADD_IO_SEG(0x0001180000001510ull) -#define CVMX_MIO_FUS_PROG_TIMES \ - CVMX_ADD_IO_SEG(0x0001180000001518ull) -#define CVMX_MIO_FUS_RCMD \ - CVMX_ADD_IO_SEG(0x0001180000001500ull) -#define CVMX_MIO_FUS_SPR_REPAIR_RES \ - CVMX_ADD_IO_SEG(0x0001180000001548ull) -#define CVMX_MIO_FUS_SPR_REPAIR_SUM \ - CVMX_ADD_IO_SEG(0x0001180000001540ull) -#define CVMX_MIO_FUS_UNLOCK \ - CVMX_ADD_IO_SEG(0x0001180000001578ull) -#define CVMX_MIO_FUS_WADR \ - CVMX_ADD_IO_SEG(0x0001180000001508ull) -#define CVMX_MIO_NDF_DMA_CFG \ - CVMX_ADD_IO_SEG(0x0001180000000168ull) -#define CVMX_MIO_NDF_DMA_INT \ - CVMX_ADD_IO_SEG(0x0001180000000170ull) -#define CVMX_MIO_NDF_DMA_INT_EN \ - CVMX_ADD_IO_SEG(0x0001180000000178ull) -#define CVMX_MIO_PLL_CTL \ - CVMX_ADD_IO_SEG(0x0001180000001448ull) -#define CVMX_MIO_PLL_SETTING \ - CVMX_ADD_IO_SEG(0x0001180000001440ull) -#define CVMX_MIO_TWSX_INT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512)) -#define CVMX_MIO_TWSX_SW_TWSI(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512)) -#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512)) -#define CVMX_MIO_TWSX_TWSI_SW(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512)) -#define CVMX_MIO_UART2_DLH \ - CVMX_ADD_IO_SEG(0x0001180000000488ull) -#define CVMX_MIO_UART2_DLL \ - CVMX_ADD_IO_SEG(0x0001180000000480ull) -#define CVMX_MIO_UART2_FAR \ - CVMX_ADD_IO_SEG(0x0001180000000520ull) -#define CVMX_MIO_UART2_FCR \ - CVMX_ADD_IO_SEG(0x0001180000000450ull) -#define CVMX_MIO_UART2_HTX \ - CVMX_ADD_IO_SEG(0x0001180000000708ull) -#define CVMX_MIO_UART2_IER \ - CVMX_ADD_IO_SEG(0x0001180000000408ull) -#define CVMX_MIO_UART2_IIR \ - CVMX_ADD_IO_SEG(0x0001180000000410ull) -#define CVMX_MIO_UART2_LCR \ - CVMX_ADD_IO_SEG(0x0001180000000418ull) -#define CVMX_MIO_UART2_LSR \ - CVMX_ADD_IO_SEG(0x0001180000000428ull) -#define CVMX_MIO_UART2_MCR \ - CVMX_ADD_IO_SEG(0x0001180000000420ull) -#define CVMX_MIO_UART2_MSR \ - CVMX_ADD_IO_SEG(0x0001180000000430ull) -#define CVMX_MIO_UART2_RBR \ - CVMX_ADD_IO_SEG(0x0001180000000400ull) -#define CVMX_MIO_UART2_RFL \ - CVMX_ADD_IO_SEG(0x0001180000000608ull) -#define CVMX_MIO_UART2_RFW \ - CVMX_ADD_IO_SEG(0x0001180000000530ull) -#define CVMX_MIO_UART2_SBCR \ - CVMX_ADD_IO_SEG(0x0001180000000620ull) -#define CVMX_MIO_UART2_SCR \ - CVMX_ADD_IO_SEG(0x0001180000000438ull) -#define CVMX_MIO_UART2_SFE \ - CVMX_ADD_IO_SEG(0x0001180000000630ull) -#define CVMX_MIO_UART2_SRR \ - CVMX_ADD_IO_SEG(0x0001180000000610ull) -#define CVMX_MIO_UART2_SRT \ - CVMX_ADD_IO_SEG(0x0001180000000638ull) -#define CVMX_MIO_UART2_SRTS \ - CVMX_ADD_IO_SEG(0x0001180000000618ull) -#define CVMX_MIO_UART2_STT \ - CVMX_ADD_IO_SEG(0x0001180000000700ull) -#define CVMX_MIO_UART2_TFL \ - CVMX_ADD_IO_SEG(0x0001180000000600ull) -#define CVMX_MIO_UART2_TFR \ - CVMX_ADD_IO_SEG(0x0001180000000528ull) -#define CVMX_MIO_UART2_THR \ - CVMX_ADD_IO_SEG(0x0001180000000440ull) -#define CVMX_MIO_UART2_USR \ - CVMX_ADD_IO_SEG(0x0001180000000538ull) -#define CVMX_MIO_UARTX_DLH(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_DLL(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_FAR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_FCR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_HTX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_IER(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_IIR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_LCR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_LSR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_MCR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_MSR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_RBR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_RFL(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_RFW(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SBCR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SCR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SFE(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SRR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SRT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_SRTS(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_STT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_TFL(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_TFR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_THR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024)) -#define CVMX_MIO_UARTX_USR(offset) \ - CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024)) - -union cvmx_mio_boot_bist_stat { - uint64_t u64; - struct cvmx_mio_boot_bist_stat_s { - uint64_t reserved_2_63:62; - uint64_t loc:1; - uint64_t ncbi:1; - } s; - struct cvmx_mio_boot_bist_stat_cn30xx { - uint64_t reserved_4_63:60; - uint64_t ncbo_1:1; - uint64_t ncbo_0:1; - uint64_t loc:1; - uint64_t ncbi:1; - } cn30xx; - struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; - struct cvmx_mio_boot_bist_stat_cn38xx { - uint64_t reserved_3_63:61; - uint64_t ncbo_0:1; - uint64_t loc:1; - uint64_t ncbi:1; - } cn38xx; - struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; - struct cvmx_mio_boot_bist_stat_cn50xx { - uint64_t reserved_6_63:58; - uint64_t pcm_1:1; - uint64_t pcm_0:1; - uint64_t ncbo_1:1; - uint64_t ncbo_0:1; - uint64_t loc:1; - uint64_t ncbi:1; - } cn50xx; - struct cvmx_mio_boot_bist_stat_cn52xx { - uint64_t reserved_6_63:58; - uint64_t ndf:2; - uint64_t ncbo_0:1; - uint64_t dma:1; - uint64_t loc:1; - uint64_t ncbi:1; - } cn52xx; - struct cvmx_mio_boot_bist_stat_cn52xxp1 { - uint64_t reserved_4_63:60; - uint64_t ncbo_0:1; - uint64_t dma:1; - uint64_t loc:1; - uint64_t ncbi:1; - } cn52xxp1; - struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; - struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; - struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; - struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; -}; - -union cvmx_mio_boot_comp { - uint64_t u64; - struct cvmx_mio_boot_comp_s { - uint64_t reserved_10_63:54; - uint64_t pctl:5; - uint64_t nctl:5; - } s; - struct cvmx_mio_boot_comp_s cn50xx; - struct cvmx_mio_boot_comp_s cn52xx; - struct cvmx_mio_boot_comp_s cn52xxp1; - struct cvmx_mio_boot_comp_s cn56xx; - struct cvmx_mio_boot_comp_s cn56xxp1; -}; - -union cvmx_mio_boot_dma_cfgx { - uint64_t u64; - struct cvmx_mio_boot_dma_cfgx_s { - uint64_t en:1; - uint64_t rw:1; - uint64_t clr:1; - uint64_t reserved_60_60:1; - uint64_t swap32:1; - uint64_t swap16:1; - uint64_t swap8:1; - uint64_t endian:1; - uint64_t size:20; - uint64_t adr:36; - } s; - struct cvmx_mio_boot_dma_cfgx_s cn52xx; - struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; - struct cvmx_mio_boot_dma_cfgx_s cn56xx; - struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; -}; - -union cvmx_mio_boot_dma_intx { - uint64_t u64; - struct cvmx_mio_boot_dma_intx_s { - uint64_t reserved_2_63:62; - uint64_t dmarq:1; - uint64_t done:1; - } s; - struct cvmx_mio_boot_dma_intx_s cn52xx; - struct cvmx_mio_boot_dma_intx_s cn52xxp1; - struct cvmx_mio_boot_dma_intx_s cn56xx; - struct cvmx_mio_boot_dma_intx_s cn56xxp1; -}; - -union cvmx_mio_boot_dma_int_enx { - uint64_t u64; - struct cvmx_mio_boot_dma_int_enx_s { - uint64_t reserved_2_63:62; - uint64_t dmarq:1; - uint64_t done:1; - } s; - struct cvmx_mio_boot_dma_int_enx_s cn52xx; - struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; - struct cvmx_mio_boot_dma_int_enx_s cn56xx; - struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; -}; - -union cvmx_mio_boot_dma_timx { - uint64_t u64; - struct cvmx_mio_boot_dma_timx_s { - uint64_t dmack_pi:1; - uint64_t dmarq_pi:1; - uint64_t tim_mult:2; - uint64_t rd_dly:3; - uint64_t ddr:1; - uint64_t width:1; - uint64_t reserved_48_54:7; - uint64_t pause:6; - uint64_t dmack_h:6; - uint64_t we_n:6; - uint64_t we_a:6; - uint64_t oe_n:6; - uint64_t oe_a:6; - uint64_t dmack_s:6; - uint64_t dmarq:6; - } s; - struct cvmx_mio_boot_dma_timx_s cn52xx; - struct cvmx_mio_boot_dma_timx_s cn52xxp1; - struct cvmx_mio_boot_dma_timx_s cn56xx; - struct cvmx_mio_boot_dma_timx_s cn56xxp1; -}; - -union cvmx_mio_boot_err { - uint64_t u64; - struct cvmx_mio_boot_err_s { - uint64_t reserved_2_63:62; - uint64_t wait_err:1; - uint64_t adr_err:1; - } s; - struct cvmx_mio_boot_err_s cn30xx; - struct cvmx_mio_boot_err_s cn31xx; - struct cvmx_mio_boot_err_s cn38xx; - struct cvmx_mio_boot_err_s cn38xxp2; - struct cvmx_mio_boot_err_s cn50xx; - struct cvmx_mio_boot_err_s cn52xx; - struct cvmx_mio_boot_err_s cn52xxp1; - struct cvmx_mio_boot_err_s cn56xx; - struct cvmx_mio_boot_err_s cn56xxp1; - struct cvmx_mio_boot_err_s cn58xx; - struct cvmx_mio_boot_err_s cn58xxp1; -}; - -union cvmx_mio_boot_int { - uint64_t u64; - struct cvmx_mio_boot_int_s { - uint64_t reserved_2_63:62; - uint64_t wait_int:1; - uint64_t adr_int:1; - } s; - struct cvmx_mio_boot_int_s cn30xx; - struct cvmx_mio_boot_int_s cn31xx; - struct cvmx_mio_boot_int_s cn38xx; - struct cvmx_mio_boot_int_s cn38xxp2; - struct cvmx_mio_boot_int_s cn50xx; - struct cvmx_mio_boot_int_s cn52xx; - struct cvmx_mio_boot_int_s cn52xxp1; - struct cvmx_mio_boot_int_s cn56xx; - struct cvmx_mio_boot_int_s cn56xxp1; - struct cvmx_mio_boot_int_s cn58xx; - struct cvmx_mio_boot_int_s cn58xxp1; -}; - -union cvmx_mio_boot_loc_adr { - uint64_t u64; - struct cvmx_mio_boot_loc_adr_s { - uint64_t reserved_8_63:56; - uint64_t adr:5; - uint64_t reserved_0_2:3; - } s; - struct cvmx_mio_boot_loc_adr_s cn30xx; - struct cvmx_mio_boot_loc_adr_s cn31xx; - struct cvmx_mio_boot_loc_adr_s cn38xx; - struct cvmx_mio_boot_loc_adr_s cn38xxp2; - struct cvmx_mio_boot_loc_adr_s cn50xx; - struct cvmx_mio_boot_loc_adr_s cn52xx; - struct cvmx_mio_boot_loc_adr_s cn52xxp1; - struct cvmx_mio_boot_loc_adr_s cn56xx; - struct cvmx_mio_boot_loc_adr_s cn56xxp1; - struct cvmx_mio_boot_loc_adr_s cn58xx; - struct cvmx_mio_boot_loc_adr_s cn58xxp1; -}; - -union cvmx_mio_boot_loc_cfgx { - uint64_t u64; - struct cvmx_mio_boot_loc_cfgx_s { - uint64_t reserved_32_63:32; - uint64_t en:1; - uint64_t reserved_28_30:3; - uint64_t base:25; - uint64_t reserved_0_2:3; - } s; - struct cvmx_mio_boot_loc_cfgx_s cn30xx; - struct cvmx_mio_boot_loc_cfgx_s cn31xx; - struct cvmx_mio_boot_loc_cfgx_s cn38xx; - struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; - struct cvmx_mio_boot_loc_cfgx_s cn50xx; - struct cvmx_mio_boot_loc_cfgx_s cn52xx; - struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; - struct cvmx_mio_boot_loc_cfgx_s cn56xx; - struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; - struct cvmx_mio_boot_loc_cfgx_s cn58xx; - struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; -}; - -union cvmx_mio_boot_loc_dat { - uint64_t u64; - struct cvmx_mio_boot_loc_dat_s { - uint64_t data:64; - } s; - struct cvmx_mio_boot_loc_dat_s cn30xx; - struct cvmx_mio_boot_loc_dat_s cn31xx; - struct cvmx_mio_boot_loc_dat_s cn38xx; - struct cvmx_mio_boot_loc_dat_s cn38xxp2; - struct cvmx_mio_boot_loc_dat_s cn50xx; - struct cvmx_mio_boot_loc_dat_s cn52xx; - struct cvmx_mio_boot_loc_dat_s cn52xxp1; - struct cvmx_mio_boot_loc_dat_s cn56xx; - struct cvmx_mio_boot_loc_dat_s cn56xxp1; - struct cvmx_mio_boot_loc_dat_s cn58xx; - struct cvmx_mio_boot_loc_dat_s cn58xxp1; -}; - -union cvmx_mio_boot_pin_defs { - uint64_t u64; - struct cvmx_mio_boot_pin_defs_s { - uint64_t reserved_16_63:48; - uint64_t ale:1; - uint64_t width:1; - uint64_t dmack_p2:1; - uint64_t dmack_p1:1; - uint64_t dmack_p0:1; - uint64_t term:2; - uint64_t nand:1; - uint64_t reserved_0_7:8; - } s; - struct cvmx_mio_boot_pin_defs_cn52xx { - uint64_t reserved_16_63:48; - uint64_t ale:1; - uint64_t width:1; - uint64_t reserved_13_13:1; - uint64_t dmack_p1:1; - uint64_t dmack_p0:1; - uint64_t term:2; - uint64_t nand:1; - uint64_t reserved_0_7:8; - } cn52xx; - struct cvmx_mio_boot_pin_defs_cn56xx { - uint64_t reserved_16_63:48; - uint64_t ale:1; - uint64_t width:1; - uint64_t dmack_p2:1; - uint64_t dmack_p1:1; - uint64_t dmack_p0:1; - uint64_t term:2; - uint64_t reserved_0_8:9; - } cn56xx; -}; - -union cvmx_mio_boot_reg_cfgx { - uint64_t u64; - struct cvmx_mio_boot_reg_cfgx_s { - uint64_t reserved_44_63:20; - uint64_t dmack:2; - uint64_t tim_mult:2; - uint64_t rd_dly:3; - uint64_t sam:1; - uint64_t we_ext:2; - uint64_t oe_ext:2; - uint64_t en:1; - uint64_t orbit:1; - uint64_t ale:1; - uint64_t width:1; - uint64_t size:12; - uint64_t base:16; - } s; - struct cvmx_mio_boot_reg_cfgx_cn30xx { - uint64_t reserved_37_63:27; - uint64_t sam:1; - uint64_t we_ext:2; - uint64_t oe_ext:2; - uint64_t en:1; - uint64_t orbit:1; - uint64_t ale:1; - uint64_t width:1; - uint64_t size:12; - uint64_t base:16; - } cn30xx; - struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; - struct cvmx_mio_boot_reg_cfgx_cn38xx { - uint64_t reserved_32_63:32; - uint64_t en:1; - uint64_t orbit:1; - uint64_t reserved_28_29:2; - uint64_t size:12; - uint64_t base:16; - } cn38xx; - struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; - struct cvmx_mio_boot_reg_cfgx_cn50xx { - uint64_t reserved_42_63:22; - uint64_t tim_mult:2; - uint64_t rd_dly:3; - uint64_t sam:1; - uint64_t we_ext:2; - uint64_t oe_ext:2; - uint64_t en:1; - uint64_t orbit:1; - uint64_t ale:1; - uint64_t width:1; - uint64_t size:12; - uint64_t base:16; - } cn50xx; - struct cvmx_mio_boot_reg_cfgx_s cn52xx; - struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; - struct cvmx_mio_boot_reg_cfgx_s cn56xx; - struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; - struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; - struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; -}; - -union cvmx_mio_boot_reg_timx { - uint64_t u64; - struct cvmx_mio_boot_reg_timx_s { - uint64_t pagem:1; - uint64_t waitm:1; - uint64_t pages:2; - uint64_t ale:6; - uint64_t page:6; - uint64_t wait:6; - uint64_t pause:6; - uint64_t wr_hld:6; - uint64_t rd_hld:6; - uint64_t we:6; - uint64_t oe:6; - uint64_t ce:6; - uint64_t adr:6; - } s; - struct cvmx_mio_boot_reg_timx_s cn30xx; - struct cvmx_mio_boot_reg_timx_s cn31xx; - struct cvmx_mio_boot_reg_timx_cn38xx { - uint64_t pagem:1; - uint64_t waitm:1; - uint64_t pages:2; - uint64_t reserved_54_59:6; - uint64_t page:6; - uint64_t wait:6; - uint64_t pause:6; - uint64_t wr_hld:6; - uint64_t rd_hld:6; - uint64_t we:6; - uint64_t oe:6; - uint64_t ce:6; - uint64_t adr:6; - } cn38xx; - struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; - struct cvmx_mio_boot_reg_timx_s cn50xx; - struct cvmx_mio_boot_reg_timx_s cn52xx; - struct cvmx_mio_boot_reg_timx_s cn52xxp1; - struct cvmx_mio_boot_reg_timx_s cn56xx; - struct cvmx_mio_boot_reg_timx_s cn56xxp1; - struct cvmx_mio_boot_reg_timx_s cn58xx; - struct cvmx_mio_boot_reg_timx_s cn58xxp1; -}; - -union cvmx_mio_boot_thr { - uint64_t u64; - struct cvmx_mio_boot_thr_s { - uint64_t reserved_22_63:42; - uint64_t dma_thr:6; - uint64_t reserved_14_15:2; - uint64_t fif_cnt:6; - uint64_t reserved_6_7:2; - uint64_t fif_thr:6; - } s; - struct cvmx_mio_boot_thr_cn30xx { - uint64_t reserved_14_63:50; - uint64_t fif_cnt:6; - uint64_t reserved_6_7:2; - uint64_t fif_thr:6; - } cn30xx; - struct cvmx_mio_boot_thr_cn30xx cn31xx; - struct cvmx_mio_boot_thr_cn30xx cn38xx; - struct cvmx_mio_boot_thr_cn30xx cn38xxp2; - struct cvmx_mio_boot_thr_cn30xx cn50xx; - struct cvmx_mio_boot_thr_s cn52xx; - struct cvmx_mio_boot_thr_s cn52xxp1; - struct cvmx_mio_boot_thr_s cn56xx; - struct cvmx_mio_boot_thr_s cn56xxp1; - struct cvmx_mio_boot_thr_cn30xx cn58xx; - struct cvmx_mio_boot_thr_cn30xx cn58xxp1; -}; - -union cvmx_mio_fus_bnk_datx { - uint64_t u64; - struct cvmx_mio_fus_bnk_datx_s { - uint64_t dat:64; - } s; - struct cvmx_mio_fus_bnk_datx_s cn50xx; - struct cvmx_mio_fus_bnk_datx_s cn52xx; - struct cvmx_mio_fus_bnk_datx_s cn52xxp1; - struct cvmx_mio_fus_bnk_datx_s cn56xx; - struct cvmx_mio_fus_bnk_datx_s cn56xxp1; - struct cvmx_mio_fus_bnk_datx_s cn58xx; - struct cvmx_mio_fus_bnk_datx_s cn58xxp1; -}; - -union cvmx_mio_fus_dat0 { - uint64_t u64; - struct cvmx_mio_fus_dat0_s { - uint64_t reserved_32_63:32; - uint64_t man_info:32; - } s; - struct cvmx_mio_fus_dat0_s cn30xx; - struct cvmx_mio_fus_dat0_s cn31xx; - struct cvmx_mio_fus_dat0_s cn38xx; - struct cvmx_mio_fus_dat0_s cn38xxp2; - struct cvmx_mio_fus_dat0_s cn50xx; - struct cvmx_mio_fus_dat0_s cn52xx; - struct cvmx_mio_fus_dat0_s cn52xxp1; - struct cvmx_mio_fus_dat0_s cn56xx; - struct cvmx_mio_fus_dat0_s cn56xxp1; - struct cvmx_mio_fus_dat0_s cn58xx; - struct cvmx_mio_fus_dat0_s cn58xxp1; -}; - -union cvmx_mio_fus_dat1 { - uint64_t u64; - struct cvmx_mio_fus_dat1_s { - uint64_t reserved_32_63:32; - uint64_t man_info:32; - } s; - struct cvmx_mio_fus_dat1_s cn30xx; - struct cvmx_mio_fus_dat1_s cn31xx; - struct cvmx_mio_fus_dat1_s cn38xx; - struct cvmx_mio_fus_dat1_s cn38xxp2; - struct cvmx_mio_fus_dat1_s cn50xx; - struct cvmx_mio_fus_dat1_s cn52xx; - struct cvmx_mio_fus_dat1_s cn52xxp1; - struct cvmx_mio_fus_dat1_s cn56xx; - struct cvmx_mio_fus_dat1_s cn56xxp1; - struct cvmx_mio_fus_dat1_s cn58xx; - struct cvmx_mio_fus_dat1_s cn58xxp1; -}; - -union cvmx_mio_fus_dat2 { - uint64_t u64; - struct cvmx_mio_fus_dat2_s { - uint64_t reserved_34_63:30; - uint64_t fus318:1; - uint64_t raid_en:1; - uint64_t reserved_30_31:2; - uint64_t nokasu:1; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t reserved_0_15:16; - } s; - struct cvmx_mio_fus_dat2_cn30xx { - uint64_t reserved_29_63:35; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t pll_off:4; - uint64_t reserved_1_11:11; - uint64_t pp_dis:1; - } cn30xx; - struct cvmx_mio_fus_dat2_cn31xx { - uint64_t reserved_29_63:35; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t pll_off:4; - uint64_t reserved_2_11:10; - uint64_t pp_dis:2; - } cn31xx; - struct cvmx_mio_fus_dat2_cn38xx { - uint64_t reserved_29_63:35; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t pp_dis:16; - } cn38xx; - struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; - struct cvmx_mio_fus_dat2_cn50xx { - uint64_t reserved_34_63:30; - uint64_t fus318:1; - uint64_t raid_en:1; - uint64_t reserved_30_31:2; - uint64_t nokasu:1; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t reserved_2_15:14; - uint64_t pp_dis:2; - } cn50xx; - struct cvmx_mio_fus_dat2_cn52xx { - uint64_t reserved_34_63:30; - uint64_t fus318:1; - uint64_t raid_en:1; - uint64_t reserved_30_31:2; - uint64_t nokasu:1; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t reserved_4_15:12; - uint64_t pp_dis:4; - } cn52xx; - struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; - struct cvmx_mio_fus_dat2_cn56xx { - uint64_t reserved_34_63:30; - uint64_t fus318:1; - uint64_t raid_en:1; - uint64_t reserved_30_31:2; - uint64_t nokasu:1; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t reserved_12_15:4; - uint64_t pp_dis:12; - } cn56xx; - struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; - struct cvmx_mio_fus_dat2_cn58xx { - uint64_t reserved_30_63:34; - uint64_t nokasu:1; - uint64_t nodfa_cp2:1; - uint64_t nomul:1; - uint64_t nocrypto:1; - uint64_t rst_sht:1; - uint64_t bist_dis:1; - uint64_t chip_id:8; - uint64_t pp_dis:16; - } cn58xx; - struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; -}; - -union cvmx_mio_fus_dat3 { - uint64_t u64; - struct cvmx_mio_fus_dat3_s { - uint64_t reserved_32_63:32; - uint64_t pll_div4:1; - uint64_t zip_crip:2; - uint64_t bar2_en:1; - uint64_t efus_lck:1; - uint64_t efus_ign:1; - uint64_t nozip:1; - uint64_t nodfa_dte:1; - uint64_t icache:24; - } s; - struct cvmx_mio_fus_dat3_cn30xx { - uint64_t reserved_32_63:32; - uint64_t pll_div4:1; - uint64_t reserved_29_30:2; - uint64_t bar2_en:1; - uint64_t efus_lck:1; - uint64_t efus_ign:1; - uint64_t nozip:1; - uint64_t nodfa_dte:1; - uint64_t icache:24; - } cn30xx; - struct cvmx_mio_fus_dat3_s cn31xx; - struct cvmx_mio_fus_dat3_cn38xx { - uint64_t reserved_31_63:33; - uint64_t zip_crip:2; - uint64_t bar2_en:1; - uint64_t efus_lck:1; - uint64_t efus_ign:1; - uint64_t nozip:1; - uint64_t nodfa_dte:1; - uint64_t icache:24; - } cn38xx; - struct cvmx_mio_fus_dat3_cn38xxp2 { - uint64_t reserved_29_63:35; - uint64_t bar2_en:1; - uint64_t efus_lck:1; - uint64_t efus_ign:1; - uint64_t nozip:1; - uint64_t nodfa_dte:1; - uint64_t icache:24; - } cn38xxp2; - struct cvmx_mio_fus_dat3_cn38xx cn50xx; - struct cvmx_mio_fus_dat3_cn38xx cn52xx; - struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; - struct cvmx_mio_fus_dat3_cn38xx cn56xx; - struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; - struct cvmx_mio_fus_dat3_cn38xx cn58xx; - struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; -}; - -union cvmx_mio_fus_ema { - uint64_t u64; - struct cvmx_mio_fus_ema_s { - uint64_t reserved_7_63:57; - uint64_t eff_ema:3; - uint64_t reserved_3_3:1; - uint64_t ema:3; - } s; - struct cvmx_mio_fus_ema_s cn50xx; - struct cvmx_mio_fus_ema_s cn52xx; - struct cvmx_mio_fus_ema_s cn52xxp1; - struct cvmx_mio_fus_ema_s cn56xx; - struct cvmx_mio_fus_ema_s cn56xxp1; - struct cvmx_mio_fus_ema_cn58xx { - uint64_t reserved_2_63:62; - uint64_t ema:2; - } cn58xx; - struct cvmx_mio_fus_ema_cn58xx cn58xxp1; -}; - -union cvmx_mio_fus_pdf { - uint64_t u64; - struct cvmx_mio_fus_pdf_s { - uint64_t pdf:64; - } s; - struct cvmx_mio_fus_pdf_s cn50xx; - struct cvmx_mio_fus_pdf_s cn52xx; - struct cvmx_mio_fus_pdf_s cn52xxp1; - struct cvmx_mio_fus_pdf_s cn56xx; - struct cvmx_mio_fus_pdf_s cn56xxp1; - struct cvmx_mio_fus_pdf_s cn58xx; -}; - -union cvmx_mio_fus_pll { - uint64_t u64; - struct cvmx_mio_fus_pll_s { - uint64_t reserved_2_63:62; - uint64_t rfslip:1; - uint64_t fbslip:1; - } s; - struct cvmx_mio_fus_pll_s cn50xx; - struct cvmx_mio_fus_pll_s cn52xx; - struct cvmx_mio_fus_pll_s cn52xxp1; - struct cvmx_mio_fus_pll_s cn56xx; - struct cvmx_mio_fus_pll_s cn56xxp1; - struct cvmx_mio_fus_pll_s cn58xx; - struct cvmx_mio_fus_pll_s cn58xxp1; -}; - -union cvmx_mio_fus_prog { - uint64_t u64; - struct cvmx_mio_fus_prog_s { - uint64_t reserved_1_63:63; - uint64_t prog:1; - } s; - struct cvmx_mio_fus_prog_s cn30xx; - struct cvmx_mio_fus_prog_s cn31xx; - struct cvmx_mio_fus_prog_s cn38xx; - struct cvmx_mio_fus_prog_s cn38xxp2; - struct cvmx_mio_fus_prog_s cn50xx; - struct cvmx_mio_fus_prog_s cn52xx; - struct cvmx_mio_fus_prog_s cn52xxp1; - struct cvmx_mio_fus_prog_s cn56xx; - struct cvmx_mio_fus_prog_s cn56xxp1; - struct cvmx_mio_fus_prog_s cn58xx; - struct cvmx_mio_fus_prog_s cn58xxp1; -}; - -union cvmx_mio_fus_prog_times { - uint64_t u64; - struct cvmx_mio_fus_prog_times_s { - uint64_t reserved_33_63:31; - uint64_t prog_pin:1; - uint64_t out:8; - uint64_t sclk_lo:4; - uint64_t sclk_hi:12; - uint64_t setup:8; - } s; - struct cvmx_mio_fus_prog_times_s cn50xx; - struct cvmx_mio_fus_prog_times_s cn52xx; - struct cvmx_mio_fus_prog_times_s cn52xxp1; - struct cvmx_mio_fus_prog_times_s cn56xx; - struct cvmx_mio_fus_prog_times_s cn56xxp1; - struct cvmx_mio_fus_prog_times_s cn58xx; - struct cvmx_mio_fus_prog_times_s cn58xxp1; -}; - -union cvmx_mio_fus_rcmd { - uint64_t u64; - struct cvmx_mio_fus_rcmd_s { - uint64_t reserved_24_63:40; - uint64_t dat:8; - uint64_t reserved_13_15:3; - uint64_t pend:1; - uint64_t reserved_9_11:3; - uint64_t efuse:1; - uint64_t addr:8; - } s; - struct cvmx_mio_fus_rcmd_cn30xx { - uint64_t reserved_24_63:40; - uint64_t dat:8; - uint64_t reserved_13_15:3; - uint64_t pend:1; - uint64_t reserved_9_11:3; - uint64_t efuse:1; - uint64_t reserved_7_7:1; - uint64_t addr:7; - } cn30xx; - struct cvmx_mio_fus_rcmd_cn30xx cn31xx; - struct cvmx_mio_fus_rcmd_cn30xx cn38xx; - struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; - struct cvmx_mio_fus_rcmd_cn30xx cn50xx; - struct cvmx_mio_fus_rcmd_s cn52xx; - struct cvmx_mio_fus_rcmd_s cn52xxp1; - struct cvmx_mio_fus_rcmd_s cn56xx; - struct cvmx_mio_fus_rcmd_s cn56xxp1; - struct cvmx_mio_fus_rcmd_cn30xx cn58xx; - struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; -}; - -union cvmx_mio_fus_spr_repair_res { - uint64_t u64; - struct cvmx_mio_fus_spr_repair_res_s { - uint64_t reserved_42_63:22; - uint64_t repair2:14; - uint64_t repair1:14; - uint64_t repair0:14; - } s; - struct cvmx_mio_fus_spr_repair_res_s cn30xx; - struct cvmx_mio_fus_spr_repair_res_s cn31xx; - struct cvmx_mio_fus_spr_repair_res_s cn38xx; - struct cvmx_mio_fus_spr_repair_res_s cn50xx; - struct cvmx_mio_fus_spr_repair_res_s cn52xx; - struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; - struct cvmx_mio_fus_spr_repair_res_s cn56xx; - struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; - struct cvmx_mio_fus_spr_repair_res_s cn58xx; - struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; -}; - -union cvmx_mio_fus_spr_repair_sum { - uint64_t u64; - struct cvmx_mio_fus_spr_repair_sum_s { - uint64_t reserved_1_63:63; - uint64_t too_many:1; - } s; - struct cvmx_mio_fus_spr_repair_sum_s cn30xx; - struct cvmx_mio_fus_spr_repair_sum_s cn31xx; - struct cvmx_mio_fus_spr_repair_sum_s cn38xx; - struct cvmx_mio_fus_spr_repair_sum_s cn50xx; - struct cvmx_mio_fus_spr_repair_sum_s cn52xx; - struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; - struct cvmx_mio_fus_spr_repair_sum_s cn56xx; - struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; - struct cvmx_mio_fus_spr_repair_sum_s cn58xx; - struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; -}; - -union cvmx_mio_fus_unlock { - uint64_t u64; - struct cvmx_mio_fus_unlock_s { - uint64_t reserved_24_63:40; - uint64_t key:24; - } s; - struct cvmx_mio_fus_unlock_s cn30xx; - struct cvmx_mio_fus_unlock_s cn31xx; -}; - -union cvmx_mio_fus_wadr { - uint64_t u64; - struct cvmx_mio_fus_wadr_s { - uint64_t reserved_10_63:54; - uint64_t addr:10; - } s; - struct cvmx_mio_fus_wadr_s cn30xx; - struct cvmx_mio_fus_wadr_s cn31xx; - struct cvmx_mio_fus_wadr_s cn38xx; - struct cvmx_mio_fus_wadr_s cn38xxp2; - struct cvmx_mio_fus_wadr_cn50xx { - uint64_t reserved_2_63:62; - uint64_t addr:2; - } cn50xx; - struct cvmx_mio_fus_wadr_cn52xx { - uint64_t reserved_3_63:61; - uint64_t addr:3; - } cn52xx; - struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; - struct cvmx_mio_fus_wadr_cn52xx cn56xx; - struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; - struct cvmx_mio_fus_wadr_cn50xx cn58xx; - struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; -}; - -union cvmx_mio_ndf_dma_cfg { - uint64_t u64; - struct cvmx_mio_ndf_dma_cfg_s { - uint64_t en:1; - uint64_t rw:1; - uint64_t clr:1; - uint64_t reserved_60_60:1; - uint64_t swap32:1; - uint64_t swap16:1; - uint64_t swap8:1; - uint64_t endian:1; - uint64_t size:20; - uint64_t adr:36; - } s; - struct cvmx_mio_ndf_dma_cfg_s cn52xx; -}; - -union cvmx_mio_ndf_dma_int { - uint64_t u64; - struct cvmx_mio_ndf_dma_int_s { - uint64_t reserved_1_63:63; - uint64_t done:1; - } s; - struct cvmx_mio_ndf_dma_int_s cn52xx; -}; - -union cvmx_mio_ndf_dma_int_en { - uint64_t u64; - struct cvmx_mio_ndf_dma_int_en_s { - uint64_t reserved_1_63:63; - uint64_t done:1; - } s; - struct cvmx_mio_ndf_dma_int_en_s cn52xx; -}; - -union cvmx_mio_pll_ctl { - uint64_t u64; - struct cvmx_mio_pll_ctl_s { - uint64_t reserved_5_63:59; - uint64_t bw_ctl:5; - } s; - struct cvmx_mio_pll_ctl_s cn30xx; - struct cvmx_mio_pll_ctl_s cn31xx; -}; - -union cvmx_mio_pll_setting { - uint64_t u64; - struct cvmx_mio_pll_setting_s { - uint64_t reserved_17_63:47; - uint64_t setting:17; - } s; - struct cvmx_mio_pll_setting_s cn30xx; - struct cvmx_mio_pll_setting_s cn31xx; -}; - -union cvmx_mio_twsx_int { - uint64_t u64; - struct cvmx_mio_twsx_int_s { - uint64_t reserved_12_63:52; - uint64_t scl:1; - uint64_t sda:1; - uint64_t scl_ovr:1; - uint64_t sda_ovr:1; - uint64_t reserved_7_7:1; - uint64_t core_en:1; - uint64_t ts_en:1; - uint64_t st_en:1; - uint64_t reserved_3_3:1; - uint64_t core_int:1; - uint64_t ts_int:1; - uint64_t st_int:1; - } s; - struct cvmx_mio_twsx_int_s cn30xx; - struct cvmx_mio_twsx_int_s cn31xx; - struct cvmx_mio_twsx_int_s cn38xx; - struct cvmx_mio_twsx_int_cn38xxp2 { - uint64_t reserved_7_63:57; - uint64_t core_en:1; - uint64_t ts_en:1; - uint64_t st_en:1; - uint64_t reserved_3_3:1; - uint64_t core_int:1; - uint64_t ts_int:1; - uint64_t st_int:1; - } cn38xxp2; - struct cvmx_mio_twsx_int_s cn50xx; - struct cvmx_mio_twsx_int_s cn52xx; - struct cvmx_mio_twsx_int_s cn52xxp1; - struct cvmx_mio_twsx_int_s cn56xx; - struct cvmx_mio_twsx_int_s cn56xxp1; - struct cvmx_mio_twsx_int_s cn58xx; - struct cvmx_mio_twsx_int_s cn58xxp1; -}; - -union cvmx_mio_twsx_sw_twsi { - uint64_t u64; - struct cvmx_mio_twsx_sw_twsi_s { - uint64_t v:1; - uint64_t slonly:1; - uint64_t eia:1; - uint64_t op:4; - uint64_t r:1; - uint64_t sovr:1; - uint64_t size:3; - uint64_t scr:2; - uint64_t a:10; - uint64_t ia:5; - uint64_t eop_ia:3; - uint64_t d:32; - } s; - struct cvmx_mio_twsx_sw_twsi_s cn30xx; - struct cvmx_mio_twsx_sw_twsi_s cn31xx; - struct cvmx_mio_twsx_sw_twsi_s cn38xx; - struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; - struct cvmx_mio_twsx_sw_twsi_s cn50xx; - struct cvmx_mio_twsx_sw_twsi_s cn52xx; - struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; - struct cvmx_mio_twsx_sw_twsi_s cn56xx; - struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; - struct cvmx_mio_twsx_sw_twsi_s cn58xx; - struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; -}; - -union cvmx_mio_twsx_sw_twsi_ext { - uint64_t u64; - struct cvmx_mio_twsx_sw_twsi_ext_s { - uint64_t reserved_40_63:24; - uint64_t ia:8; - uint64_t d:32; - } s; - struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; - struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; - struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; - struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; - struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; -}; - -union cvmx_mio_twsx_twsi_sw { - uint64_t u64; - struct cvmx_mio_twsx_twsi_sw_s { - uint64_t v:2; - uint64_t reserved_32_61:30; - uint64_t d:32; - } s; - struct cvmx_mio_twsx_twsi_sw_s cn30xx; - struct cvmx_mio_twsx_twsi_sw_s cn31xx; - struct cvmx_mio_twsx_twsi_sw_s cn38xx; - struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; - struct cvmx_mio_twsx_twsi_sw_s cn50xx; - struct cvmx_mio_twsx_twsi_sw_s cn52xx; - struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; - struct cvmx_mio_twsx_twsi_sw_s cn56xx; - struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; - struct cvmx_mio_twsx_twsi_sw_s cn58xx; - struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; -}; - -union cvmx_mio_uartx_dlh { - uint64_t u64; - struct cvmx_mio_uartx_dlh_s { - uint64_t reserved_8_63:56; - uint64_t dlh:8; - } s; - struct cvmx_mio_uartx_dlh_s cn30xx; - struct cvmx_mio_uartx_dlh_s cn31xx; - struct cvmx_mio_uartx_dlh_s cn38xx; - struct cvmx_mio_uartx_dlh_s cn38xxp2; - struct cvmx_mio_uartx_dlh_s cn50xx; - struct cvmx_mio_uartx_dlh_s cn52xx; - struct cvmx_mio_uartx_dlh_s cn52xxp1; - struct cvmx_mio_uartx_dlh_s cn56xx; - struct cvmx_mio_uartx_dlh_s cn56xxp1; - struct cvmx_mio_uartx_dlh_s cn58xx; - struct cvmx_mio_uartx_dlh_s cn58xxp1; -}; - -union cvmx_mio_uartx_dll { - uint64_t u64; - struct cvmx_mio_uartx_dll_s { - uint64_t reserved_8_63:56; - uint64_t dll:8; - } s; - struct cvmx_mio_uartx_dll_s cn30xx; - struct cvmx_mio_uartx_dll_s cn31xx; - struct cvmx_mio_uartx_dll_s cn38xx; - struct cvmx_mio_uartx_dll_s cn38xxp2; - struct cvmx_mio_uartx_dll_s cn50xx; - struct cvmx_mio_uartx_dll_s cn52xx; - struct cvmx_mio_uartx_dll_s cn52xxp1; - struct cvmx_mio_uartx_dll_s cn56xx; - struct cvmx_mio_uartx_dll_s cn56xxp1; - struct cvmx_mio_uartx_dll_s cn58xx; - struct cvmx_mio_uartx_dll_s cn58xxp1; -}; - -union cvmx_mio_uartx_far { - uint64_t u64; - struct cvmx_mio_uartx_far_s { - uint64_t reserved_1_63:63; - uint64_t far:1; - } s; - struct cvmx_mio_uartx_far_s cn30xx; - struct cvmx_mio_uartx_far_s cn31xx; - struct cvmx_mio_uartx_far_s cn38xx; - struct cvmx_mio_uartx_far_s cn38xxp2; - struct cvmx_mio_uartx_far_s cn50xx; - struct cvmx_mio_uartx_far_s cn52xx; - struct cvmx_mio_uartx_far_s cn52xxp1; - struct cvmx_mio_uartx_far_s cn56xx; - struct cvmx_mio_uartx_far_s cn56xxp1; - struct cvmx_mio_uartx_far_s cn58xx; - struct cvmx_mio_uartx_far_s cn58xxp1; -}; - -union cvmx_mio_uartx_fcr { - uint64_t u64; - struct cvmx_mio_uartx_fcr_s { - uint64_t reserved_8_63:56; - uint64_t rxtrig:2; - uint64_t txtrig:2; - uint64_t reserved_3_3:1; - uint64_t txfr:1; - uint64_t rxfr:1; - uint64_t en:1; - } s; - struct cvmx_mio_uartx_fcr_s cn30xx; - struct cvmx_mio_uartx_fcr_s cn31xx; - struct cvmx_mio_uartx_fcr_s cn38xx; - struct cvmx_mio_uartx_fcr_s cn38xxp2; - struct cvmx_mio_uartx_fcr_s cn50xx; - struct cvmx_mio_uartx_fcr_s cn52xx; - struct cvmx_mio_uartx_fcr_s cn52xxp1; - struct cvmx_mio_uartx_fcr_s cn56xx; - struct cvmx_mio_uartx_fcr_s cn56xxp1; - struct cvmx_mio_uartx_fcr_s cn58xx; - struct cvmx_mio_uartx_fcr_s cn58xxp1; -}; - -union cvmx_mio_uartx_htx { - uint64_t u64; - struct cvmx_mio_uartx_htx_s { - uint64_t reserved_1_63:63; - uint64_t htx:1; - } s; - struct cvmx_mio_uartx_htx_s cn30xx; - struct cvmx_mio_uartx_htx_s cn31xx; - struct cvmx_mio_uartx_htx_s cn38xx; - struct cvmx_mio_uartx_htx_s cn38xxp2; - struct cvmx_mio_uartx_htx_s cn50xx; - struct cvmx_mio_uartx_htx_s cn52xx; - struct cvmx_mio_uartx_htx_s cn52xxp1; - struct cvmx_mio_uartx_htx_s cn56xx; - struct cvmx_mio_uartx_htx_s cn56xxp1; - struct cvmx_mio_uartx_htx_s cn58xx; - struct cvmx_mio_uartx_htx_s cn58xxp1; -}; - -union cvmx_mio_uartx_ier { - uint64_t u64; - struct cvmx_mio_uartx_ier_s { - uint64_t reserved_8_63:56; - uint64_t ptime:1; - uint64_t reserved_4_6:3; - uint64_t edssi:1; - uint64_t elsi:1; - uint64_t etbei:1; - uint64_t erbfi:1; - } s; - struct cvmx_mio_uartx_ier_s cn30xx; - struct cvmx_mio_uartx_ier_s cn31xx; - struct cvmx_mio_uartx_ier_s cn38xx; - struct cvmx_mio_uartx_ier_s cn38xxp2; - struct cvmx_mio_uartx_ier_s cn50xx; - struct cvmx_mio_uartx_ier_s cn52xx; - struct cvmx_mio_uartx_ier_s cn52xxp1; - struct cvmx_mio_uartx_ier_s cn56xx; - struct cvmx_mio_uartx_ier_s cn56xxp1; - struct cvmx_mio_uartx_ier_s cn58xx; - struct cvmx_mio_uartx_ier_s cn58xxp1; -}; - -union cvmx_mio_uartx_iir { - uint64_t u64; - struct cvmx_mio_uartx_iir_s { - uint64_t reserved_8_63:56; - uint64_t fen:2; - uint64_t reserved_4_5:2; - uint64_t iid:4; - } s; - struct cvmx_mio_uartx_iir_s cn30xx; - struct cvmx_mio_uartx_iir_s cn31xx; - struct cvmx_mio_uartx_iir_s cn38xx; - struct cvmx_mio_uartx_iir_s cn38xxp2; - struct cvmx_mio_uartx_iir_s cn50xx; - struct cvmx_mio_uartx_iir_s cn52xx; - struct cvmx_mio_uartx_iir_s cn52xxp1; - struct cvmx_mio_uartx_iir_s cn56xx; - struct cvmx_mio_uartx_iir_s cn56xxp1; - struct cvmx_mio_uartx_iir_s cn58xx; - struct cvmx_mio_uartx_iir_s cn58xxp1; -}; - -union cvmx_mio_uartx_lcr { - uint64_t u64; - struct cvmx_mio_uartx_lcr_s { - uint64_t reserved_8_63:56; - uint64_t dlab:1; - uint64_t brk:1; - uint64_t reserved_5_5:1; - uint64_t eps:1; - uint64_t pen:1; - uint64_t stop:1; - uint64_t cls:2; - } s; - struct cvmx_mio_uartx_lcr_s cn30xx; - struct cvmx_mio_uartx_lcr_s cn31xx; - struct cvmx_mio_uartx_lcr_s cn38xx; - struct cvmx_mio_uartx_lcr_s cn38xxp2; - struct cvmx_mio_uartx_lcr_s cn50xx; - struct cvmx_mio_uartx_lcr_s cn52xx; - struct cvmx_mio_uartx_lcr_s cn52xxp1; - struct cvmx_mio_uartx_lcr_s cn56xx; - struct cvmx_mio_uartx_lcr_s cn56xxp1; - struct cvmx_mio_uartx_lcr_s cn58xx; - struct cvmx_mio_uartx_lcr_s cn58xxp1; -}; - -union cvmx_mio_uartx_lsr { - uint64_t u64; - struct cvmx_mio_uartx_lsr_s { - uint64_t reserved_8_63:56; - uint64_t ferr:1; - uint64_t temt:1; - uint64_t thre:1; - uint64_t bi:1; - uint64_t fe:1; - uint64_t pe:1; - uint64_t oe:1; - uint64_t dr:1; - } s; - struct cvmx_mio_uartx_lsr_s cn30xx; - struct cvmx_mio_uartx_lsr_s cn31xx; - struct cvmx_mio_uartx_lsr_s cn38xx; - struct cvmx_mio_uartx_lsr_s cn38xxp2; - struct cvmx_mio_uartx_lsr_s cn50xx; - struct cvmx_mio_uartx_lsr_s cn52xx; - struct cvmx_mio_uartx_lsr_s cn52xxp1; - struct cvmx_mio_uartx_lsr_s cn56xx; - struct cvmx_mio_uartx_lsr_s cn56xxp1; - struct cvmx_mio_uartx_lsr_s cn58xx; - struct cvmx_mio_uartx_lsr_s cn58xxp1; -}; - -union cvmx_mio_uartx_mcr { - uint64_t u64; - struct cvmx_mio_uartx_mcr_s { - uint64_t reserved_6_63:58; - uint64_t afce:1; - uint64_t loop:1; - uint64_t out2:1; - uint64_t out1:1; - uint64_t rts:1; - uint64_t dtr:1; - } s; - struct cvmx_mio_uartx_mcr_s cn30xx; - struct cvmx_mio_uartx_mcr_s cn31xx; - struct cvmx_mio_uartx_mcr_s cn38xx; - struct cvmx_mio_uartx_mcr_s cn38xxp2; - struct cvmx_mio_uartx_mcr_s cn50xx; - struct cvmx_mio_uartx_mcr_s cn52xx; - struct cvmx_mio_uartx_mcr_s cn52xxp1; - struct cvmx_mio_uartx_mcr_s cn56xx; - struct cvmx_mio_uartx_mcr_s cn56xxp1; - struct cvmx_mio_uartx_mcr_s cn58xx; - struct cvmx_mio_uartx_mcr_s cn58xxp1; -}; - -union cvmx_mio_uartx_msr { - uint64_t u64; - struct cvmx_mio_uartx_msr_s { - uint64_t reserved_8_63:56; - uint64_t dcd:1; - uint64_t ri:1; - uint64_t dsr:1; - uint64_t cts:1; - uint64_t ddcd:1; - uint64_t teri:1; - uint64_t ddsr:1; - uint64_t dcts:1; - } s; - struct cvmx_mio_uartx_msr_s cn30xx; - struct cvmx_mio_uartx_msr_s cn31xx; - struct cvmx_mio_uartx_msr_s cn38xx; - struct cvmx_mio_uartx_msr_s cn38xxp2; - struct cvmx_mio_uartx_msr_s cn50xx; - struct cvmx_mio_uartx_msr_s cn52xx; - struct cvmx_mio_uartx_msr_s cn52xxp1; - struct cvmx_mio_uartx_msr_s cn56xx; - struct cvmx_mio_uartx_msr_s cn56xxp1; - struct cvmx_mio_uartx_msr_s cn58xx; - struct cvmx_mio_uartx_msr_s cn58xxp1; -}; - -union cvmx_mio_uartx_rbr { - uint64_t u64; - struct cvmx_mio_uartx_rbr_s { - uint64_t reserved_8_63:56; - uint64_t rbr:8; - } s; - struct cvmx_mio_uartx_rbr_s cn30xx; - struct cvmx_mio_uartx_rbr_s cn31xx; - struct cvmx_mio_uartx_rbr_s cn38xx; - struct cvmx_mio_uartx_rbr_s cn38xxp2; - struct cvmx_mio_uartx_rbr_s cn50xx; - struct cvmx_mio_uartx_rbr_s cn52xx; - struct cvmx_mio_uartx_rbr_s cn52xxp1; - struct cvmx_mio_uartx_rbr_s cn56xx; - struct cvmx_mio_uartx_rbr_s cn56xxp1; - struct cvmx_mio_uartx_rbr_s cn58xx; - struct cvmx_mio_uartx_rbr_s cn58xxp1; -}; - -union cvmx_mio_uartx_rfl { - uint64_t u64; - struct cvmx_mio_uartx_rfl_s { - uint64_t reserved_7_63:57; - uint64_t rfl:7; - } s; - struct cvmx_mio_uartx_rfl_s cn30xx; - struct cvmx_mio_uartx_rfl_s cn31xx; - struct cvmx_mio_uartx_rfl_s cn38xx; - struct cvmx_mio_uartx_rfl_s cn38xxp2; - struct cvmx_mio_uartx_rfl_s cn50xx; - struct cvmx_mio_uartx_rfl_s cn52xx; - struct cvmx_mio_uartx_rfl_s cn52xxp1; - struct cvmx_mio_uartx_rfl_s cn56xx; - struct cvmx_mio_uartx_rfl_s cn56xxp1; - struct cvmx_mio_uartx_rfl_s cn58xx; - struct cvmx_mio_uartx_rfl_s cn58xxp1; -}; - -union cvmx_mio_uartx_rfw { - uint64_t u64; - struct cvmx_mio_uartx_rfw_s { - uint64_t reserved_10_63:54; - uint64_t rffe:1; - uint64_t rfpe:1; - uint64_t rfwd:8; - } s; - struct cvmx_mio_uartx_rfw_s cn30xx; - struct cvmx_mio_uartx_rfw_s cn31xx; - struct cvmx_mio_uartx_rfw_s cn38xx; - struct cvmx_mio_uartx_rfw_s cn38xxp2; - struct cvmx_mio_uartx_rfw_s cn50xx; - struct cvmx_mio_uartx_rfw_s cn52xx; - struct cvmx_mio_uartx_rfw_s cn52xxp1; - struct cvmx_mio_uartx_rfw_s cn56xx; - struct cvmx_mio_uartx_rfw_s cn56xxp1; - struct cvmx_mio_uartx_rfw_s cn58xx; - struct cvmx_mio_uartx_rfw_s cn58xxp1; -}; - -union cvmx_mio_uartx_sbcr { - uint64_t u64; - struct cvmx_mio_uartx_sbcr_s { - uint64_t reserved_1_63:63; - uint64_t sbcr:1; - } s; - struct cvmx_mio_uartx_sbcr_s cn30xx; - struct cvmx_mio_uartx_sbcr_s cn31xx; - struct cvmx_mio_uartx_sbcr_s cn38xx; - struct cvmx_mio_uartx_sbcr_s cn38xxp2; - struct cvmx_mio_uartx_sbcr_s cn50xx; - struct cvmx_mio_uartx_sbcr_s cn52xx; - struct cvmx_mio_uartx_sbcr_s cn52xxp1; - struct cvmx_mio_uartx_sbcr_s cn56xx; - struct cvmx_mio_uartx_sbcr_s cn56xxp1; - struct cvmx_mio_uartx_sbcr_s cn58xx; - struct cvmx_mio_uartx_sbcr_s cn58xxp1; -}; - -union cvmx_mio_uartx_scr { - uint64_t u64; - struct cvmx_mio_uartx_scr_s { - uint64_t reserved_8_63:56; - uint64_t scr:8; - } s; - struct cvmx_mio_uartx_scr_s cn30xx; - struct cvmx_mio_uartx_scr_s cn31xx; - struct cvmx_mio_uartx_scr_s cn38xx; - struct cvmx_mio_uartx_scr_s cn38xxp2; - struct cvmx_mio_uartx_scr_s cn50xx; - struct cvmx_mio_uartx_scr_s cn52xx; - struct cvmx_mio_uartx_scr_s cn52xxp1; - struct cvmx_mio_uartx_scr_s cn56xx; - struct cvmx_mio_uartx_scr_s cn56xxp1; - struct cvmx_mio_uartx_scr_s cn58xx; - struct cvmx_mio_uartx_scr_s cn58xxp1; -}; - -union cvmx_mio_uartx_sfe { - uint64_t u64; - struct cvmx_mio_uartx_sfe_s { - uint64_t reserved_1_63:63; - uint64_t sfe:1; - } s; - struct cvmx_mio_uartx_sfe_s cn30xx; - struct cvmx_mio_uartx_sfe_s cn31xx; - struct cvmx_mio_uartx_sfe_s cn38xx; - struct cvmx_mio_uartx_sfe_s cn38xxp2; - struct cvmx_mio_uartx_sfe_s cn50xx; - struct cvmx_mio_uartx_sfe_s cn52xx; - struct cvmx_mio_uartx_sfe_s cn52xxp1; - struct cvmx_mio_uartx_sfe_s cn56xx; - struct cvmx_mio_uartx_sfe_s cn56xxp1; - struct cvmx_mio_uartx_sfe_s cn58xx; - struct cvmx_mio_uartx_sfe_s cn58xxp1; -}; - -union cvmx_mio_uartx_srr { - uint64_t u64; - struct cvmx_mio_uartx_srr_s { - uint64_t reserved_3_63:61; - uint64_t stfr:1; - uint64_t srfr:1; - uint64_t usr:1; - } s; - struct cvmx_mio_uartx_srr_s cn30xx; - struct cvmx_mio_uartx_srr_s cn31xx; - struct cvmx_mio_uartx_srr_s cn38xx; - struct cvmx_mio_uartx_srr_s cn38xxp2; - struct cvmx_mio_uartx_srr_s cn50xx; - struct cvmx_mio_uartx_srr_s cn52xx; - struct cvmx_mio_uartx_srr_s cn52xxp1; - struct cvmx_mio_uartx_srr_s cn56xx; - struct cvmx_mio_uartx_srr_s cn56xxp1; - struct cvmx_mio_uartx_srr_s cn58xx; - struct cvmx_mio_uartx_srr_s cn58xxp1; -}; - -union cvmx_mio_uartx_srt { - uint64_t u64; - struct cvmx_mio_uartx_srt_s { - uint64_t reserved_2_63:62; - uint64_t srt:2; - } s; - struct cvmx_mio_uartx_srt_s cn30xx; - struct cvmx_mio_uartx_srt_s cn31xx; - struct cvmx_mio_uartx_srt_s cn38xx; - struct cvmx_mio_uartx_srt_s cn38xxp2; - struct cvmx_mio_uartx_srt_s cn50xx; - struct cvmx_mio_uartx_srt_s cn52xx; - struct cvmx_mio_uartx_srt_s cn52xxp1; - struct cvmx_mio_uartx_srt_s cn56xx; - struct cvmx_mio_uartx_srt_s cn56xxp1; - struct cvmx_mio_uartx_srt_s cn58xx; - struct cvmx_mio_uartx_srt_s cn58xxp1; -}; - -union cvmx_mio_uartx_srts { - uint64_t u64; - struct cvmx_mio_uartx_srts_s { - uint64_t reserved_1_63:63; - uint64_t srts:1; - } s; - struct cvmx_mio_uartx_srts_s cn30xx; - struct cvmx_mio_uartx_srts_s cn31xx; - struct cvmx_mio_uartx_srts_s cn38xx; - struct cvmx_mio_uartx_srts_s cn38xxp2; - struct cvmx_mio_uartx_srts_s cn50xx; - struct cvmx_mio_uartx_srts_s cn52xx; - struct cvmx_mio_uartx_srts_s cn52xxp1; - struct cvmx_mio_uartx_srts_s cn56xx; - struct cvmx_mio_uartx_srts_s cn56xxp1; - struct cvmx_mio_uartx_srts_s cn58xx; - struct cvmx_mio_uartx_srts_s cn58xxp1; -}; - -union cvmx_mio_uartx_stt { - uint64_t u64; - struct cvmx_mio_uartx_stt_s { - uint64_t reserved_2_63:62; - uint64_t stt:2; - } s; - struct cvmx_mio_uartx_stt_s cn30xx; - struct cvmx_mio_uartx_stt_s cn31xx; - struct cvmx_mio_uartx_stt_s cn38xx; - struct cvmx_mio_uartx_stt_s cn38xxp2; - struct cvmx_mio_uartx_stt_s cn50xx; - struct cvmx_mio_uartx_stt_s cn52xx; - struct cvmx_mio_uartx_stt_s cn52xxp1; - struct cvmx_mio_uartx_stt_s cn56xx; - struct cvmx_mio_uartx_stt_s cn56xxp1; - struct cvmx_mio_uartx_stt_s cn58xx; - struct cvmx_mio_uartx_stt_s cn58xxp1; -}; - -union cvmx_mio_uartx_tfl { - uint64_t u64; - struct cvmx_mio_uartx_tfl_s { - uint64_t reserved_7_63:57; - uint64_t tfl:7; - } s; - struct cvmx_mio_uartx_tfl_s cn30xx; - struct cvmx_mio_uartx_tfl_s cn31xx; - struct cvmx_mio_uartx_tfl_s cn38xx; - struct cvmx_mio_uartx_tfl_s cn38xxp2; - struct cvmx_mio_uartx_tfl_s cn50xx; - struct cvmx_mio_uartx_tfl_s cn52xx; - struct cvmx_mio_uartx_tfl_s cn52xxp1; - struct cvmx_mio_uartx_tfl_s cn56xx; - struct cvmx_mio_uartx_tfl_s cn56xxp1; - struct cvmx_mio_uartx_tfl_s cn58xx; - struct cvmx_mio_uartx_tfl_s cn58xxp1; -}; - -union cvmx_mio_uartx_tfr { - uint64_t u64; - struct cvmx_mio_uartx_tfr_s { - uint64_t reserved_8_63:56; - uint64_t tfr:8; - } s; - struct cvmx_mio_uartx_tfr_s cn30xx; - struct cvmx_mio_uartx_tfr_s cn31xx; - struct cvmx_mio_uartx_tfr_s cn38xx; - struct cvmx_mio_uartx_tfr_s cn38xxp2; - struct cvmx_mio_uartx_tfr_s cn50xx; - struct cvmx_mio_uartx_tfr_s cn52xx; - struct cvmx_mio_uartx_tfr_s cn52xxp1; - struct cvmx_mio_uartx_tfr_s cn56xx; - struct cvmx_mio_uartx_tfr_s cn56xxp1; - struct cvmx_mio_uartx_tfr_s cn58xx; - struct cvmx_mio_uartx_tfr_s cn58xxp1; -}; - -union cvmx_mio_uartx_thr { - uint64_t u64; - struct cvmx_mio_uartx_thr_s { - uint64_t reserved_8_63:56; - uint64_t thr:8; - } s; - struct cvmx_mio_uartx_thr_s cn30xx; - struct cvmx_mio_uartx_thr_s cn31xx; - struct cvmx_mio_uartx_thr_s cn38xx; - struct cvmx_mio_uartx_thr_s cn38xxp2; - struct cvmx_mio_uartx_thr_s cn50xx; - struct cvmx_mio_uartx_thr_s cn52xx; - struct cvmx_mio_uartx_thr_s cn52xxp1; - struct cvmx_mio_uartx_thr_s cn56xx; - struct cvmx_mio_uartx_thr_s cn56xxp1; - struct cvmx_mio_uartx_thr_s cn58xx; - struct cvmx_mio_uartx_thr_s cn58xxp1; -}; - -union cvmx_mio_uartx_usr { - uint64_t u64; - struct cvmx_mio_uartx_usr_s { - uint64_t reserved_5_63:59; - uint64_t rff:1; - uint64_t rfne:1; - uint64_t tfe:1; - uint64_t tfnf:1; - uint64_t busy:1; - } s; - struct cvmx_mio_uartx_usr_s cn30xx; - struct cvmx_mio_uartx_usr_s cn31xx; - struct cvmx_mio_uartx_usr_s cn38xx; - struct cvmx_mio_uartx_usr_s cn38xxp2; - struct cvmx_mio_uartx_usr_s cn50xx; - struct cvmx_mio_uartx_usr_s cn52xx; - struct cvmx_mio_uartx_usr_s cn52xxp1; - struct cvmx_mio_uartx_usr_s cn56xx; - struct cvmx_mio_uartx_usr_s cn56xxp1; - struct cvmx_mio_uartx_usr_s cn58xx; - struct cvmx_mio_uartx_usr_s cn58xxp1; -}; - -union cvmx_mio_uart2_dlh { - uint64_t u64; - struct cvmx_mio_uart2_dlh_s { - uint64_t reserved_8_63:56; - uint64_t dlh:8; - } s; - struct cvmx_mio_uart2_dlh_s cn52xx; - struct cvmx_mio_uart2_dlh_s cn52xxp1; -}; - -union cvmx_mio_uart2_dll { - uint64_t u64; - struct cvmx_mio_uart2_dll_s { - uint64_t reserved_8_63:56; - uint64_t dll:8; - } s; - struct cvmx_mio_uart2_dll_s cn52xx; - struct cvmx_mio_uart2_dll_s cn52xxp1; -}; - -union cvmx_mio_uart2_far { - uint64_t u64; - struct cvmx_mio_uart2_far_s { - uint64_t reserved_1_63:63; - uint64_t far:1; - } s; - struct cvmx_mio_uart2_far_s cn52xx; - struct cvmx_mio_uart2_far_s cn52xxp1; -}; - -union cvmx_mio_uart2_fcr { - uint64_t u64; - struct cvmx_mio_uart2_fcr_s { - uint64_t reserved_8_63:56; - uint64_t rxtrig:2; - uint64_t txtrig:2; - uint64_t reserved_3_3:1; - uint64_t txfr:1; - uint64_t rxfr:1; - uint64_t en:1; - } s; - struct cvmx_mio_uart2_fcr_s cn52xx; - struct cvmx_mio_uart2_fcr_s cn52xxp1; -}; - -union cvmx_mio_uart2_htx { - uint64_t u64; - struct cvmx_mio_uart2_htx_s { - uint64_t reserved_1_63:63; - uint64_t htx:1; - } s; - struct cvmx_mio_uart2_htx_s cn52xx; - struct cvmx_mio_uart2_htx_s cn52xxp1; -}; - -union cvmx_mio_uart2_ier { - uint64_t u64; - struct cvmx_mio_uart2_ier_s { - uint64_t reserved_8_63:56; - uint64_t ptime:1; - uint64_t reserved_4_6:3; - uint64_t edssi:1; - uint64_t elsi:1; - uint64_t etbei:1; - uint64_t erbfi:1; - } s; - struct cvmx_mio_uart2_ier_s cn52xx; - struct cvmx_mio_uart2_ier_s cn52xxp1; -}; - -union cvmx_mio_uart2_iir { - uint64_t u64; - struct cvmx_mio_uart2_iir_s { - uint64_t reserved_8_63:56; - uint64_t fen:2; - uint64_t reserved_4_5:2; - uint64_t iid:4; - } s; - struct cvmx_mio_uart2_iir_s cn52xx; - struct cvmx_mio_uart2_iir_s cn52xxp1; -}; - -union cvmx_mio_uart2_lcr { - uint64_t u64; - struct cvmx_mio_uart2_lcr_s { - uint64_t reserved_8_63:56; - uint64_t dlab:1; - uint64_t brk:1; - uint64_t reserved_5_5:1; - uint64_t eps:1; - uint64_t pen:1; - uint64_t stop:1; - uint64_t cls:2; - } s; - struct cvmx_mio_uart2_lcr_s cn52xx; - struct cvmx_mio_uart2_lcr_s cn52xxp1; -}; - -union cvmx_mio_uart2_lsr { - uint64_t u64; - struct cvmx_mio_uart2_lsr_s { - uint64_t reserved_8_63:56; - uint64_t ferr:1; - uint64_t temt:1; - uint64_t thre:1; - uint64_t bi:1; - uint64_t fe:1; - uint64_t pe:1; - uint64_t oe:1; - uint64_t dr:1; - } s; - struct cvmx_mio_uart2_lsr_s cn52xx; - struct cvmx_mio_uart2_lsr_s cn52xxp1; -}; - -union cvmx_mio_uart2_mcr { - uint64_t u64; - struct cvmx_mio_uart2_mcr_s { - uint64_t reserved_6_63:58; - uint64_t afce:1; - uint64_t loop:1; - uint64_t out2:1; - uint64_t out1:1; - uint64_t rts:1; - uint64_t dtr:1; - } s; - struct cvmx_mio_uart2_mcr_s cn52xx; - struct cvmx_mio_uart2_mcr_s cn52xxp1; -}; - -union cvmx_mio_uart2_msr { - uint64_t u64; - struct cvmx_mio_uart2_msr_s { - uint64_t reserved_8_63:56; - uint64_t dcd:1; - uint64_t ri:1; - uint64_t dsr:1; - uint64_t cts:1; - uint64_t ddcd:1; - uint64_t teri:1; - uint64_t ddsr:1; - uint64_t dcts:1; - } s; - struct cvmx_mio_uart2_msr_s cn52xx; - struct cvmx_mio_uart2_msr_s cn52xxp1; -}; - -union cvmx_mio_uart2_rbr { - uint64_t u64; - struct cvmx_mio_uart2_rbr_s { - uint64_t reserved_8_63:56; - uint64_t rbr:8; - } s; - struct cvmx_mio_uart2_rbr_s cn52xx; - struct cvmx_mio_uart2_rbr_s cn52xxp1; -}; - -union cvmx_mio_uart2_rfl { - uint64_t u64; - struct cvmx_mio_uart2_rfl_s { - uint64_t reserved_7_63:57; - uint64_t rfl:7; - } s; - struct cvmx_mio_uart2_rfl_s cn52xx; - struct cvmx_mio_uart2_rfl_s cn52xxp1; -}; - -union cvmx_mio_uart2_rfw { - uint64_t u64; - struct cvmx_mio_uart2_rfw_s { - uint64_t reserved_10_63:54; - uint64_t rffe:1; - uint64_t rfpe:1; - uint64_t rfwd:8; - } s; - struct cvmx_mio_uart2_rfw_s cn52xx; - struct cvmx_mio_uart2_rfw_s cn52xxp1; -}; - -union cvmx_mio_uart2_sbcr { - uint64_t u64; - struct cvmx_mio_uart2_sbcr_s { - uint64_t reserved_1_63:63; - uint64_t sbcr:1; - } s; - struct cvmx_mio_uart2_sbcr_s cn52xx; - struct cvmx_mio_uart2_sbcr_s cn52xxp1; -}; - -union cvmx_mio_uart2_scr { - uint64_t u64; - struct cvmx_mio_uart2_scr_s { - uint64_t reserved_8_63:56; - uint64_t scr:8; - } s; - struct cvmx_mio_uart2_scr_s cn52xx; - struct cvmx_mio_uart2_scr_s cn52xxp1; -}; - -union cvmx_mio_uart2_sfe { - uint64_t u64; - struct cvmx_mio_uart2_sfe_s { - uint64_t reserved_1_63:63; - uint64_t sfe:1; - } s; - struct cvmx_mio_uart2_sfe_s cn52xx; - struct cvmx_mio_uart2_sfe_s cn52xxp1; -}; - -union cvmx_mio_uart2_srr { - uint64_t u64; - struct cvmx_mio_uart2_srr_s { - uint64_t reserved_3_63:61; - uint64_t stfr:1; - uint64_t srfr:1; - uint64_t usr:1; - } s; - struct cvmx_mio_uart2_srr_s cn52xx; - struct cvmx_mio_uart2_srr_s cn52xxp1; -}; - -union cvmx_mio_uart2_srt { - uint64_t u64; - struct cvmx_mio_uart2_srt_s { - uint64_t reserved_2_63:62; - uint64_t srt:2; - } s; - struct cvmx_mio_uart2_srt_s cn52xx; - struct cvmx_mio_uart2_srt_s cn52xxp1; -}; - -union cvmx_mio_uart2_srts { - uint64_t u64; - struct cvmx_mio_uart2_srts_s { - uint64_t reserved_1_63:63; - uint64_t srts:1; - } s; - struct cvmx_mio_uart2_srts_s cn52xx; - struct cvmx_mio_uart2_srts_s cn52xxp1; -}; - -union cvmx_mio_uart2_stt { - uint64_t u64; - struct cvmx_mio_uart2_stt_s { - uint64_t reserved_2_63:62; - uint64_t stt:2; - } s; - struct cvmx_mio_uart2_stt_s cn52xx; - struct cvmx_mio_uart2_stt_s cn52xxp1; -}; - -union cvmx_mio_uart2_tfl { - uint64_t u64; - struct cvmx_mio_uart2_tfl_s { - uint64_t reserved_7_63:57; - uint64_t tfl:7; - } s; - struct cvmx_mio_uart2_tfl_s cn52xx; - struct cvmx_mio_uart2_tfl_s cn52xxp1; -}; - -union cvmx_mio_uart2_tfr { - uint64_t u64; - struct cvmx_mio_uart2_tfr_s { - uint64_t reserved_8_63:56; - uint64_t tfr:8; - } s; - struct cvmx_mio_uart2_tfr_s cn52xx; - struct cvmx_mio_uart2_tfr_s cn52xxp1; -}; - -union cvmx_mio_uart2_thr { - uint64_t u64; - struct cvmx_mio_uart2_thr_s { - uint64_t reserved_8_63:56; - uint64_t thr:8; - } s; - struct cvmx_mio_uart2_thr_s cn52xx; - struct cvmx_mio_uart2_thr_s cn52xxp1; -}; - -union cvmx_mio_uart2_usr { - uint64_t u64; - struct cvmx_mio_uart2_usr_s { - uint64_t reserved_5_63:59; - uint64_t rff:1; - uint64_t rfne:1; - uint64_t tfe:1; - uint64_t tfnf:1; - uint64_t busy:1; - } s; - struct cvmx_mio_uart2_usr_s cn52xx; - struct cvmx_mio_uart2_usr_s cn52xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-packet.h b/trunk/arch/mips/include/asm/octeon/cvmx-packet.h deleted file mode 100644 index 38aefa1bab9d..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-packet.h +++ /dev/null @@ -1,61 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Packet buffer defines. - */ - -#ifndef __CVMX_PACKET_H__ -#define __CVMX_PACKET_H__ - -/** - * This structure defines a buffer pointer on Octeon - */ -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - /* if set, invert the "free" pick of the overall - * packet. HW always sets this bit to 0 on inbound - * packet */ - uint64_t i:1; - - /* Indicates the amount to back up to get to the - * buffer start in cache lines. In most cases this is - * less than one complete cache line, so the value is - * zero */ - uint64_t back:4; - /* The pool that the buffer came from / goes to */ - uint64_t pool:3; - /* The size of the segment pointed to by addr (in bytes) */ - uint64_t size:16; - /* Pointer to the first byte of the data, NOT buffer */ - uint64_t addr:40; - } s; -}; - -#endif /* __CVMX_PACKET_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h deleted file mode 100644 index 2d82e24be51c..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-pow-defs.h +++ /dev/null @@ -1,698 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_POW_DEFS_H__ -#define __CVMX_POW_DEFS_H__ - -#define CVMX_POW_BIST_STAT \ - CVMX_ADD_IO_SEG(0x00016700000003F8ull) -#define CVMX_POW_DS_PC \ - CVMX_ADD_IO_SEG(0x0001670000000398ull) -#define CVMX_POW_ECC_ERR \ - CVMX_ADD_IO_SEG(0x0001670000000218ull) -#define CVMX_POW_INT_CTL \ - CVMX_ADD_IO_SEG(0x0001670000000220ull) -#define CVMX_POW_IQ_CNTX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8)) -#define CVMX_POW_IQ_COM_CNT \ - CVMX_ADD_IO_SEG(0x0001670000000388ull) -#define CVMX_POW_IQ_INT \ - CVMX_ADD_IO_SEG(0x0001670000000238ull) -#define CVMX_POW_IQ_INT_EN \ - CVMX_ADD_IO_SEG(0x0001670000000240ull) -#define CVMX_POW_IQ_THRX(offset) \ - CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8)) -#define CVMX_POW_NOS_CNT \ - CVMX_ADD_IO_SEG(0x0001670000000228ull) -#define CVMX_POW_NW_TIM \ - CVMX_ADD_IO_SEG(0x0001670000000210ull) -#define CVMX_POW_PF_RST_MSK \ - CVMX_ADD_IO_SEG(0x0001670000000230ull) -#define CVMX_POW_PP_GRP_MSKX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8)) -#define CVMX_POW_QOS_RNDX(offset) \ - CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8)) -#define CVMX_POW_QOS_THRX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8)) -#define CVMX_POW_TS_PC \ - CVMX_ADD_IO_SEG(0x0001670000000390ull) -#define CVMX_POW_WA_COM_PC \ - CVMX_ADD_IO_SEG(0x0001670000000380ull) -#define CVMX_POW_WA_PCX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8)) -#define CVMX_POW_WQ_INT \ - CVMX_ADD_IO_SEG(0x0001670000000200ull) -#define CVMX_POW_WQ_INT_CNTX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8)) -#define CVMX_POW_WQ_INT_PC \ - CVMX_ADD_IO_SEG(0x0001670000000208ull) -#define CVMX_POW_WQ_INT_THRX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8)) -#define CVMX_POW_WS_PCX(offset) \ - CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8)) - -union cvmx_pow_bist_stat { - uint64_t u64; - struct cvmx_pow_bist_stat_s { - uint64_t reserved_32_63:32; - uint64_t pp:16; - uint64_t reserved_0_15:16; - } s; - struct cvmx_pow_bist_stat_cn30xx { - uint64_t reserved_17_63:47; - uint64_t pp:1; - uint64_t reserved_9_15:7; - uint64_t cam:1; - uint64_t nbt1:1; - uint64_t nbt0:1; - uint64_t index:1; - uint64_t fidx:1; - uint64_t nbr1:1; - uint64_t nbr0:1; - uint64_t pend:1; - uint64_t adr:1; - } cn30xx; - struct cvmx_pow_bist_stat_cn31xx { - uint64_t reserved_18_63:46; - uint64_t pp:2; - uint64_t reserved_9_15:7; - uint64_t cam:1; - uint64_t nbt1:1; - uint64_t nbt0:1; - uint64_t index:1; - uint64_t fidx:1; - uint64_t nbr1:1; - uint64_t nbr0:1; - uint64_t pend:1; - uint64_t adr:1; - } cn31xx; - struct cvmx_pow_bist_stat_cn38xx { - uint64_t reserved_32_63:32; - uint64_t pp:16; - uint64_t reserved_10_15:6; - uint64_t cam:1; - uint64_t nbt:1; - uint64_t index:1; - uint64_t fidx:1; - uint64_t nbr1:1; - uint64_t nbr0:1; - uint64_t pend1:1; - uint64_t pend0:1; - uint64_t adr1:1; - uint64_t adr0:1; - } cn38xx; - struct cvmx_pow_bist_stat_cn38xx cn38xxp2; - struct cvmx_pow_bist_stat_cn31xx cn50xx; - struct cvmx_pow_bist_stat_cn52xx { - uint64_t reserved_20_63:44; - uint64_t pp:4; - uint64_t reserved_9_15:7; - uint64_t cam:1; - uint64_t nbt1:1; - uint64_t nbt0:1; - uint64_t index:1; - uint64_t fidx:1; - uint64_t nbr1:1; - uint64_t nbr0:1; - uint64_t pend:1; - uint64_t adr:1; - } cn52xx; - struct cvmx_pow_bist_stat_cn52xx cn52xxp1; - struct cvmx_pow_bist_stat_cn56xx { - uint64_t reserved_28_63:36; - uint64_t pp:12; - uint64_t reserved_10_15:6; - uint64_t cam:1; - uint64_t nbt:1; - uint64_t index:1; - uint64_t fidx:1; - uint64_t nbr1:1; - uint64_t nbr0:1; - uint64_t pend1:1; - uint64_t pend0:1; - uint64_t adr1:1; - uint64_t adr0:1; - } cn56xx; - struct cvmx_pow_bist_stat_cn56xx cn56xxp1; - struct cvmx_pow_bist_stat_cn38xx cn58xx; - struct cvmx_pow_bist_stat_cn38xx cn58xxp1; -}; - -union cvmx_pow_ds_pc { - uint64_t u64; - struct cvmx_pow_ds_pc_s { - uint64_t reserved_32_63:32; - uint64_t ds_pc:32; - } s; - struct cvmx_pow_ds_pc_s cn30xx; - struct cvmx_pow_ds_pc_s cn31xx; - struct cvmx_pow_ds_pc_s cn38xx; - struct cvmx_pow_ds_pc_s cn38xxp2; - struct cvmx_pow_ds_pc_s cn50xx; - struct cvmx_pow_ds_pc_s cn52xx; - struct cvmx_pow_ds_pc_s cn52xxp1; - struct cvmx_pow_ds_pc_s cn56xx; - struct cvmx_pow_ds_pc_s cn56xxp1; - struct cvmx_pow_ds_pc_s cn58xx; - struct cvmx_pow_ds_pc_s cn58xxp1; -}; - -union cvmx_pow_ecc_err { - uint64_t u64; - struct cvmx_pow_ecc_err_s { - uint64_t reserved_45_63:19; - uint64_t iop_ie:13; - uint64_t reserved_29_31:3; - uint64_t iop:13; - uint64_t reserved_14_15:2; - uint64_t rpe_ie:1; - uint64_t rpe:1; - uint64_t reserved_9_11:3; - uint64_t syn:5; - uint64_t dbe_ie:1; - uint64_t sbe_ie:1; - uint64_t dbe:1; - uint64_t sbe:1; - } s; - struct cvmx_pow_ecc_err_s cn30xx; - struct cvmx_pow_ecc_err_cn31xx { - uint64_t reserved_14_63:50; - uint64_t rpe_ie:1; - uint64_t rpe:1; - uint64_t reserved_9_11:3; - uint64_t syn:5; - uint64_t dbe_ie:1; - uint64_t sbe_ie:1; - uint64_t dbe:1; - uint64_t sbe:1; - } cn31xx; - struct cvmx_pow_ecc_err_s cn38xx; - struct cvmx_pow_ecc_err_cn31xx cn38xxp2; - struct cvmx_pow_ecc_err_s cn50xx; - struct cvmx_pow_ecc_err_s cn52xx; - struct cvmx_pow_ecc_err_s cn52xxp1; - struct cvmx_pow_ecc_err_s cn56xx; - struct cvmx_pow_ecc_err_s cn56xxp1; - struct cvmx_pow_ecc_err_s cn58xx; - struct cvmx_pow_ecc_err_s cn58xxp1; -}; - -union cvmx_pow_int_ctl { - uint64_t u64; - struct cvmx_pow_int_ctl_s { - uint64_t reserved_6_63:58; - uint64_t pfr_dis:1; - uint64_t nbr_thr:5; - } s; - struct cvmx_pow_int_ctl_s cn30xx; - struct cvmx_pow_int_ctl_s cn31xx; - struct cvmx_pow_int_ctl_s cn38xx; - struct cvmx_pow_int_ctl_s cn38xxp2; - struct cvmx_pow_int_ctl_s cn50xx; - struct cvmx_pow_int_ctl_s cn52xx; - struct cvmx_pow_int_ctl_s cn52xxp1; - struct cvmx_pow_int_ctl_s cn56xx; - struct cvmx_pow_int_ctl_s cn56xxp1; - struct cvmx_pow_int_ctl_s cn58xx; - struct cvmx_pow_int_ctl_s cn58xxp1; -}; - -union cvmx_pow_iq_cntx { - uint64_t u64; - struct cvmx_pow_iq_cntx_s { - uint64_t reserved_32_63:32; - uint64_t iq_cnt:32; - } s; - struct cvmx_pow_iq_cntx_s cn30xx; - struct cvmx_pow_iq_cntx_s cn31xx; - struct cvmx_pow_iq_cntx_s cn38xx; - struct cvmx_pow_iq_cntx_s cn38xxp2; - struct cvmx_pow_iq_cntx_s cn50xx; - struct cvmx_pow_iq_cntx_s cn52xx; - struct cvmx_pow_iq_cntx_s cn52xxp1; - struct cvmx_pow_iq_cntx_s cn56xx; - struct cvmx_pow_iq_cntx_s cn56xxp1; - struct cvmx_pow_iq_cntx_s cn58xx; - struct cvmx_pow_iq_cntx_s cn58xxp1; -}; - -union cvmx_pow_iq_com_cnt { - uint64_t u64; - struct cvmx_pow_iq_com_cnt_s { - uint64_t reserved_32_63:32; - uint64_t iq_cnt:32; - } s; - struct cvmx_pow_iq_com_cnt_s cn30xx; - struct cvmx_pow_iq_com_cnt_s cn31xx; - struct cvmx_pow_iq_com_cnt_s cn38xx; - struct cvmx_pow_iq_com_cnt_s cn38xxp2; - struct cvmx_pow_iq_com_cnt_s cn50xx; - struct cvmx_pow_iq_com_cnt_s cn52xx; - struct cvmx_pow_iq_com_cnt_s cn52xxp1; - struct cvmx_pow_iq_com_cnt_s cn56xx; - struct cvmx_pow_iq_com_cnt_s cn56xxp1; - struct cvmx_pow_iq_com_cnt_s cn58xx; - struct cvmx_pow_iq_com_cnt_s cn58xxp1; -}; - -union cvmx_pow_iq_int { - uint64_t u64; - struct cvmx_pow_iq_int_s { - uint64_t reserved_8_63:56; - uint64_t iq_int:8; - } s; - struct cvmx_pow_iq_int_s cn52xx; - struct cvmx_pow_iq_int_s cn52xxp1; - struct cvmx_pow_iq_int_s cn56xx; - struct cvmx_pow_iq_int_s cn56xxp1; -}; - -union cvmx_pow_iq_int_en { - uint64_t u64; - struct cvmx_pow_iq_int_en_s { - uint64_t reserved_8_63:56; - uint64_t int_en:8; - } s; - struct cvmx_pow_iq_int_en_s cn52xx; - struct cvmx_pow_iq_int_en_s cn52xxp1; - struct cvmx_pow_iq_int_en_s cn56xx; - struct cvmx_pow_iq_int_en_s cn56xxp1; -}; - -union cvmx_pow_iq_thrx { - uint64_t u64; - struct cvmx_pow_iq_thrx_s { - uint64_t reserved_32_63:32; - uint64_t iq_thr:32; - } s; - struct cvmx_pow_iq_thrx_s cn52xx; - struct cvmx_pow_iq_thrx_s cn52xxp1; - struct cvmx_pow_iq_thrx_s cn56xx; - struct cvmx_pow_iq_thrx_s cn56xxp1; -}; - -union cvmx_pow_nos_cnt { - uint64_t u64; - struct cvmx_pow_nos_cnt_s { - uint64_t reserved_12_63:52; - uint64_t nos_cnt:12; - } s; - struct cvmx_pow_nos_cnt_cn30xx { - uint64_t reserved_7_63:57; - uint64_t nos_cnt:7; - } cn30xx; - struct cvmx_pow_nos_cnt_cn31xx { - uint64_t reserved_9_63:55; - uint64_t nos_cnt:9; - } cn31xx; - struct cvmx_pow_nos_cnt_s cn38xx; - struct cvmx_pow_nos_cnt_s cn38xxp2; - struct cvmx_pow_nos_cnt_cn31xx cn50xx; - struct cvmx_pow_nos_cnt_cn52xx { - uint64_t reserved_10_63:54; - uint64_t nos_cnt:10; - } cn52xx; - struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; - struct cvmx_pow_nos_cnt_s cn56xx; - struct cvmx_pow_nos_cnt_s cn56xxp1; - struct cvmx_pow_nos_cnt_s cn58xx; - struct cvmx_pow_nos_cnt_s cn58xxp1; -}; - -union cvmx_pow_nw_tim { - uint64_t u64; - struct cvmx_pow_nw_tim_s { - uint64_t reserved_10_63:54; - uint64_t nw_tim:10; - } s; - struct cvmx_pow_nw_tim_s cn30xx; - struct cvmx_pow_nw_tim_s cn31xx; - struct cvmx_pow_nw_tim_s cn38xx; - struct cvmx_pow_nw_tim_s cn38xxp2; - struct cvmx_pow_nw_tim_s cn50xx; - struct cvmx_pow_nw_tim_s cn52xx; - struct cvmx_pow_nw_tim_s cn52xxp1; - struct cvmx_pow_nw_tim_s cn56xx; - struct cvmx_pow_nw_tim_s cn56xxp1; - struct cvmx_pow_nw_tim_s cn58xx; - struct cvmx_pow_nw_tim_s cn58xxp1; -}; - -union cvmx_pow_pf_rst_msk { - uint64_t u64; - struct cvmx_pow_pf_rst_msk_s { - uint64_t reserved_8_63:56; - uint64_t rst_msk:8; - } s; - struct cvmx_pow_pf_rst_msk_s cn50xx; - struct cvmx_pow_pf_rst_msk_s cn52xx; - struct cvmx_pow_pf_rst_msk_s cn52xxp1; - struct cvmx_pow_pf_rst_msk_s cn56xx; - struct cvmx_pow_pf_rst_msk_s cn56xxp1; - struct cvmx_pow_pf_rst_msk_s cn58xx; - struct cvmx_pow_pf_rst_msk_s cn58xxp1; -}; - -union cvmx_pow_pp_grp_mskx { - uint64_t u64; - struct cvmx_pow_pp_grp_mskx_s { - uint64_t reserved_48_63:16; - uint64_t qos7_pri:4; - uint64_t qos6_pri:4; - uint64_t qos5_pri:4; - uint64_t qos4_pri:4; - uint64_t qos3_pri:4; - uint64_t qos2_pri:4; - uint64_t qos1_pri:4; - uint64_t qos0_pri:4; - uint64_t grp_msk:16; - } s; - struct cvmx_pow_pp_grp_mskx_cn30xx { - uint64_t reserved_16_63:48; - uint64_t grp_msk:16; - } cn30xx; - struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; - struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; - struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; - struct cvmx_pow_pp_grp_mskx_s cn50xx; - struct cvmx_pow_pp_grp_mskx_s cn52xx; - struct cvmx_pow_pp_grp_mskx_s cn52xxp1; - struct cvmx_pow_pp_grp_mskx_s cn56xx; - struct cvmx_pow_pp_grp_mskx_s cn56xxp1; - struct cvmx_pow_pp_grp_mskx_s cn58xx; - struct cvmx_pow_pp_grp_mskx_s cn58xxp1; -}; - -union cvmx_pow_qos_rndx { - uint64_t u64; - struct cvmx_pow_qos_rndx_s { - uint64_t reserved_32_63:32; - uint64_t rnd_p3:8; - uint64_t rnd_p2:8; - uint64_t rnd_p1:8; - uint64_t rnd:8; - } s; - struct cvmx_pow_qos_rndx_s cn30xx; - struct cvmx_pow_qos_rndx_s cn31xx; - struct cvmx_pow_qos_rndx_s cn38xx; - struct cvmx_pow_qos_rndx_s cn38xxp2; - struct cvmx_pow_qos_rndx_s cn50xx; - struct cvmx_pow_qos_rndx_s cn52xx; - struct cvmx_pow_qos_rndx_s cn52xxp1; - struct cvmx_pow_qos_rndx_s cn56xx; - struct cvmx_pow_qos_rndx_s cn56xxp1; - struct cvmx_pow_qos_rndx_s cn58xx; - struct cvmx_pow_qos_rndx_s cn58xxp1; -}; - -union cvmx_pow_qos_thrx { - uint64_t u64; - struct cvmx_pow_qos_thrx_s { - uint64_t reserved_60_63:4; - uint64_t des_cnt:12; - uint64_t buf_cnt:12; - uint64_t free_cnt:12; - uint64_t reserved_23_23:1; - uint64_t max_thr:11; - uint64_t reserved_11_11:1; - uint64_t min_thr:11; - } s; - struct cvmx_pow_qos_thrx_cn30xx { - uint64_t reserved_55_63:9; - uint64_t des_cnt:7; - uint64_t reserved_43_47:5; - uint64_t buf_cnt:7; - uint64_t reserved_31_35:5; - uint64_t free_cnt:7; - uint64_t reserved_18_23:6; - uint64_t max_thr:6; - uint64_t reserved_6_11:6; - uint64_t min_thr:6; - } cn30xx; - struct cvmx_pow_qos_thrx_cn31xx { - uint64_t reserved_57_63:7; - uint64_t des_cnt:9; - uint64_t reserved_45_47:3; - uint64_t buf_cnt:9; - uint64_t reserved_33_35:3; - uint64_t free_cnt:9; - uint64_t reserved_20_23:4; - uint64_t max_thr:8; - uint64_t reserved_8_11:4; - uint64_t min_thr:8; - } cn31xx; - struct cvmx_pow_qos_thrx_s cn38xx; - struct cvmx_pow_qos_thrx_s cn38xxp2; - struct cvmx_pow_qos_thrx_cn31xx cn50xx; - struct cvmx_pow_qos_thrx_cn52xx { - uint64_t reserved_58_63:6; - uint64_t des_cnt:10; - uint64_t reserved_46_47:2; - uint64_t buf_cnt:10; - uint64_t reserved_34_35:2; - uint64_t free_cnt:10; - uint64_t reserved_21_23:3; - uint64_t max_thr:9; - uint64_t reserved_9_11:3; - uint64_t min_thr:9; - } cn52xx; - struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; - struct cvmx_pow_qos_thrx_s cn56xx; - struct cvmx_pow_qos_thrx_s cn56xxp1; - struct cvmx_pow_qos_thrx_s cn58xx; - struct cvmx_pow_qos_thrx_s cn58xxp1; -}; - -union cvmx_pow_ts_pc { - uint64_t u64; - struct cvmx_pow_ts_pc_s { - uint64_t reserved_32_63:32; - uint64_t ts_pc:32; - } s; - struct cvmx_pow_ts_pc_s cn30xx; - struct cvmx_pow_ts_pc_s cn31xx; - struct cvmx_pow_ts_pc_s cn38xx; - struct cvmx_pow_ts_pc_s cn38xxp2; - struct cvmx_pow_ts_pc_s cn50xx; - struct cvmx_pow_ts_pc_s cn52xx; - struct cvmx_pow_ts_pc_s cn52xxp1; - struct cvmx_pow_ts_pc_s cn56xx; - struct cvmx_pow_ts_pc_s cn56xxp1; - struct cvmx_pow_ts_pc_s cn58xx; - struct cvmx_pow_ts_pc_s cn58xxp1; -}; - -union cvmx_pow_wa_com_pc { - uint64_t u64; - struct cvmx_pow_wa_com_pc_s { - uint64_t reserved_32_63:32; - uint64_t wa_pc:32; - } s; - struct cvmx_pow_wa_com_pc_s cn30xx; - struct cvmx_pow_wa_com_pc_s cn31xx; - struct cvmx_pow_wa_com_pc_s cn38xx; - struct cvmx_pow_wa_com_pc_s cn38xxp2; - struct cvmx_pow_wa_com_pc_s cn50xx; - struct cvmx_pow_wa_com_pc_s cn52xx; - struct cvmx_pow_wa_com_pc_s cn52xxp1; - struct cvmx_pow_wa_com_pc_s cn56xx; - struct cvmx_pow_wa_com_pc_s cn56xxp1; - struct cvmx_pow_wa_com_pc_s cn58xx; - struct cvmx_pow_wa_com_pc_s cn58xxp1; -}; - -union cvmx_pow_wa_pcx { - uint64_t u64; - struct cvmx_pow_wa_pcx_s { - uint64_t reserved_32_63:32; - uint64_t wa_pc:32; - } s; - struct cvmx_pow_wa_pcx_s cn30xx; - struct cvmx_pow_wa_pcx_s cn31xx; - struct cvmx_pow_wa_pcx_s cn38xx; - struct cvmx_pow_wa_pcx_s cn38xxp2; - struct cvmx_pow_wa_pcx_s cn50xx; - struct cvmx_pow_wa_pcx_s cn52xx; - struct cvmx_pow_wa_pcx_s cn52xxp1; - struct cvmx_pow_wa_pcx_s cn56xx; - struct cvmx_pow_wa_pcx_s cn56xxp1; - struct cvmx_pow_wa_pcx_s cn58xx; - struct cvmx_pow_wa_pcx_s cn58xxp1; -}; - -union cvmx_pow_wq_int { - uint64_t u64; - struct cvmx_pow_wq_int_s { - uint64_t reserved_32_63:32; - uint64_t iq_dis:16; - uint64_t wq_int:16; - } s; - struct cvmx_pow_wq_int_s cn30xx; - struct cvmx_pow_wq_int_s cn31xx; - struct cvmx_pow_wq_int_s cn38xx; - struct cvmx_pow_wq_int_s cn38xxp2; - struct cvmx_pow_wq_int_s cn50xx; - struct cvmx_pow_wq_int_s cn52xx; - struct cvmx_pow_wq_int_s cn52xxp1; - struct cvmx_pow_wq_int_s cn56xx; - struct cvmx_pow_wq_int_s cn56xxp1; - struct cvmx_pow_wq_int_s cn58xx; - struct cvmx_pow_wq_int_s cn58xxp1; -}; - -union cvmx_pow_wq_int_cntx { - uint64_t u64; - struct cvmx_pow_wq_int_cntx_s { - uint64_t reserved_28_63:36; - uint64_t tc_cnt:4; - uint64_t ds_cnt:12; - uint64_t iq_cnt:12; - } s; - struct cvmx_pow_wq_int_cntx_cn30xx { - uint64_t reserved_28_63:36; - uint64_t tc_cnt:4; - uint64_t reserved_19_23:5; - uint64_t ds_cnt:7; - uint64_t reserved_7_11:5; - uint64_t iq_cnt:7; - } cn30xx; - struct cvmx_pow_wq_int_cntx_cn31xx { - uint64_t reserved_28_63:36; - uint64_t tc_cnt:4; - uint64_t reserved_21_23:3; - uint64_t ds_cnt:9; - uint64_t reserved_9_11:3; - uint64_t iq_cnt:9; - } cn31xx; - struct cvmx_pow_wq_int_cntx_s cn38xx; - struct cvmx_pow_wq_int_cntx_s cn38xxp2; - struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; - struct cvmx_pow_wq_int_cntx_cn52xx { - uint64_t reserved_28_63:36; - uint64_t tc_cnt:4; - uint64_t reserved_22_23:2; - uint64_t ds_cnt:10; - uint64_t reserved_10_11:2; - uint64_t iq_cnt:10; - } cn52xx; - struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; - struct cvmx_pow_wq_int_cntx_s cn56xx; - struct cvmx_pow_wq_int_cntx_s cn56xxp1; - struct cvmx_pow_wq_int_cntx_s cn58xx; - struct cvmx_pow_wq_int_cntx_s cn58xxp1; -}; - -union cvmx_pow_wq_int_pc { - uint64_t u64; - struct cvmx_pow_wq_int_pc_s { - uint64_t reserved_60_63:4; - uint64_t pc:28; - uint64_t reserved_28_31:4; - uint64_t pc_thr:20; - uint64_t reserved_0_7:8; - } s; - struct cvmx_pow_wq_int_pc_s cn30xx; - struct cvmx_pow_wq_int_pc_s cn31xx; - struct cvmx_pow_wq_int_pc_s cn38xx; - struct cvmx_pow_wq_int_pc_s cn38xxp2; - struct cvmx_pow_wq_int_pc_s cn50xx; - struct cvmx_pow_wq_int_pc_s cn52xx; - struct cvmx_pow_wq_int_pc_s cn52xxp1; - struct cvmx_pow_wq_int_pc_s cn56xx; - struct cvmx_pow_wq_int_pc_s cn56xxp1; - struct cvmx_pow_wq_int_pc_s cn58xx; - struct cvmx_pow_wq_int_pc_s cn58xxp1; -}; - -union cvmx_pow_wq_int_thrx { - uint64_t u64; - struct cvmx_pow_wq_int_thrx_s { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_23_23:1; - uint64_t ds_thr:11; - uint64_t reserved_11_11:1; - uint64_t iq_thr:11; - } s; - struct cvmx_pow_wq_int_thrx_cn30xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_18_23:6; - uint64_t ds_thr:6; - uint64_t reserved_6_11:6; - uint64_t iq_thr:6; - } cn30xx; - struct cvmx_pow_wq_int_thrx_cn31xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_20_23:4; - uint64_t ds_thr:8; - uint64_t reserved_8_11:4; - uint64_t iq_thr:8; - } cn31xx; - struct cvmx_pow_wq_int_thrx_s cn38xx; - struct cvmx_pow_wq_int_thrx_s cn38xxp2; - struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; - struct cvmx_pow_wq_int_thrx_cn52xx { - uint64_t reserved_29_63:35; - uint64_t tc_en:1; - uint64_t tc_thr:4; - uint64_t reserved_21_23:3; - uint64_t ds_thr:9; - uint64_t reserved_9_11:3; - uint64_t iq_thr:9; - } cn52xx; - struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; - struct cvmx_pow_wq_int_thrx_s cn56xx; - struct cvmx_pow_wq_int_thrx_s cn56xxp1; - struct cvmx_pow_wq_int_thrx_s cn58xx; - struct cvmx_pow_wq_int_thrx_s cn58xxp1; -}; - -union cvmx_pow_ws_pcx { - uint64_t u64; - struct cvmx_pow_ws_pcx_s { - uint64_t reserved_32_63:32; - uint64_t ws_pc:32; - } s; - struct cvmx_pow_ws_pcx_s cn30xx; - struct cvmx_pow_ws_pcx_s cn31xx; - struct cvmx_pow_ws_pcx_s cn38xx; - struct cvmx_pow_ws_pcx_s cn38xxp2; - struct cvmx_pow_ws_pcx_s cn50xx; - struct cvmx_pow_ws_pcx_s cn52xx; - struct cvmx_pow_ws_pcx_s cn52xxp1; - struct cvmx_pow_ws_pcx_s cn56xx; - struct cvmx_pow_ws_pcx_s cn56xxp1; - struct cvmx_pow_ws_pcx_s cn58xx; - struct cvmx_pow_ws_pcx_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-spinlock.h b/trunk/arch/mips/include/asm/octeon/cvmx-spinlock.h deleted file mode 100644 index 2fbf0871df11..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-spinlock.h +++ /dev/null @@ -1,232 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * Implementation of spinlocks for Octeon CVMX. Although similar in - * function to Linux kernel spinlocks, they are not compatible. - * Octeon CVMX spinlocks are only used to synchronize with the boot - * monitor and other non-Linux programs running in the system. - */ - -#ifndef __CVMX_SPINLOCK_H__ -#define __CVMX_SPINLOCK_H__ - -#include "cvmx-asm.h" - -/* Spinlocks for Octeon */ - -/* define these to enable recursive spinlock debugging */ -/*#define CVMX_SPINLOCK_DEBUG */ - -/** - * Spinlocks for Octeon CVMX - */ -typedef struct { - volatile uint32_t value; -} cvmx_spinlock_t; - -/* note - macros not expanded in inline ASM, so values hardcoded */ -#define CVMX_SPINLOCK_UNLOCKED_VAL 0 -#define CVMX_SPINLOCK_LOCKED_VAL 1 - -#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL} - -/** - * Initialize a spinlock - * - * @lock: Lock to initialize - */ -static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock) -{ - lock->value = CVMX_SPINLOCK_UNLOCKED_VAL; -} - -/** - * Return non-zero if the spinlock is currently locked - * - * @lock: Lock to check - * Returns Non-zero if locked - */ -static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock) -{ - return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL; -} - -/** - * Releases lock - * - * @lock: pointer to lock structure - */ -static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock) -{ - CVMX_SYNCWS; - lock->value = 0; - CVMX_SYNCWS; -} - -/** - * Attempts to take the lock, but does not spin if lock is not available. - * May take some time to acquire the lock even if it is available - * due to the ll/sc not succeeding. - * - * @lock: pointer to lock structure - * - * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else - * These return values match the Linux semantics. - */ - -static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock) -{ - unsigned int tmp; - - __asm__ __volatile__(".set noreorder \n" - "1: ll %[tmp], %[val] \n" - /* if lock held, fail immediately */ - " bnez %[tmp], 2f \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set reorder \n" : - [val] "+m"(lock->value), [tmp] "=&r"(tmp) - : : "memory"); - - return tmp != 0; /* normalize to 0 or 1 */ -} - -/** - * Gets lock, spins until lock is taken - * - * @lock: pointer to lock structure - */ -static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock) -{ - unsigned int tmp; - - __asm__ __volatile__(".set noreorder \n" - "1: ll %[tmp], %[val] \n" - " bnez %[tmp], 1b \n" - " li %[tmp], 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set reorder \n" : - [val] "+m"(lock->value), [tmp] "=&r"(tmp) - : : "memory"); - -} - -/** ******************************************************************** - * Bit spinlocks - * These spinlocks use a single bit (bit 31) of a 32 bit word for locking. - * The rest of the bits in the word are left undisturbed. This enables more - * compact data structures as only 1 bit is consumed for the lock. - * - */ - -/** - * Gets lock, spins until lock is taken - * Preserves the low 31 bits of the 32 bit - * word used for the lock. - * - * - * @word: word to lock bit 31 of - */ -static inline void cvmx_spinlock_bit_lock(uint32_t *word) -{ - unsigned int tmp; - unsigned int sav; - - __asm__ __volatile__(".set noreorder \n" - ".set noat \n" - "1: ll %[tmp], %[val] \n" - " bbit1 %[tmp], 31, 1b \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " nop \n" - ".set at \n" - ".set reorder \n" : - [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav) - : : "memory"); - -} - -/** - * Attempts to get lock, returns immediately with success/failure - * Preserves the low 31 bits of the 32 bit - * word used for the lock. - * - * - * @word: word to lock bit 31 of - * Returns 0: lock successfully taken - * 1: lock not taken, held by someone else - * These return values match the Linux semantics. - */ -static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word) -{ - unsigned int tmp; - - __asm__ __volatile__(".set noreorder\n\t" - ".set noat\n" - "1: ll %[tmp], %[val] \n" - /* if lock held, fail immediately */ - " bbit1 %[tmp], 31, 2f \n" - " li $at, 1 \n" - " ins %[tmp], $at, 31, 1 \n" - " sc %[tmp], %[val] \n" - " beqz %[tmp], 1b \n" - " li %[tmp], 0 \n" - "2: \n" - ".set at \n" - ".set reorder \n" : - [val] "+m"(*word), [tmp] "=&r"(tmp) - : : "memory"); - - return tmp != 0; /* normalize to 0 or 1 */ -} - -/** - * Releases bit lock - * - * Unconditionally clears bit 31 of the lock word. Note that this is - * done non-atomically, as this implementation assumes that the rest - * of the bits in the word are protected by the lock. - * - * @word: word to unlock bit 31 in - */ -static inline void cvmx_spinlock_bit_unlock(uint32_t *word) -{ - CVMX_SYNCWS; - *word &= ~(1UL << 31); - CVMX_SYNCWS; -} - -#endif /* __CVMX_SPINLOCK_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/trunk/arch/mips/include/asm/octeon/cvmx-sysinfo.h deleted file mode 100644 index 61dd5741afe4..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-sysinfo.h +++ /dev/null @@ -1,152 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * This module provides system/board information obtained by the bootloader. - */ - -#ifndef __CVMX_SYSINFO_H__ -#define __CVMX_SYSINFO_H__ - -#define OCTEON_SERIAL_LEN 20 -/** - * Structure describing application specific information. - * __cvmx_app_init() populates this from the cvmx boot descriptor. - * This structure is private to simple executive applications, so - * no versioning is required. - * - * This structure must be provided with some fields set in order to - * use simple executive functions in other applications (Linux kernel, - * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is - * provided to set the required values in these cases. - */ -struct cvmx_sysinfo { - /* System wide variables */ - /* installed DRAM in system, in bytes */ - uint64_t system_dram_size; - - /* ptr to memory descriptor block */ - void *phy_mem_desc_ptr; - - - /* Application image specific variables */ - /* stack top address (virtual) */ - uint64_t stack_top; - /* heap base address (virtual) */ - uint64_t heap_base; - /* stack size in bytes */ - uint32_t stack_size; - /* heap size in bytes */ - uint32_t heap_size; - /* coremask defining cores running application */ - uint32_t core_mask; - /* Deprecated, use cvmx_coremask_first_core() to select init core */ - uint32_t init_core; - - /* exception base address, as set by bootloader */ - uint64_t exception_base_addr; - - /* cpu clock speed in hz */ - uint32_t cpu_clock_hz; - - /* dram data rate in hz (data rate = 2 * clock rate */ - uint32_t dram_data_rate_hz; - - - uint16_t board_type; - uint8_t board_rev_major; - uint8_t board_rev_minor; - uint8_t mac_addr_base[6]; - uint8_t mac_addr_count; - char board_serial_number[OCTEON_SERIAL_LEN]; - /* - * Several boards support compact flash on the Octeon boot - * bus. The CF memory spaces may be mapped to different - * addresses on different boards. These values will be 0 if - * CF is not present. Note that these addresses are physical - * addresses, and it is up to the application to use the - * proper addressing mode (XKPHYS, KSEG0, etc.) - */ - uint64_t compact_flash_common_base_addr; - uint64_t compact_flash_attribute_base_addr; - /* - * Base address of the LED display (as on EBT3000 board) This - * will be 0 if LED display not present. Note that this - * address is a physical address, and it is up to the - * application to use the proper addressing mode (XKPHYS, - * KSEG0, etc.) - */ - uint64_t led_display_base_addr; - /* DFA reference clock in hz (if applicable)*/ - uint32_t dfa_ref_clock_hz; - /* configuration flags from bootloader */ - uint32_t bootloader_config_flags; - - /* Uart number used for console */ - uint8_t console_uart_num; -}; - -/** - * This function returns the system/board information as obtained - * by the bootloader. - * - * - * Returns Pointer to the boot information structure - * - */ - -extern struct cvmx_sysinfo *cvmx_sysinfo_get(void); - -/** - * This function is used in non-simple executive environments (such as - * Linux kernel, u-boot, etc.) to configure the minimal fields that - * are required to use simple executive files directly. - * - * Locking (if required) must be handled outside of this - * function - * - * @phy_mem_desc_ptr: Pointer to global physical memory descriptor - * (bootmem descriptor) @board_type: Octeon board - * type enumeration - * - * @board_rev_major: - * Board major revision - * @board_rev_minor: - * Board minor revision - * @cpu_clock_hz: - * CPU clock freqency in hertz - * - * Returns 0: Failure - * 1: success - */ -extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, - uint16_t board_type, - uint8_t board_rev_major, - uint8_t board_rev_minor, - uint32_t cpu_clock_hz); - -#endif /* __CVMX_SYSINFO_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx.h b/trunk/arch/mips/include/asm/octeon/cvmx.h deleted file mode 100644 index 03fddfa3e928..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx.h +++ /dev/null @@ -1,505 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_H__ -#define __CVMX_H__ - -#include -#include - -#include "cvmx-asm.h" -#include "cvmx-packet.h" -#include "cvmx-sysinfo.h" - -#include "cvmx-ciu-defs.h" -#include "cvmx-gpio-defs.h" -#include "cvmx-iob-defs.h" -#include "cvmx-ipd-defs.h" -#include "cvmx-l2c-defs.h" -#include "cvmx-l2d-defs.h" -#include "cvmx-l2t-defs.h" -#include "cvmx-led-defs.h" -#include "cvmx-mio-defs.h" -#include "cvmx-pow-defs.h" - -#include "cvmx-bootinfo.h" -#include "cvmx-bootmem.h" -#include "cvmx-l2c.h" - -#ifndef CVMX_ENABLE_DEBUG_PRINTS -#define CVMX_ENABLE_DEBUG_PRINTS 1 -#endif - -#if CVMX_ENABLE_DEBUG_PRINTS -#define cvmx_dprintf printk -#else -#define cvmx_dprintf(...) {} -#endif - -#define CVMX_MAX_CORES (16) -#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ -#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ -#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) -#define CAST64(v) ((long long)(long)(v)) -#define CASTPTR(type, v) ((type *)(long)(v)) - -/* - * Returns processor ID, different Linux and simple exec versions - * provided in the cvmx-app-init*.c files. - */ -static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); -static inline uint32_t cvmx_get_proc_id(void) -{ - uint32_t id; - asm("mfc0 %0, $15,0" : "=r"(id)); - return id; -} - -/* turn the variable name into a string */ -#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x) -#define CVMX_TMP_STR2(x) #x - -/** - * Builds a bit mask given the required size in bits. - * - * @bits: Number of bits in the mask - * Returns The mask - */ static inline uint64_t cvmx_build_mask(uint64_t bits) -{ - return ~((~0x0ull) << bits); -} - -/** - * Builds a memory address for I/O based on the Major and Sub DID. - * - * @major_did: 5 bit major did - * @sub_did: 3 bit sub did - * Returns I/O base address - */ -static inline uint64_t cvmx_build_io_address(uint64_t major_did, - uint64_t sub_did) -{ - return (0x1ull << 48) | (major_did << 43) | (sub_did << 40); -} - -/** - * Perform mask and shift to place the supplied value into - * the supplied bit rage. - * - * Example: cvmx_build_bits(39,24,value) - * 
- * 6       5       4       3       3       2       1
- * 3       5       7       9       1       3       5       7      0
- * +-------+-------+-------+-------+-------+-------+-------+------+
- * 000000000000000000000000___________value000000000000000000000000
- *
- * - * @high_bit: Highest bit value can occupy (inclusive) 0-63 - * @low_bit: Lowest bit value can occupy inclusive 0-high_bit - * @value: Value to use - * Returns Value masked and shifted - */ -static inline uint64_t cvmx_build_bits(uint64_t high_bit, - uint64_t low_bit, uint64_t value) -{ - return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; -} - -enum cvmx_mips_space { - CVMX_MIPS_SPACE_XKSEG = 3LL, - CVMX_MIPS_SPACE_XKPHYS = 2LL, - CVMX_MIPS_SPACE_XSSEG = 1LL, - CVMX_MIPS_SPACE_XUSEG = 0LL -}; - -/* These macros for use when using 32 bit pointers. */ -#define CVMX_MIPS32_SPACE_KSEG0 1l -#define CVMX_ADD_SEG32(segment, add) \ - (((int32_t)segment << 31) | (int32_t)(add)) - -#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS - -/* These macros simplify the process of creating common IO addresses */ -#define CVMX_ADD_SEG(segment, add) \ - ((((uint64_t)segment) << 62) | (add)) -#ifndef CVMX_ADD_IO_SEG -#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) -#endif - -/** - * Convert a memory pointer (void*) into a hardware compatable - * memory address (uint64_t). Octeon hardware widgets don't - * understand logical addresses. - * - * @ptr: C style memory pointer - * Returns Hardware physical address - */ -static inline uint64_t cvmx_ptr_to_phys(void *ptr) -{ - if (sizeof(void *) == 8) { - /* - * We're running in 64 bit mode. Normally this means - * that we can use 40 bits of address space (the - * hardware limit). Unfortunately there is one case - * were we need to limit this to 30 bits, sign - * extended 32 bit. Although these are 64 bits wide, - * only 30 bits can be used. - */ - if ((CAST64(ptr) >> 62) == 3) - return CAST64(ptr) & cvmx_build_mask(30); - else - return CAST64(ptr) & cvmx_build_mask(40); - } else { - return (long)(ptr) & 0x1fffffff; - } -} - -/** - * Convert a hardware physical address (uint64_t) into a - * memory pointer (void *). - * - * @physical_address: - * Hardware physical address to memory - * Returns Pointer to memory - */ -static inline void *cvmx_phys_to_ptr(uint64_t physical_address) -{ - if (sizeof(void *) == 8) { - /* Just set the top bit, avoiding any TLB uglyness */ - return CASTPTR(void, - CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, - physical_address)); - } else { - return CASTPTR(void, - CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, - physical_address)); - } -} - -/* The following #if controls the definition of the macro - CVMX_BUILD_WRITE64. This macro is used to build a store operation to - a full 64bit address. With a 64bit ABI, this can be done with a simple - pointer access. 32bit ABIs require more complicated assembly */ - -/* We have a full 64bit ABI. Writing to a 64bit address can be done with - a simple volatile pointer */ -#define CVMX_BUILD_WRITE64(TYPE, ST) \ -static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ -{ \ - *CASTPTR(volatile TYPE##_t, addr) = val; \ -} - - -/* The following #if controls the definition of the macro - CVMX_BUILD_READ64. This macro is used to build a load operation from - a full 64bit address. With a 64bit ABI, this can be done with a simple - pointer access. 32bit ABIs require more complicated assembly */ - -/* We have a full 64bit ABI. Writing to a 64bit address can be done with - a simple volatile pointer */ -#define CVMX_BUILD_READ64(TYPE, LT) \ -static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ -{ \ - return *CASTPTR(volatile TYPE##_t, addr); \ -} - - -/* The following defines 8 functions for writing to a 64bit address. Each - takes two arguments, the address and the value to write. - cvmx_write64_int64 cvmx_write64_uint64 - cvmx_write64_int32 cvmx_write64_uint32 - cvmx_write64_int16 cvmx_write64_uint16 - cvmx_write64_int8 cvmx_write64_uint8 */ -CVMX_BUILD_WRITE64(int64, "sd"); -CVMX_BUILD_WRITE64(int32, "sw"); -CVMX_BUILD_WRITE64(int16, "sh"); -CVMX_BUILD_WRITE64(int8, "sb"); -CVMX_BUILD_WRITE64(uint64, "sd"); -CVMX_BUILD_WRITE64(uint32, "sw"); -CVMX_BUILD_WRITE64(uint16, "sh"); -CVMX_BUILD_WRITE64(uint8, "sb"); -#define cvmx_write64 cvmx_write64_uint64 - -/* The following defines 8 functions for reading from a 64bit address. Each - takes the address as the only argument - cvmx_read64_int64 cvmx_read64_uint64 - cvmx_read64_int32 cvmx_read64_uint32 - cvmx_read64_int16 cvmx_read64_uint16 - cvmx_read64_int8 cvmx_read64_uint8 */ -CVMX_BUILD_READ64(int64, "ld"); -CVMX_BUILD_READ64(int32, "lw"); -CVMX_BUILD_READ64(int16, "lh"); -CVMX_BUILD_READ64(int8, "lb"); -CVMX_BUILD_READ64(uint64, "ld"); -CVMX_BUILD_READ64(uint32, "lw"); -CVMX_BUILD_READ64(uint16, "lhu"); -CVMX_BUILD_READ64(uint8, "lbu"); -#define cvmx_read64 cvmx_read64_uint64 - - -static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) -{ - cvmx_write64(csr_addr, val); - - /* - * Perform an immediate read after every write to an RSL - * register to force the write to complete. It doesn't matter - * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT - * because it is fast and harmless. - */ - if ((csr_addr >> 40) == (0x800118)) - cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); -} - -static inline void cvmx_write_io(uint64_t io_addr, uint64_t val) -{ - cvmx_write64(io_addr, val); - -} - -static inline uint64_t cvmx_read_csr(uint64_t csr_addr) -{ - uint64_t val = cvmx_read64(csr_addr); - return val; -} - - -static inline void cvmx_send_single(uint64_t data) -{ - const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull; - cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data); -} - -static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) -{ - union { - uint64_t u64; - struct { - uint64_t scraddr:8; - uint64_t len:8; - uint64_t addr:48; - } s; - } addr; - addr.u64 = csr_addr; - addr.s.scraddr = scraddr >> 3; - addr.s.len = 1; - cvmx_send_single(addr.u64); -} - -/* Return true if Octeon is CN38XX pass 1 */ -static inline int cvmx_octeon_is_pass1(void) -{ -#if OCTEON_IS_COMMON_BINARY() - return 0; /* Pass 1 isn't supported for common binaries */ -#else -/* Now that we know we're built for a specific model, only check CN38XX */ -#if OCTEON_IS_MODEL(OCTEON_CN38XX) - return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1; -#else - return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */ -#endif -#endif -} - -static inline unsigned int cvmx_get_core_num(void) -{ - unsigned int core_num; - CVMX_RDHWRNV(core_num, 0); - return core_num; -} - -/** - * Returns the number of bits set in the provided value. - * Simple wrapper for POP instruction. - * - * @val: 32 bit value to count set bits in - * - * Returns Number of bits set - */ -static inline uint32_t cvmx_pop(uint32_t val) -{ - uint32_t pop; - CVMX_POP(pop, val); - return pop; -} - -/** - * Returns the number of bits set in the provided value. - * Simple wrapper for DPOP instruction. - * - * @val: 64 bit value to count set bits in - * - * Returns Number of bits set - */ -static inline int cvmx_dpop(uint64_t val) -{ - int pop; - CVMX_DPOP(pop, val); - return pop; -} - -/** - * Provide current cycle counter as a return value - * - * Returns current cycle counter - */ - -static inline uint64_t cvmx_get_cycle(void) -{ - uint64_t cycle; - CVMX_RDHWR(cycle, 31); - return cycle; -} - -/** - * Reads a chip global cycle counter. This counts CPU cycles since - * chip reset. The counter is 64 bit. - * This register does not exist on CN38XX pass 1 silicion - * - * Returns Global chip cycle count since chip reset. - */ -static inline uint64_t cvmx_get_cycle_global(void) -{ - if (cvmx_octeon_is_pass1()) - return 0; - else - return cvmx_read64(CVMX_IPD_CLK_COUNT); -} - -/** - * This macro spins on a field waiting for it to reach a value. It - * is common in code to need to wait for a specific field in a CSR - * to match a specific value. Conceptually this macro expands to: - * - * 1) read csr at "address" with a csr typedef of "type" - * 2) Check if ("type".s."field" "op" "value") - * 3) If #2 isn't true loop to #1 unless too much time has passed. - */ -#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\ - ( \ -{ \ - int result; \ - do { \ - uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \ - cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \ - type c; \ - while (1) { \ - c.u64 = cvmx_read_csr(address); \ - if ((c.s.field) op(value)) { \ - result = 0; \ - break; \ - } else if (cvmx_get_cycle() > done) { \ - result = -1; \ - break; \ - } else \ - cvmx_wait(100); \ - } \ - } while (0); \ - result; \ -}) - -/***************************************************************************/ - -static inline void cvmx_reset_octeon(void) -{ - union cvmx_ciu_soft_rst ciu_soft_rst; - ciu_soft_rst.u64 = 0; - ciu_soft_rst.s.soft_rst = 1; - cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64); -} - -/* Return the number of cores available in the chip */ -static inline uint32_t cvmx_octeon_num_cores(void) -{ - uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff; - return cvmx_pop(ciu_fuse); -} - -/** - * Read a byte of fuse data - * @byte_addr: address to read - * - * Returns fuse value: 0 or 1 - */ -static uint8_t cvmx_fuse_read_byte(int byte_addr) -{ - union cvmx_mio_fus_rcmd read_cmd; - - read_cmd.u64 = 0; - read_cmd.s.addr = byte_addr; - read_cmd.s.pend = 1; - cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64); - while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) - && read_cmd.s.pend) - ; - return read_cmd.s.dat; -} - -/** - * Read a single fuse bit - * - * @fuse: Fuse number (0-1024) - * - * Returns fuse value: 0 or 1 - */ -static inline int cvmx_fuse_read(int fuse) -{ - return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1; -} - -static inline int cvmx_octeon_model_CN36XX(void) -{ - return OCTEON_IS_MODEL(OCTEON_CN38XX) - && !cvmx_octeon_is_pass1() - && cvmx_fuse_read(264); -} - -static inline int cvmx_octeon_zip_present(void) -{ - return octeon_has_feature(OCTEON_FEATURE_ZIP); -} - -static inline int cvmx_octeon_dfa_present(void) -{ - if (!OCTEON_IS_MODEL(OCTEON_CN38XX) - && !OCTEON_IS_MODEL(OCTEON_CN31XX) - && !OCTEON_IS_MODEL(OCTEON_CN58XX)) - return 0; - else if (OCTEON_IS_MODEL(OCTEON_CN3020)) - return 0; - else if (cvmx_octeon_is_pass1()) - return 1; - else - return !cvmx_fuse_read(120); -} - -static inline int cvmx_octeon_crypto_present(void) -{ - return octeon_has_feature(OCTEON_FEATURE_CRYPTO); -} - -#endif /* __CVMX_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/octeon-feature.h b/trunk/arch/mips/include/asm/octeon/octeon-feature.h deleted file mode 100644 index 04fac684069c..000000000000 --- a/trunk/arch/mips/include/asm/octeon/octeon-feature.h +++ /dev/null @@ -1,119 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * File defining checks for different Octeon features. - */ - -#ifndef __OCTEON_FEATURE_H__ -#define __OCTEON_FEATURE_H__ - -enum octeon_feature { - /* - * Octeon models in the CN5XXX family and higher support - * atomic add instructions to memory (saa/saad). - */ - OCTEON_FEATURE_SAAD, - /* Does this Octeon support the ZIP offload engine? */ - OCTEON_FEATURE_ZIP, - /* Does this Octeon support crypto acceleration using COP2? */ - OCTEON_FEATURE_CRYPTO, - /* Does this Octeon support PCI express? */ - OCTEON_FEATURE_PCIE, - /* Some Octeon models support internal memory for storing - * cryptographic keys */ - OCTEON_FEATURE_KEY_MEMORY, - /* Octeon has a LED controller for banks of external LEDs */ - OCTEON_FEATURE_LED_CONTROLLER, - /* Octeon has a trace buffer */ - OCTEON_FEATURE_TRA, - /* Octeon has a management port */ - OCTEON_FEATURE_MGMT_PORT, - /* Octeon has a raid unit */ - OCTEON_FEATURE_RAID, - /* Octeon has a builtin USB */ - OCTEON_FEATURE_USB, -}; - -static inline int cvmx_fuse_read(int fuse); - -/** - * Determine if the current Octeon supports a specific feature. These - * checks have been optimized to be fairly quick, but they should still - * be kept out of fast path code. - * - * @feature: Feature to check for. This should always be a constant so the - * compiler can remove the switch statement through optimization. - * - * Returns Non zero if the feature exists. Zero if the feature does not - * exist. - */ -static inline int octeon_has_feature(enum octeon_feature feature) -{ - switch (feature) { - case OCTEON_FEATURE_SAAD: - return !OCTEON_IS_MODEL(OCTEON_CN3XXX); - - case OCTEON_FEATURE_ZIP: - if (OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) - return 1; - else - return !cvmx_fuse_read(121); - - case OCTEON_FEATURE_CRYPTO: - return !cvmx_fuse_read(90); - - case OCTEON_FEATURE_PCIE: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); - - case OCTEON_FEATURE_KEY_MEMORY: - case OCTEON_FEATURE_LED_CONTROLLER: - return OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX) - || OCTEON_IS_MODEL(OCTEON_CN56XX); - case OCTEON_FEATURE_TRA: - return !(OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)); - case OCTEON_FEATURE_MGMT_PORT: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); - case OCTEON_FEATURE_RAID: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); - case OCTEON_FEATURE_USB: - return !(OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)); - } - return 0; -} - -#endif /* __OCTEON_FEATURE_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/octeon-model.h b/trunk/arch/mips/include/asm/octeon/octeon-model.h deleted file mode 100644 index cf50336eca2e..000000000000 --- a/trunk/arch/mips/include/asm/octeon/octeon-model.h +++ /dev/null @@ -1,321 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * File defining different Octeon model IDs and macros to - * compare them. - * - */ - -#ifndef __OCTEON_MODEL_H__ -#define __OCTEON_MODEL_H__ - -/* NOTE: These must match what is checked in common-config.mk */ -/* Defines to represent the different versions of Octeon. */ - -/* - * IMPORTANT: When the default pass is updated for an Octeon Model, - * the corresponding change must also be made in the oct-sim script. - */ - -/* - * The defines below should be used with the OCTEON_IS_MODEL() macro - * to determine what model of chip the software is running on. Models - * ending in 'XX' match multiple models (families), while specific - * models match only that model. If a pass (revision) is specified, - * then only that revision will be matched. Care should be taken when - * checking for both specific models and families that the specific - * models are checked for first. While these defines are similar to - * the processor ID, they are not intended to be used by anything - * other that the OCTEON_IS_MODEL framework, and the values are - * subject to change at anytime without notice. - * - * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN* - * macros should be used outside of this file. All other macros are - * for internal use only, and may change without notice. - */ - -/* Flag bits in top byte */ -/* Ignores revision in model checks */ -#define OM_IGNORE_REVISION 0x01000000 -/* Check submodels */ -#define OM_CHECK_SUBMODEL 0x02000000 -/* Match all models previous than the one specified */ -#define OM_MATCH_PREVIOUS_MODELS 0x04000000 -/* Ignores the minor revison on newer parts */ -#define OM_IGNORE_MINOR_REVISION 0x08000000 -#define OM_FLAG_MASK 0xff000000 - -/* - * CN5XXX models with new revision encoding - */ -#define OCTEON_CN58XX_PASS1_0 0x000d0300 -#define OCTEON_CN58XX_PASS1_1 0x000d0301 -#define OCTEON_CN58XX_PASS1_2 0x000d0303 -#define OCTEON_CN58XX_PASS2_0 0x000d0308 -#define OCTEON_CN58XX_PASS2_1 0x000d0309 -#define OCTEON_CN58XX_PASS2_2 0x000d030a -#define OCTEON_CN58XX_PASS2_3 0x000d030b - -#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X -#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X - -#define OCTEON_CN56XX_PASS1_0 0x000d0400 -#define OCTEON_CN56XX_PASS1_1 0x000d0401 -#define OCTEON_CN56XX_PASS2_0 0x000d0408 -#define OCTEON_CN56XX_PASS2_1 0x000d0409 - -#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X -#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X - -#define OCTEON_CN57XX OCTEON_CN56XX -#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN55XX OCTEON_CN56XX -#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN54XX OCTEON_CN56XX -#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1 -#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2 - -#define OCTEON_CN50XX_PASS1_0 0x000d0600 - -#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) -#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X - -/* - * NOTE: Octeon CN5000F model is not identifiable using the - * OCTEON_IS_MODEL() functions, but are treated as CN50XX. - */ - -#define OCTEON_CN52XX_PASS1_0 0x000d0700 -#define OCTEON_CN52XX_PASS2_0 0x000d0708 - -#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) -#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \ - | OM_IGNORE_MINOR_REVISION) -#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X -#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X - -/* - * CN3XXX models with old revision enconding - */ -#define OCTEON_CN38XX_PASS1 0x000d0000 -#define OCTEON_CN38XX_PASS2 0x000d0001 -#define OCTEON_CN38XX_PASS3 0x000d0003 -#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION) - -#define OCTEON_CN36XX OCTEON_CN38XX -#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2 -#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3 - -/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */ -#define OCTEON_CN31XX_PASS1 0x000d0100 -#define OCTEON_CN31XX_PASS1_1 0x000d0102 -#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION) - -/* - * This model is only used for internal checks, it is not a valid - * model for the OCTEON_MODEL environment variable. This matches the - * CN3010 and CN3005 but NOT the CN3020. - */ -#define OCTEON_CN30XX_PASS1 0x000d0200 -#define OCTEON_CN30XX_PASS1_1 0x000d0202 -#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION) - -#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) - -#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) - -#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) -#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ - | OM_CHECK_SUBMODEL) - - - -/* This matches the complete family of CN3xxx CPUs, and not subsequent models */ -#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \ - | OM_MATCH_PREVIOUS_MODELS \ - | OM_IGNORE_REVISION) - -/* The revision byte (low byte) has two different encodings. - * CN3XXX: - * - * bits - * <7:5>: reserved (0) - * <4>: alternate package - * <3:0>: revision - * - * CN5XXX: - * - * bits - * <7>: reserved (0) - * <6>: alternate package - * <5:3>: major revision - * <2:0>: minor revision - * - */ - -/* Masks used for the various types of model/family/revision matching */ -#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 -#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f -#define OCTEON_38XX_MODEL_MASK 0x00ffff10 -#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ - | OCTEON_38XX_MODEL_MASK) - -/* CN5XXX and later use different layout of bits in the revision ID field */ -#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK -#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f -#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 -#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ - | OCTEON_58XX_MODEL_MASK) -#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \ - & 0x00fffff8) - -#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z))) - -/* NOTE: This is for internal (to this file) use only. */ -static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model, - uint32_t chip_model) -{ - uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL; - - if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) { - if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_MODEL_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == 0) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_FAMILY_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && - __OCTEON_MATCH_MASK__(chip_model, arg_model, - OCTEON_38XX_FAMILY_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_38XX_MODEL_REV_MASK)) - return 1; - if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && - ((chip_model & OCTEON_38XX_MODEL_MASK) < - (arg_model & OCTEON_38XX_MODEL_MASK))) - return 1; - } else { - if (((arg_model & OM_FLAG_MASK) == rev_and_sub) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == 0) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_FAMILY_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_MINOR_REV_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_FAMILY_MASK)) - return 1; - if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) && - __OCTEON_MATCH_MASK__((chip_model), (arg_model), - OCTEON_58XX_MODEL_REV_MASK)) - return 1; - if ((arg_model & OM_MATCH_PREVIOUS_MODELS) && - ((chip_model & OCTEON_58XX_MODEL_MASK) < - (arg_model & OCTEON_58XX_MODEL_MASK))) - return 1; - } - return 0; -} - -/* forward declarations */ -static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); -static inline uint64_t cvmx_read_csr(uint64_t csr_addr); - -/* NOTE: This for internal use only!!!!! */ -static inline int __octeon_is_model_runtime__(uint32_t model) -{ - uint32_t cpuid = cvmx_get_proc_id(); - - /* - * Check for special case of mismarked 3005 samples. We only - * need to check if the sub model isn't being ignored. - */ - if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { - if (cpuid == OCTEON_CN3010_PASS1 \ - && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34))) - cpuid |= 0x10; - } - return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); -} - -/* - * The OCTEON_IS_MODEL macro should be used for all Octeon model - * checking done in a program. This should be kept runtime if at all - * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be - * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking - * support is required. - */ -#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) -#define OCTEON_IS_COMMON_BINARY() 1 -#undef OCTEON_MODEL - -const char *octeon_model_get_string(uint32_t chip_id); -const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); - -#include "octeon-feature.h" - -#endif /* __OCTEON_MODEL_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h deleted file mode 100644 index edc676084cda..000000000000 --- a/trunk/arch/mips/include/asm/octeon/octeon.h +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004-2008 Cavium Networks - */ -#ifndef __ASM_OCTEON_OCTEON_H -#define __ASM_OCTEON_OCTEON_H - -#include "cvmx.h" - -extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, - uint64_t alignment, - uint64_t min_addr, - uint64_t max_addr, - int do_locking); -extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, - int do_locking); -extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, - uint64_t min_addr, uint64_t max_addr, - int do_locking); -extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, - char *name); -extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, - uint64_t max_addr, uint64_t align, - char *name); -extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, - char *name); -extern int octeon_bootmem_free_named(char *name); -extern void octeon_bootmem_lock(void); -extern void octeon_bootmem_unlock(void); - -extern int octeon_is_simulation(void); -extern int octeon_is_pci_host(void); -extern int octeon_usb_is_ref_clk(void); -extern uint64_t octeon_get_clock_rate(void); -extern const char *octeon_board_type_string(void); -extern const char *octeon_get_pci_interrupts(void); -extern int octeon_get_southbridge_interrupt(void); -extern int octeon_get_boot_coremask(void); -extern int octeon_get_boot_num_arguments(void); -extern const char *octeon_get_boot_argument(int arg); -extern void octeon_hal_setup_reserved32(void); -extern void octeon_user_io_init(void); -struct octeon_cop2_state; -extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); -extern void octeon_crypto_disable(struct octeon_cop2_state *state, - unsigned long flags); - -extern void octeon_init_cvmcount(void); - -#define OCTEON_ARGV_MAX_ARGS 64 -#define OCTOEN_SERIAL_LEN 20 - -struct octeon_boot_descriptor { - /* Start of block referenced by assembly code - do not change! */ - uint32_t desc_version; - uint32_t desc_size; - uint64_t stack_top; - uint64_t heap_base; - uint64_t heap_end; - /* Only used by bootloader */ - uint64_t entry_point; - uint64_t desc_vaddr; - /* End of This block referenced by assembly code - do not change! */ - uint32_t exception_base_addr; - uint32_t stack_size; - uint32_t heap_size; - /* Argc count for application. */ - uint32_t argc; - uint32_t argv[OCTEON_ARGV_MAX_ARGS]; - -#define BOOT_FLAG_INIT_CORE (1 << 0) -#define OCTEON_BL_FLAG_DEBUG (1 << 1) -#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) - /* If set, use uart1 for console */ -#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) - /* If set, use PCI console */ -#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) - /* Call exit on break on serial port */ -#define OCTEON_BL_FLAG_BREAK (1 << 5) - - uint32_t flags; - uint32_t core_mask; - /* DRAM size in megabyes. */ - uint32_t dram_size; - /* physical address of free memory descriptor block. */ - uint32_t phy_mem_desc_addr; - /* used to pass flags from app to debugger. */ - uint32_t debugger_flags_base_addr; - /* CPU clock speed, in hz. */ - uint32_t eclock_hz; - /* DRAM clock speed, in hz. */ - uint32_t dclock_hz; - /* SPI4 clock in hz. */ - uint32_t spi_clock_hz; - uint16_t board_type; - uint8_t board_rev_major; - uint8_t board_rev_minor; - uint16_t chip_type; - uint8_t chip_rev_major; - uint8_t chip_rev_minor; - char board_serial_number[OCTOEN_SERIAL_LEN]; - uint8_t mac_addr_base[6]; - uint8_t mac_addr_count; - uint64_t cvmx_desc_vaddr; -}; - -union octeon_cvmemctl { - uint64_t u64; - struct { - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t tlbbist:1; - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t l1cbist:1; - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t l1dbist:1; - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t dcmbist:1; - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t ptgbist:1; - /* RO 1 = BIST fail, 0 = BIST pass */ - uint64_t wbfbist:1; - /* Reserved */ - uint64_t reserved:22; - /* R/W If set, marked write-buffer entries time out - * the same as as other entries; if clear, marked - * write-buffer entries use the maximum timeout. */ - uint64_t dismarkwblongto:1; - /* R/W If set, a merged store does not clear the - * write-buffer entry timeout state. */ - uint64_t dismrgclrwbto:1; - /* R/W Two bits that are the MSBs of the resultant - * CVMSEG LM word location for an IOBDMA. The other 8 - * bits come from the SCRADDR field of the IOBDMA. */ - uint64_t iobdmascrmsb:2; - /* R/W If set, SYNCWS and SYNCS only order marked - * stores; if clear, SYNCWS and SYNCS only order - * unmarked stores. SYNCWSMARKED has no effect when - * DISSYNCWS is set. */ - uint64_t syncwsmarked:1; - /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as - * SYNC. */ - uint64_t dissyncws:1; - /* R/W If set, no stall happens on write buffer - * full. */ - uint64_t diswbfst:1; - /* R/W If set (and SX set), supervisor-level - * loads/stores can use XKPHYS addresses with - * VA<48>==0 */ - uint64_t xkmemenas:1; - /* R/W If set (and UX set), user-level loads/stores - * can use XKPHYS addresses with VA<48>==0 */ - uint64_t xkmemenau:1; - /* R/W If set (and SX set), supervisor-level - * loads/stores can use XKPHYS addresses with - * VA<48>==1 */ - uint64_t xkioenas:1; - /* R/W If set (and UX set), user-level loads/stores - * can use XKPHYS addresses with VA<48>==1 */ - uint64_t xkioenau:1; - /* R/W If set, all stores act as SYNCW (NOMERGE must - * be set when this is set) RW, reset to 0. */ - uint64_t allsyncw:1; - /* R/W If set, no stores merge, and all stores reach - * the coherent bus in order. */ - uint64_t nomerge:1; - /* R/W Selects the bit in the counter used for DID - * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = - * 214. Actual time-out is between 1x and 2x this - * interval. For example, with DIDTTO=3, expiration - * interval is between 16K and 32K. */ - uint64_t didtto:2; - /* R/W If set, the (mem) CSR clock never turns off. */ - uint64_t csrckalwys:1; - /* R/W If set, mclk never turns off. */ - uint64_t mclkalwys:1; - /* R/W Selects the bit in the counter used for write - * buffer flush time-outs (WBFLT+11) is the bit - * position in an internal counter used to determine - * expiration. The write buffer expires between 1x and - * 2x this interval. For example, with WBFLT = 0, a - * write buffer expires between 2K and 4K cycles after - * the write buffer entry is allocated. */ - uint64_t wbfltime:3; - /* R/W If set, do not put Istream in the L2 cache. */ - uint64_t istrnol2:1; - /* R/W The write buffer threshold. */ - uint64_t wbthresh:4; - /* Reserved */ - uint64_t reserved2:2; - /* R/W If set, CVMSEG is available for loads/stores in - * kernel/debug mode. */ - uint64_t cvmsegenak:1; - /* R/W If set, CVMSEG is available for loads/stores in - * supervisor mode. */ - uint64_t cvmsegenas:1; - /* R/W If set, CVMSEG is available for loads/stores in - * user mode. */ - uint64_t cvmsegenau:1; - /* R/W Size of local memory in cache blocks, 54 (6912 - * bytes) is max legal value. */ - uint64_t lmemsz:6; - } s; -}; - -struct octeon_cf_data { - unsigned long base_region_bias; - unsigned int base_region; /* The chip select region used by CF */ - int is16bit; /* 0 - 8bit, !0 - 16bit */ - int dma_engine; /* -1 for no DMA */ -}; - -extern void octeon_write_lcd(const char *s); -extern void octeon_check_cpu_bist(void); -extern int octeon_get_boot_debug_flag(void); -extern int octeon_get_boot_uart(void); - -struct uart_port; -extern unsigned int octeon_serial_in(struct uart_port *, int); -extern void octeon_serial_out(struct uart_port *, int, int); - -/** - * Write a 32bit value to the Octeon NPI register space - * - * @address: Address to write to - * @val: Value to write - */ -static inline void octeon_npi_write32(uint64_t address, uint32_t val) -{ - cvmx_write64_uint32(address ^ 4, val); - cvmx_read64_uint32(address ^ 4); -} - - -/** - * Read a 32bit value from the Octeon NPI register space - * - * @address: Address to read - * Returns The result - */ -static inline uint32_t octeon_npi_read32(uint64_t address) -{ - return cvmx_read64_uint32(address ^ 4); -} - -#endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/trunk/arch/mips/include/asm/processor.h b/trunk/arch/mips/include/asm/processor.h index 0f926aa0cb47..18ee58e39445 100644 --- a/trunk/arch/mips/include/asm/processor.h +++ b/trunk/arch/mips/include/asm/processor.h @@ -118,60 +118,6 @@ union mips_watch_reg_state { struct mips3264_watch_reg_state mips3264; }; -#ifdef CONFIG_CPU_CAVIUM_OCTEON - -struct octeon_cop2_state { - /* DMFC2 rt, 0x0201 */ - unsigned long cop2_crc_iv; - /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ - unsigned long cop2_crc_length; - /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ - unsigned long cop2_crc_poly; - /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ - unsigned long cop2_llm_dat[2]; - /* DMFC2 rt, 0x0084 */ - unsigned long cop2_3des_iv; - /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ - unsigned long cop2_3des_key[3]; - /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ - unsigned long cop2_3des_result; - /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ - unsigned long cop2_aes_inp0; - /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ - unsigned long cop2_aes_iv[2]; - /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 - * rt, 0x0107 */ - unsigned long cop2_aes_key[4]; - /* DMFC2 rt, 0x0110 */ - unsigned long cop2_aes_keylen; - /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ - unsigned long cop2_aes_result[2]; - /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 - * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, - * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, - * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, - * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ - unsigned long cop2_hsh_datw[15]; - /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 - * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, - * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ - unsigned long cop2_hsh_ivw[8]; - /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ - unsigned long cop2_gfm_mult[2]; - /* DMFC2 rt, 0x025E - Pass2 */ - unsigned long cop2_gfm_poly; - /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ - unsigned long cop2_gfm_result[2]; -}; -#define INIT_OCTEON_COP2 {0,} - -struct octeon_cvmseg_state { - unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] - [cpu_dcache_line_size() / sizeof(unsigned long)]; -}; - -#endif - typedef struct { unsigned long seg; } mm_segment_t; @@ -214,10 +160,6 @@ struct thread_struct { unsigned long trap_no; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; -#ifdef CONFIG_CPU_CAVIUM_OCTEON - struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); - struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); -#endif struct mips_abi *abi; }; @@ -229,13 +171,6 @@ struct thread_struct { #define FPAFF_INIT #endif /* CONFIG_MIPS_MT_FPAFF */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define OCTEON_INIT \ - .cp2 = INIT_OCTEON_COP2, -#else -#define OCTEON_INIT -#endif /* CONFIG_CPU_CAVIUM_OCTEON */ - #define INIT_THREAD { \ /* \ * Saved main processor registers \ @@ -286,10 +221,6 @@ struct thread_struct { .trap_no = 0, \ .irix_trampoline = 0, \ .irix_oldctx = 0, \ - /* \ - * Cavium Octeon specifics (null if not Octeon) \ - */ \ - OCTEON_INIT \ } struct task_struct; diff --git a/trunk/arch/mips/include/asm/ptrace.h b/trunk/arch/mips/include/asm/ptrace.h index 1f30d16d4669..c2c8bac43307 100644 --- a/trunk/arch/mips/include/asm/ptrace.h +++ b/trunk/arch/mips/include/asm/ptrace.h @@ -48,10 +48,6 @@ struct pt_regs { #ifdef CONFIG_MIPS_MT_SMTC unsigned long cp0_tcstatus; #endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - unsigned long long mpl[3]; /* MTM{0,1,2} */ - unsigned long long mtp[3]; /* MTP{0,1,2} */ -#endif } __attribute__ ((aligned (8))); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ diff --git a/trunk/arch/mips/include/asm/smp.h b/trunk/arch/mips/include/asm/smp.h index 40e5ef1d4d26..86557b5d1b3f 100644 --- a/trunk/arch/mips/include/asm/smp.h +++ b/trunk/arch/mips/include/asm/smp.h @@ -37,9 +37,6 @@ extern int __cpu_logical_map[NR_CPUS]; #define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ #define SMP_CALL_FUNCTION 0x2 -/* Octeon - Tell another core to flush its icache */ -#define SMP_ICACHE_FLUSH 0x4 - extern void asmlinkage smp_bootstrap(void); diff --git a/trunk/arch/mips/include/asm/stackframe.h b/trunk/arch/mips/include/asm/stackframe.h index db0fa7b5aeaf..4c37c4e5f72e 100644 --- a/trunk/arch/mips/include/asm/stackframe.h +++ b/trunk/arch/mips/include/asm/stackframe.h @@ -194,19 +194,6 @@ LONG_S $31, PT_R31(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK -#ifdef CONFIG_CPU_CAVIUM_OCTEON - .set mips64 - pref 0, 0($28) /* Prefetch the current pointer */ - pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ - /* The Octeon multiplier state is affected by general multiply - instructions. It must be saved before and kernel code might - corrupt it */ - jal octeon_mult_save - LONG_L v1, 0($28) /* Load the current pointer */ - /* Restore $31(ra) that was changed by the jal */ - LONG_L ra, PT_R31(sp) - pref 0, 0(v1) /* Prefetch the current thread */ -#endif .set pop .endm @@ -337,10 +324,6 @@ DVPE 5 # dvpe a1 jal mips_ihb #endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - /* Restore the Octeon multiplier state */ - jal octeon_mult_restore -#endif mfc0 a0, CP0_STATUS ori a0, STATMASK xori a0, STATMASK diff --git a/trunk/arch/mips/include/asm/time.h b/trunk/arch/mips/include/asm/time.h index 38a30d2ee959..9601ea950542 100644 --- a/trunk/arch/mips/include/asm/time.h +++ b/trunk/arch/mips/include/asm/time.h @@ -50,35 +50,27 @@ extern int (*perf_irq)(void); /* * Initialize the calling CPU's compare interrupt as clockevent device */ -#ifdef CONFIG_CEVT_R4K_LIB +#ifdef CONFIG_CEVT_R4K +extern int mips_clockevent_init(void); extern unsigned int __weak get_c0_compare_int(void); -extern int r4k_clockevent_init(void); -#endif - +#else static inline int mips_clockevent_init(void) { -#ifdef CONFIG_CEVT_R4K - return r4k_clockevent_init(); -#else return -ENXIO; -#endif } +#endif /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CSRC_R4K_LIB -extern int init_r4k_clocksource(void); -#endif - -static inline int init_mips_clocksource(void) -{ #ifdef CONFIG_CSRC_R4K - return init_r4k_clocksource(); +extern int init_mips_clocksource(void); #else +static inline int init_mips_clocksource(void) +{ return 0; -#endif } +#endif extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); extern void clockevent_set_clock(struct clock_event_device *cd, diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile index e96122159928..b1372c27f136 100644 --- a/trunk/arch/mips/kernel/Makefile +++ b/trunk/arch/mips/kernel/Makefile @@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ time.o topology.o traps.o unaligned.o watch.o obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o -obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o +obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o @@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o -obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o +obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o @@ -43,7 +43,6 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP_UP) += smp-up.o diff --git a/trunk/arch/mips/kernel/asm-offsets.c b/trunk/arch/mips/kernel/asm-offsets.c index c901c22d7ad0..72942226fcdd 100644 --- a/trunk/arch/mips/kernel/asm-offsets.c +++ b/trunk/arch/mips/kernel/asm-offsets.c @@ -64,10 +64,6 @@ void output_ptreg_defines(void) #ifdef CONFIG_MIPS_MT_SMTC OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); #endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON - OFFSET(PT_MPL, pt_regs, mpl); - OFFSET(PT_MTP, pt_regs, mtp); -#endif /* CONFIG_CPU_CAVIUM_OCTEON */ DEFINE(PT_SIZE, sizeof(struct pt_regs)); BLANK(); } @@ -299,30 +295,3 @@ void output_irq_cpustat_t_defines(void) DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); BLANK(); } - -#ifdef CONFIG_CPU_CAVIUM_OCTEON -void output_octeon_cop2_state_defines(void) -{ - COMMENT("Octeon specific octeon_cop2_state offsets."); - OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); - OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); - OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); - OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); - OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); - OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); - OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); - OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); - OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); - OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); - OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); - OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); - OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); - OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); - OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); - OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); - OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); - OFFSET(THREAD_CP2, task_struct, thread.cp2); - OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); - BLANK(); -} -#endif diff --git a/trunk/arch/mips/kernel/branch.c b/trunk/arch/mips/kernel/branch.c index 0176ed015c89..6b5df8bfab85 100644 --- a/trunk/arch/mips/kernel/branch.c +++ b/trunk/arch/mips/kernel/branch.c @@ -205,39 +205,6 @@ int __compute_return_epc(struct pt_regs *regs) break; } break; -#ifdef CONFIG_CPU_CAVIUM_OCTEON - case lwc2_op: /* This is bbit0 on Octeon */ - if ((regs->regs[insn.i_format.rs] & (1ull<cp0_epc = epc; - break; - case ldc2_op: /* This is bbit032 on Octeon */ - if ((regs->regs[insn.i_format.rs] & - (1ull<<(insn.i_format.rt+32))) == 0) - epc = epc + 4 + (insn.i_format.simmediate << 2); - else - epc += 8; - regs->cp0_epc = epc; - break; - case swc2_op: /* This is bbit1 on Octeon */ - if (regs->regs[insn.i_format.rs] & (1ull<cp0_epc = epc; - break; - case sdc2_op: /* This is bbit132 on Octeon */ - if (regs->regs[insn.i_format.rs] & - (1ull<<(insn.i_format.rt+32))) - epc = epc + 4 + (insn.i_format.simmediate << 2); - else - epc += 8; - regs->cp0_epc = epc; - break; -#endif } return 0; diff --git a/trunk/arch/mips/kernel/cevt-r4k.c b/trunk/arch/mips/kernel/cevt-r4k.c index 0015e442572b..e1ec83b68031 100644 --- a/trunk/arch/mips/kernel/cevt-r4k.c +++ b/trunk/arch/mips/kernel/cevt-r4k.c @@ -160,7 +160,7 @@ int c0_compare_int_usable(void) #ifndef CONFIG_MIPS_MT_SMTC -int __cpuinit r4k_clockevent_init(void) +int __cpuinit mips_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index a7162a4484cf..c9207b5fd923 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -96,9 +96,6 @@ int allow_au1k_wait; static void au1k_wait(void) { - if (!allow_au1k_wait) - return; - /* using the wait instruction makes CP0 counter unusable */ __asm__(" .set mips3 \n" " cache 0x14, 0(%0) \n" @@ -157,7 +154,6 @@ void __init check_wait(void) case CPU_25KF: case CPU_PR4450: case CPU_BCM3302: - case CPU_CAVIUM_OCTEON: cpu_wait = r4k_wait; break; @@ -189,7 +185,8 @@ void __init check_wait(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: - cpu_wait = au1k_wait; + if (allow_au1k_wait) + cpu_wait = au1k_wait; break; case CPU_20KC: /* @@ -878,27 +875,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) } } -static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) -{ - decode_configs(c); - switch (c->processor_id & 0xff00) { - case PRID_IMP_CAVIUM_CN38XX: - case PRID_IMP_CAVIUM_CN31XX: - case PRID_IMP_CAVIUM_CN30XX: - case PRID_IMP_CAVIUM_CN58XX: - case PRID_IMP_CAVIUM_CN56XX: - case PRID_IMP_CAVIUM_CN50XX: - case PRID_IMP_CAVIUM_CN52XX: - c->cputype = CPU_CAVIUM_OCTEON; - __cpu_name[cpu] = "Cavium Octeon"; - break; - default: - printk(KERN_INFO "Unknown Octeon chip!\n"); - c->cputype = CPU_UNKNOWN; - break; - } -} - const char *__cpu_name[NR_CPUS]; __cpuinit void cpu_probe(void) @@ -933,9 +909,6 @@ __cpuinit void cpu_probe(void) case PRID_COMP_NXP: cpu_probe_nxp(c, cpu); break; - case PRID_COMP_CAVIUM: - cpu_probe_cavium(c, cpu); - break; } BUG_ON(!__cpu_name[cpu]); diff --git a/trunk/arch/mips/kernel/csrc-r4k.c b/trunk/arch/mips/kernel/csrc-r4k.c index f1a2893931ed..74fb74583b4e 100644 --- a/trunk/arch/mips/kernel/csrc-r4k.c +++ b/trunk/arch/mips/kernel/csrc-r4k.c @@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -int __init init_r4k_clocksource(void) +int __init init_mips_clocksource(void) { if (!cpu_has_counter || !mips_hpt_frequency) return -ENXIO; diff --git a/trunk/arch/mips/kernel/genex.S b/trunk/arch/mips/kernel/genex.S index fb6f73148df2..757d48f0d80f 100644 --- a/trunk/arch/mips/kernel/genex.S +++ b/trunk/arch/mips/kernel/genex.S @@ -385,14 +385,10 @@ NESTED(nmi_handler, PT_SIZE, sp) .endm .macro __build_clear_fpe - .set push - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - .set mips1 cfc1 a1, fcr31 li a2, ~(0x3f << 12) and a2, a1 ctc1 a2, fcr31 - .set pop TRACE_IRQS_ON STI .endm diff --git a/trunk/arch/mips/kernel/irq.c b/trunk/arch/mips/kernel/irq.c index a0ff2b66e22b..4b4007b3083a 100644 --- a/trunk/arch/mips/kernel/irq.c +++ b/trunk/arch/mips/kernel/irq.c @@ -111,7 +111,6 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif seq_printf(p, " %14s", irq_desc[i].chip->name); - seq_printf(p, "-%-8s", irq_desc[i].name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/trunk/arch/mips/kernel/octeon_switch.S b/trunk/arch/mips/kernel/octeon_switch.S deleted file mode 100644 index d52389672b06..000000000000 --- a/trunk/arch/mips/kernel/octeon_switch.S +++ /dev/null @@ -1,506 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1994, 1995, 1996, by Andreas Busse - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2000 MIPS Technologies, Inc. - * written by Carsten Langgaard, carstenl@mips.com - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * Offset to the current process status flags, the first 32 bytes of the - * stack are not used. - */ -#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) - -/* - * task_struct *resume(task_struct *prev, task_struct *next, - * struct thread_info *next_ti) - */ - .align 7 - LEAF(resume) - .set arch=octeon -#ifndef CONFIG_CPU_HAS_LLSC - sw zero, ll_bit -#endif - mfc0 t1, CP0_STATUS - LONG_S t1, THREAD_STATUS(a0) - cpu_save_nonscratch a0 - LONG_S ra, THREAD_REG31(a0) - - /* check if we need to save COP2 registers */ - PTR_L t2, TASK_THREAD_INFO(a0) - LONG_L t0, ST_OFF(t2) - bbit0 t0, 30, 1f - - /* Disable COP2 in the stored process state */ - li t1, ST0_CU2 - xor t0, t1 - LONG_S t0, ST_OFF(t2) - - /* Enable COP2 so we can save it */ - mfc0 t0, CP0_STATUS - or t0, t1 - mtc0 t0, CP0_STATUS - - /* Save COP2 */ - daddu a0, THREAD_CP2 - jal octeon_cop2_save - dsubu a0, THREAD_CP2 - - /* Disable COP2 now that we are done */ - mfc0 t0, CP0_STATUS - li t1, ST0_CU2 - xor t0, t1 - mtc0 t0, CP0_STATUS - -1: -#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 - /* Check if we need to store CVMSEG state */ - mfc0 t0, $11,7 /* CvmMemCtl */ - bbit0 t0, 6, 3f /* Is user access enabled? */ - - /* Store the CVMSEG state */ - /* Extract the size of CVMSEG */ - andi t0, 0x3f - /* Multiply * (cache line size/sizeof(long)/2) */ - sll t0, 7-LONGLOG-1 - li t1, -32768 /* Base address of CVMSEG */ - LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ - synciobdma -2: - .set noreorder - LONG_L t8, 0(t1) /* Load from CVMSEG */ - subu t0, 1 /* Decrement loop var */ - LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ - LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ - LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ - LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ - bnez t0, 2b /* Loop until we've copied it all */ - LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ - .set reorder - - /* Disable access to CVMSEG */ - mfc0 t0, $11,7 /* CvmMemCtl */ - xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ - mtc0 t0, $11,7 /* CvmMemCtl */ -#endif -3: - /* - * The order of restoring the registers takes care of the race - * updating $28, $29 and kernelsp without disabling ints. - */ - move $28, a2 - cpu_restore_nonscratch a1 - -#if (_THREAD_SIZE - 32) < 0x8000 - PTR_ADDIU t0, $28, _THREAD_SIZE - 32 -#else - PTR_LI t0, _THREAD_SIZE - 32 - PTR_ADDU t0, $28 -#endif - set_saved_sp t0, t1, t2 - - mfc0 t1, CP0_STATUS /* Do we really need this? */ - li a3, 0xff01 - and t1, a3 - LONG_L a2, THREAD_STATUS(a1) - nor a3, $0, a3 - and a2, a3 - or a2, t1 - mtc0 a2, CP0_STATUS - move v0, a0 - jr ra - END(resume) - -/* - * void octeon_cop2_save(struct octeon_cop2_state *a0) - */ - .align 7 - LEAF(octeon_cop2_save) - - dmfc0 t9, $9,7 /* CvmCtl register. */ - - /* Save the COP2 CRC state */ - dmfc2 t0, 0x0201 - dmfc2 t1, 0x0202 - dmfc2 t2, 0x0200 - sd t0, OCTEON_CP2_CRC_IV(a0) - sd t1, OCTEON_CP2_CRC_LENGTH(a0) - sd t2, OCTEON_CP2_CRC_POLY(a0) - /* Skip next instructions if CvmCtl[NODFA_CP2] set */ - bbit1 t9, 28, 1f - - /* Save the LLM state */ - dmfc2 t0, 0x0402 - dmfc2 t1, 0x040A - sd t0, OCTEON_CP2_LLM_DAT(a0) - sd t1, OCTEON_CP2_LLM_DAT+8(a0) - -1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ - - /* Save the COP2 crypto state */ - /* this part is mostly common to both pass 1 and later revisions */ - dmfc2 t0, 0x0084 - dmfc2 t1, 0x0080 - dmfc2 t2, 0x0081 - dmfc2 t3, 0x0082 - sd t0, OCTEON_CP2_3DES_IV(a0) - dmfc2 t0, 0x0088 - sd t1, OCTEON_CP2_3DES_KEY(a0) - dmfc2 t1, 0x0111 /* only necessary for pass 1 */ - sd t2, OCTEON_CP2_3DES_KEY+8(a0) - dmfc2 t2, 0x0102 - sd t3, OCTEON_CP2_3DES_KEY+16(a0) - dmfc2 t3, 0x0103 - sd t0, OCTEON_CP2_3DES_RESULT(a0) - dmfc2 t0, 0x0104 - sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ - dmfc2 t1, 0x0105 - sd t2, OCTEON_CP2_AES_IV(a0) - dmfc2 t2, 0x0106 - sd t3, OCTEON_CP2_AES_IV+8(a0) - dmfc2 t3, 0x0107 - sd t0, OCTEON_CP2_AES_KEY(a0) - dmfc2 t0, 0x0110 - sd t1, OCTEON_CP2_AES_KEY+8(a0) - dmfc2 t1, 0x0100 - sd t2, OCTEON_CP2_AES_KEY+16(a0) - dmfc2 t2, 0x0101 - sd t3, OCTEON_CP2_AES_KEY+24(a0) - mfc0 t3, $15,0 /* Get the processor ID register */ - sd t0, OCTEON_CP2_AES_KEYLEN(a0) - li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ - sd t1, OCTEON_CP2_AES_RESULT(a0) - sd t2, OCTEON_CP2_AES_RESULT+8(a0) - /* Skip to the Pass1 version of the remainder of the COP2 state */ - beq t3, t0, 2f - - /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ - dmfc2 t1, 0x0240 - dmfc2 t2, 0x0241 - dmfc2 t3, 0x0242 - dmfc2 t0, 0x0243 - sd t1, OCTEON_CP2_HSH_DATW(a0) - dmfc2 t1, 0x0244 - sd t2, OCTEON_CP2_HSH_DATW+8(a0) - dmfc2 t2, 0x0245 - sd t3, OCTEON_CP2_HSH_DATW+16(a0) - dmfc2 t3, 0x0246 - sd t0, OCTEON_CP2_HSH_DATW+24(a0) - dmfc2 t0, 0x0247 - sd t1, OCTEON_CP2_HSH_DATW+32(a0) - dmfc2 t1, 0x0248 - sd t2, OCTEON_CP2_HSH_DATW+40(a0) - dmfc2 t2, 0x0249 - sd t3, OCTEON_CP2_HSH_DATW+48(a0) - dmfc2 t3, 0x024A - sd t0, OCTEON_CP2_HSH_DATW+56(a0) - dmfc2 t0, 0x024B - sd t1, OCTEON_CP2_HSH_DATW+64(a0) - dmfc2 t1, 0x024C - sd t2, OCTEON_CP2_HSH_DATW+72(a0) - dmfc2 t2, 0x024D - sd t3, OCTEON_CP2_HSH_DATW+80(a0) - dmfc2 t3, 0x024E - sd t0, OCTEON_CP2_HSH_DATW+88(a0) - dmfc2 t0, 0x0250 - sd t1, OCTEON_CP2_HSH_DATW+96(a0) - dmfc2 t1, 0x0251 - sd t2, OCTEON_CP2_HSH_DATW+104(a0) - dmfc2 t2, 0x0252 - sd t3, OCTEON_CP2_HSH_DATW+112(a0) - dmfc2 t3, 0x0253 - sd t0, OCTEON_CP2_HSH_IVW(a0) - dmfc2 t0, 0x0254 - sd t1, OCTEON_CP2_HSH_IVW+8(a0) - dmfc2 t1, 0x0255 - sd t2, OCTEON_CP2_HSH_IVW+16(a0) - dmfc2 t2, 0x0256 - sd t3, OCTEON_CP2_HSH_IVW+24(a0) - dmfc2 t3, 0x0257 - sd t0, OCTEON_CP2_HSH_IVW+32(a0) - dmfc2 t0, 0x0258 - sd t1, OCTEON_CP2_HSH_IVW+40(a0) - dmfc2 t1, 0x0259 - sd t2, OCTEON_CP2_HSH_IVW+48(a0) - dmfc2 t2, 0x025E - sd t3, OCTEON_CP2_HSH_IVW+56(a0) - dmfc2 t3, 0x025A - sd t0, OCTEON_CP2_GFM_MULT(a0) - dmfc2 t0, 0x025B - sd t1, OCTEON_CP2_GFM_MULT+8(a0) - sd t2, OCTEON_CP2_GFM_POLY(a0) - sd t3, OCTEON_CP2_GFM_RESULT(a0) - sd t0, OCTEON_CP2_GFM_RESULT+8(a0) - jr ra - -2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ - dmfc2 t3, 0x0040 - dmfc2 t0, 0x0041 - dmfc2 t1, 0x0042 - dmfc2 t2, 0x0043 - sd t3, OCTEON_CP2_HSH_DATW(a0) - dmfc2 t3, 0x0044 - sd t0, OCTEON_CP2_HSH_DATW+8(a0) - dmfc2 t0, 0x0045 - sd t1, OCTEON_CP2_HSH_DATW+16(a0) - dmfc2 t1, 0x0046 - sd t2, OCTEON_CP2_HSH_DATW+24(a0) - dmfc2 t2, 0x0048 - sd t3, OCTEON_CP2_HSH_DATW+32(a0) - dmfc2 t3, 0x0049 - sd t0, OCTEON_CP2_HSH_DATW+40(a0) - dmfc2 t0, 0x004A - sd t1, OCTEON_CP2_HSH_DATW+48(a0) - sd t2, OCTEON_CP2_HSH_IVW(a0) - sd t3, OCTEON_CP2_HSH_IVW+8(a0) - sd t0, OCTEON_CP2_HSH_IVW+16(a0) - -3: /* pass 1 or CvmCtl[NOCRYPTO] set */ - jr ra - END(octeon_cop2_save) - -/* - * void octeon_cop2_restore(struct octeon_cop2_state *a0) - */ - .align 7 - .set push - .set noreorder - LEAF(octeon_cop2_restore) - /* First cache line was prefetched before the call */ - pref 4, 128(a0) - dmfc0 t9, $9,7 /* CvmCtl register. */ - - pref 4, 256(a0) - ld t0, OCTEON_CP2_CRC_IV(a0) - pref 4, 384(a0) - ld t1, OCTEON_CP2_CRC_LENGTH(a0) - ld t2, OCTEON_CP2_CRC_POLY(a0) - - /* Restore the COP2 CRC state */ - dmtc2 t0, 0x0201 - dmtc2 t1, 0x1202 - bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ - dmtc2 t2, 0x4200 - - /* Restore the LLM state */ - ld t0, OCTEON_CP2_LLM_DAT(a0) - ld t1, OCTEON_CP2_LLM_DAT+8(a0) - dmtc2 t0, 0x0402 - dmtc2 t1, 0x040A - -2: - bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */ - nop - - /* Restore the COP2 crypto state common to pass 1 and pass 2 */ - ld t0, OCTEON_CP2_3DES_IV(a0) - ld t1, OCTEON_CP2_3DES_KEY(a0) - ld t2, OCTEON_CP2_3DES_KEY+8(a0) - dmtc2 t0, 0x0084 - ld t0, OCTEON_CP2_3DES_KEY+16(a0) - dmtc2 t1, 0x0080 - ld t1, OCTEON_CP2_3DES_RESULT(a0) - dmtc2 t2, 0x0081 - ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ - dmtc2 t0, 0x0082 - ld t0, OCTEON_CP2_AES_IV(a0) - dmtc2 t1, 0x0098 - ld t1, OCTEON_CP2_AES_IV+8(a0) - dmtc2 t2, 0x010A /* only really needed for pass 1 */ - ld t2, OCTEON_CP2_AES_KEY(a0) - dmtc2 t0, 0x0102 - ld t0, OCTEON_CP2_AES_KEY+8(a0) - dmtc2 t1, 0x0103 - ld t1, OCTEON_CP2_AES_KEY+16(a0) - dmtc2 t2, 0x0104 - ld t2, OCTEON_CP2_AES_KEY+24(a0) - dmtc2 t0, 0x0105 - ld t0, OCTEON_CP2_AES_KEYLEN(a0) - dmtc2 t1, 0x0106 - ld t1, OCTEON_CP2_AES_RESULT(a0) - dmtc2 t2, 0x0107 - ld t2, OCTEON_CP2_AES_RESULT+8(a0) - mfc0 t3, $15,0 /* Get the processor ID register */ - dmtc2 t0, 0x0110 - li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ - dmtc2 t1, 0x0100 - bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ - dmtc2 t2, 0x0101 - - /* this code is specific for pass 1 */ - ld t0, OCTEON_CP2_HSH_DATW(a0) - ld t1, OCTEON_CP2_HSH_DATW+8(a0) - ld t2, OCTEON_CP2_HSH_DATW+16(a0) - dmtc2 t0, 0x0040 - ld t0, OCTEON_CP2_HSH_DATW+24(a0) - dmtc2 t1, 0x0041 - ld t1, OCTEON_CP2_HSH_DATW+32(a0) - dmtc2 t2, 0x0042 - ld t2, OCTEON_CP2_HSH_DATW+40(a0) - dmtc2 t0, 0x0043 - ld t0, OCTEON_CP2_HSH_DATW+48(a0) - dmtc2 t1, 0x0044 - ld t1, OCTEON_CP2_HSH_IVW(a0) - dmtc2 t2, 0x0045 - ld t2, OCTEON_CP2_HSH_IVW+8(a0) - dmtc2 t0, 0x0046 - ld t0, OCTEON_CP2_HSH_IVW+16(a0) - dmtc2 t1, 0x0048 - dmtc2 t2, 0x0049 - b done_restore /* unconditional branch */ - dmtc2 t0, 0x004A - -3: /* this is post-pass1 code */ - ld t2, OCTEON_CP2_HSH_DATW(a0) - ld t0, OCTEON_CP2_HSH_DATW+8(a0) - ld t1, OCTEON_CP2_HSH_DATW+16(a0) - dmtc2 t2, 0x0240 - ld t2, OCTEON_CP2_HSH_DATW+24(a0) - dmtc2 t0, 0x0241 - ld t0, OCTEON_CP2_HSH_DATW+32(a0) - dmtc2 t1, 0x0242 - ld t1, OCTEON_CP2_HSH_DATW+40(a0) - dmtc2 t2, 0x0243 - ld t2, OCTEON_CP2_HSH_DATW+48(a0) - dmtc2 t0, 0x0244 - ld t0, OCTEON_CP2_HSH_DATW+56(a0) - dmtc2 t1, 0x0245 - ld t1, OCTEON_CP2_HSH_DATW+64(a0) - dmtc2 t2, 0x0246 - ld t2, OCTEON_CP2_HSH_DATW+72(a0) - dmtc2 t0, 0x0247 - ld t0, OCTEON_CP2_HSH_DATW+80(a0) - dmtc2 t1, 0x0248 - ld t1, OCTEON_CP2_HSH_DATW+88(a0) - dmtc2 t2, 0x0249 - ld t2, OCTEON_CP2_HSH_DATW+96(a0) - dmtc2 t0, 0x024A - ld t0, OCTEON_CP2_HSH_DATW+104(a0) - dmtc2 t1, 0x024B - ld t1, OCTEON_CP2_HSH_DATW+112(a0) - dmtc2 t2, 0x024C - ld t2, OCTEON_CP2_HSH_IVW(a0) - dmtc2 t0, 0x024D - ld t0, OCTEON_CP2_HSH_IVW+8(a0) - dmtc2 t1, 0x024E - ld t1, OCTEON_CP2_HSH_IVW+16(a0) - dmtc2 t2, 0x0250 - ld t2, OCTEON_CP2_HSH_IVW+24(a0) - dmtc2 t0, 0x0251 - ld t0, OCTEON_CP2_HSH_IVW+32(a0) - dmtc2 t1, 0x0252 - ld t1, OCTEON_CP2_HSH_IVW+40(a0) - dmtc2 t2, 0x0253 - ld t2, OCTEON_CP2_HSH_IVW+48(a0) - dmtc2 t0, 0x0254 - ld t0, OCTEON_CP2_HSH_IVW+56(a0) - dmtc2 t1, 0x0255 - ld t1, OCTEON_CP2_GFM_MULT(a0) - dmtc2 t2, 0x0256 - ld t2, OCTEON_CP2_GFM_MULT+8(a0) - dmtc2 t0, 0x0257 - ld t0, OCTEON_CP2_GFM_POLY(a0) - dmtc2 t1, 0x0258 - ld t1, OCTEON_CP2_GFM_RESULT(a0) - dmtc2 t2, 0x0259 - ld t2, OCTEON_CP2_GFM_RESULT+8(a0) - dmtc2 t0, 0x025E - dmtc2 t1, 0x025A - dmtc2 t2, 0x025B - -done_restore: - jr ra - nop - END(octeon_cop2_restore) - .set pop - -/* - * void octeon_mult_save() - * sp is assumed to point to a struct pt_regs - * - * NOTE: This is called in SAVE_SOME in stackframe.h. It can only - * safely modify k0 and k1. - */ - .align 7 - .set push - .set noreorder - LEAF(octeon_mult_save) - dmfc0 k0, $9,7 /* CvmCtl register. */ - bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */ - nop - - /* Save the multiplier state */ - v3mulu k0, $0, $0 - v3mulu k1, $0, $0 - sd k0, PT_MTP(sp) /* PT_MTP has P0 */ - v3mulu k0, $0, $0 - sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ - ori k1, $0, 1 - v3mulu k1, k1, $0 - sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ - v3mulu k0, $0, $0 - sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ - v3mulu k1, $0, $0 - sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ - jr ra - sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ - -1: /* Resume here if CvmCtl[NOMUL] */ - jr ra - END(octeon_mult_save) - .set pop - -/* - * void octeon_mult_restore() - * sp is assumed to point to a struct pt_regs - * - * NOTE: This is called in RESTORE_SOME in stackframe.h. - */ - .align 7 - .set push - .set noreorder - LEAF(octeon_mult_restore) - dmfc0 k1, $9,7 /* CvmCtl register. */ - ld v0, PT_MPL(sp) /* MPL0 */ - ld v1, PT_MPL+8(sp) /* MPL1 */ - ld k0, PT_MPL+16(sp) /* MPL2 */ - bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ - /* Normally falls through, so no time wasted here */ - nop - - /* Restore the multiplier state */ - ld k1, PT_MTP+16(sp) /* P2 */ - MTM0 v0 /* MPL0 */ - ld v0, PT_MTP+8(sp) /* P1 */ - MTM1 v1 /* MPL1 */ - ld v1, PT_MTP(sp) /* P0 */ - MTM2 k0 /* MPL2 */ - MTP2 k1 /* P2 */ - MTP1 v0 /* P1 */ - jr ra - MTP0 v1 /* P0 */ - -1: /* Resume here if CvmCtl[NOMUL] */ - jr ra - nop - END(octeon_mult_restore) - .set pop - diff --git a/trunk/arch/mips/kernel/ptrace32.c b/trunk/arch/mips/kernel/ptrace32.c index c4f9ac17474a..1ca34104e593 100644 --- a/trunk/arch/mips/kernel/ptrace32.c +++ b/trunk/arch/mips/kernel/ptrace32.c @@ -49,6 +49,19 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, int ret; switch (request) { + /* when I and D space are separate, these will need to be fixed. */ + case PTRACE_PEEKTEXT: /* read word at location addr. */ + case PTRACE_PEEKDATA: { + unsigned int tmp; + int copied; + + copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); + ret = -EIO; + if (copied != sizeof(tmp)) + break; + ret = put_user(tmp, (unsigned int __user *) (unsigned long) data); + break; + } /* * Read 4 bytes of the other process' storage @@ -195,6 +208,16 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; } + /* when I and D space are separate, this will have to be fixed. */ + case PTRACE_POKETEXT: /* write the word at location addr. */ + case PTRACE_POKEDATA: + ret = 0; + if (access_process_vm(child, addr, &data, sizeof(data), 1) + == sizeof(data)) + break; + ret = -EIO; + break; + /* * Write 4 bytes into the other process' storage * data is the 4 bytes that the user wants written @@ -309,11 +332,50 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); break; + case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ + case PTRACE_CONT: { /* restart after signal. */ + ret = -EIO; + if (!valid_signal(data)) + break; + if (request == PTRACE_SYSCALL) { + set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } + else { + clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } + child->exit_code = data; + wake_up_process(child); + ret = 0; + break; + } + + /* + * make the child exit. Best I can do is send it a sigkill. + * perhaps it should be put in the status that it wants to + * exit. + */ + case PTRACE_KILL: + ret = 0; + if (child->exit_state == EXIT_ZOMBIE) /* already dead */ + break; + child->exit_code = SIGKILL; + wake_up_process(child); + break; + case PTRACE_GET_THREAD_AREA: ret = put_user(task_thread_info(child)->tp_value, (unsigned int __user *) (unsigned long) data); break; + case PTRACE_DETACH: /* detach a process that was attached. */ + ret = ptrace_detach(child, data); + break; + + case PTRACE_GETEVENTMSG: + ret = put_user(child->ptrace_message, + (unsigned int __user *) (unsigned long) data); + break; + case PTRACE_GET_THREAD_AREA_3264: ret = put_user(task_thread_info(child)->tp_value, (unsigned long __user *) (unsigned long) data); @@ -330,7 +392,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, break; default: - ret = compat_ptrace_request(child, request, addr, data); + ret = ptrace_request(child, request, addr, data); break; } out: diff --git a/trunk/arch/mips/kernel/smtc.c b/trunk/arch/mips/kernel/smtc.c index 5f5af7d4c890..d2c1ab12425a 100644 --- a/trunk/arch/mips/kernel/smtc.c +++ b/trunk/arch/mips/kernel/smtc.c @@ -921,13 +921,11 @@ void ipi_decode(struct smtc_ipi *pipi) struct clock_event_device *cd; void *arg_copy = pipi->arg; int type_copy = pipi->type; - int irq = MIPS_CPU_IRQ_BASE + 1; - smtc_ipi_nq(&freeIPIq, pipi); switch (type_copy) { case SMTC_CLOCK_TICK: irq_enter(); - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++; cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); irq_exit(); diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index f6083c6bfaa4..353056110f2b 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -47,7 +47,6 @@ #include #include #include -#include extern void check_wait(void); extern asmlinkage void r4k_wait(void); @@ -79,10 +78,6 @@ extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu); -#ifdef CONFIG_CPU_CAVIUM_OCTEON -extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); -#endif - void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -865,7 +860,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) unsigned int opcode; unsigned int cpid; int status; - unsigned long __maybe_unused flags; die_if_kernel("do_cpu invoked from kernel context!", regs); @@ -921,17 +915,6 @@ asmlinkage void do_cpu(struct pt_regs *regs) return; case 2: -#ifdef CONFIG_CPU_CAVIUM_OCTEON - prefetch(¤t->thread.cp2); - local_irq_save(flags); - KSTK_STATUS(current) |= ST0_CU2; - status = read_c0_status(); - write_c0_status(status | ST0_CU2); - octeon_cop2_restore(&(current->thread.cp2)); - write_c0_status(status & ~ST0_CU2); - local_irq_restore(flags); - return; -#endif case 3: break; } @@ -1505,10 +1488,6 @@ void __cpuinit per_cpu_trap_init(void) write_c0_hwrena(enable); } -#ifdef CONFIG_CPU_CAVIUM_OCTEON - write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */ -#endif - #ifdef CONFIG_MIPS_MT_SMTC if (!secondaryTC) { #endif /* CONFIG_MIPS_MT_SMTC */ diff --git a/trunk/arch/mips/lib/Makefile b/trunk/arch/mips/lib/Makefile index c13c7ad2cdae..dbcf6511b74e 100644 --- a/trunk/arch/mips/lib/Makefile +++ b/trunk/arch/mips/lib/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o diff --git a/trunk/arch/mips/mm/Makefile b/trunk/arch/mips/mm/Makefile index d7ec95522292..95ba32b5b720 100644 --- a/trunk/arch/mips/mm/Makefile +++ b/trunk/arch/mips/mm/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o -obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o diff --git a/trunk/arch/mips/mm/c-octeon.c b/trunk/arch/mips/mm/c-octeon.c deleted file mode 100644 index 44d01a0a8490..000000000000 --- a/trunk/arch/mips/mm/c-octeon.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005-2007 Cavium Networks - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -unsigned long long cache_err_dcache[NR_CPUS]; - -/** - * Octeon automatically flushes the dcache on tlb changes, so - * from Linux's viewpoint it acts much like a physically - * tagged cache. No flushing is needed - * - */ -static void octeon_flush_data_cache_page(unsigned long addr) -{ - /* Nothing to do */ -} - -static inline void octeon_local_flush_icache(void) -{ - asm volatile ("synci 0($0)"); -} - -/* - * Flush local I-cache for the specified range. - */ -static void local_octeon_flush_icache_range(unsigned long start, - unsigned long end) -{ - octeon_local_flush_icache(); -} - -/** - * Flush caches as necessary for all cores affected by a - * vma. If no vma is supplied, all cores are flushed. - * - * @vma: VMA to flush or NULL to flush all icaches. - */ -static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) -{ - extern void octeon_send_ipi_single(int cpu, unsigned int action); -#ifdef CONFIG_SMP - int cpu; - cpumask_t mask; -#endif - - mb(); - octeon_local_flush_icache(); -#ifdef CONFIG_SMP - preempt_disable(); - cpu = smp_processor_id(); - - /* - * If we have a vma structure, we only need to worry about - * cores it has been used on - */ - if (vma) - mask = vma->vm_mm->cpu_vm_mask; - else - mask = cpu_online_map; - cpu_clear(cpu, mask); - for_each_cpu_mask(cpu, mask) - octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); - - preempt_enable(); -#endif -} - - -/** - * Called to flush the icache on all cores - */ -static void octeon_flush_icache_all(void) -{ - octeon_flush_icache_all_cores(NULL); -} - - -/** - * Called to flush all memory associated with a memory - * context. - * - * @mm: Memory context to flush - */ -static void octeon_flush_cache_mm(struct mm_struct *mm) -{ - /* - * According to the R4K version of this file, CPUs without - * dcache aliases don't need to do anything here - */ -} - - -/** - * Flush a range of kernel addresses out of the icache - * - */ -static void octeon_flush_icache_range(unsigned long start, unsigned long end) -{ - octeon_flush_icache_all_cores(NULL); -} - - -/** - * Flush the icache for a trampoline. These are used for interrupt - * and exception hooking. - * - * @addr: Address to flush - */ -static void octeon_flush_cache_sigtramp(unsigned long addr) -{ - struct vm_area_struct *vma; - - vma = find_vma(current->mm, addr); - octeon_flush_icache_all_cores(vma); -} - - -/** - * Flush a range out of a vma - * - * @vma: VMA to flush - * @start: - * @end: - */ -static void octeon_flush_cache_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - if (vma->vm_flags & VM_EXEC) - octeon_flush_icache_all_cores(vma); -} - - -/** - * Flush a specific page of a vma - * - * @vma: VMA to flush page for - * @page: Page to flush - * @pfn: - */ -static void octeon_flush_cache_page(struct vm_area_struct *vma, - unsigned long page, unsigned long pfn) -{ - if (vma->vm_flags & VM_EXEC) - octeon_flush_icache_all_cores(vma); -} - - -/** - * Probe Octeon's caches - * - */ -static void __devinit probe_octeon(void) -{ - unsigned long icache_size; - unsigned long dcache_size; - unsigned int config1; - struct cpuinfo_mips *c = ¤t_cpu_data; - - switch (c->cputype) { - case CPU_CAVIUM_OCTEON: - config1 = read_c0_config1(); - c->icache.linesz = 2 << ((config1 >> 19) & 7); - c->icache.sets = 64 << ((config1 >> 22) & 7); - c->icache.ways = 1 + ((config1 >> 16) & 7); - c->icache.flags |= MIPS_CACHE_VTAG; - icache_size = - c->icache.sets * c->icache.ways * c->icache.linesz; - c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; - c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else - c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ - c->dcache.ways = 64; - dcache_size = - c->dcache.sets * c->dcache.ways * c->dcache.linesz; - c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; - c->options |= MIPS_CPU_PREFETCH; - break; - - default: - panic("Unsupported Cavium Networks CPU type\n"); - break; - } - - /* compute a couple of other cache variables */ - c->icache.waysize = icache_size / c->icache.ways; - c->dcache.waysize = dcache_size / c->dcache.ways; - - c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); - c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); - - if (smp_processor_id() == 0) { - pr_notice("Primary instruction cache %ldkB, %s, %d way, " - "%d sets, linesize %d bytes.\n", - icache_size >> 10, - cpu_has_vtag_icache ? - "virtually tagged" : "physically tagged", - c->icache.ways, c->icache.sets, c->icache.linesz); - - pr_notice("Primary data cache %ldkB, %d-way, %d sets, " - "linesize %d bytes.\n", - dcache_size >> 10, c->dcache.ways, - c->dcache.sets, c->dcache.linesz); - } -} - - -/** - * Setup the Octeon cache flush routines - * - */ -void __devinit octeon_cache_init(void) -{ - extern unsigned long ebase; - extern char except_vec2_octeon; - - memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80); - octeon_flush_cache_sigtramp(ebase + 0x100); - - probe_octeon(); - - shm_align_mask = PAGE_SIZE - 1; - - flush_cache_all = octeon_flush_icache_all; - __flush_cache_all = octeon_flush_icache_all; - flush_cache_mm = octeon_flush_cache_mm; - flush_cache_page = octeon_flush_cache_page; - flush_cache_range = octeon_flush_cache_range; - flush_cache_sigtramp = octeon_flush_cache_sigtramp; - flush_icache_all = octeon_flush_icache_all; - flush_data_cache_page = octeon_flush_data_cache_page; - flush_icache_range = octeon_flush_icache_range; - local_flush_icache_range = local_octeon_flush_icache_range; - - build_clear_page(); - build_copy_page(); -} - -/** - * Handle a cache error exception - */ - -static void cache_parity_error_octeon(int non_recoverable) -{ - unsigned long coreid = cvmx_get_core_num(); - uint64_t icache_err = read_octeon_c0_icacheerr(); - - pr_err("Cache error exception:\n"); - pr_err("cp0_errorepc == %lx\n", read_c0_errorepc()); - if (icache_err & 1) { - pr_err("CacheErr (Icache) == %llx\n", - (unsigned long long)icache_err); - write_octeon_c0_icacheerr(0); - } - if (cache_err_dcache[coreid] & 1) { - pr_err("CacheErr (Dcache) == %llx\n", - (unsigned long long)cache_err_dcache[coreid]); - cache_err_dcache[coreid] = 0; - } - - if (non_recoverable) - panic("Can't handle cache error: nested exception"); -} - -/** - * Called when the the exception is not recoverable - */ - -asmlinkage void cache_parity_error_octeon_recoverable(void) -{ - cache_parity_error_octeon(0); -} - -/** - * Called when the the exception is recoverable - */ - -asmlinkage void cache_parity_error_octeon_non_recoverable(void) -{ - cache_parity_error_octeon(1); -} - diff --git a/trunk/arch/mips/mm/cache.c b/trunk/arch/mips/mm/cache.c index 98ad0a82c29e..1eb7c71e3d6a 100644 --- a/trunk/arch/mips/mm/cache.c +++ b/trunk/arch/mips/mm/cache.c @@ -182,12 +182,6 @@ void __devinit cpu_cache_init(void) tx39_cache_init(); } - if (cpu_has_octeon_cache) { - extern void __weak octeon_cache_init(void); - - octeon_cache_init(); - } - setup_protection_map(); } diff --git a/trunk/arch/mips/mm/cex-oct.S b/trunk/arch/mips/mm/cex-oct.S deleted file mode 100644 index 3db8553fcd34..000000000000 --- a/trunk/arch/mips/mm/cex-oct.S +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Cavium Networks - * Cache error handler - */ - -#include -#include -#include -#include - -/* - * Handle cache error. Indicate to the second level handler whether - * the exception is recoverable. - */ - LEAF(except_vec2_octeon) - - .set push - .set mips64r2 - .set noreorder - .set noat - - - /* due to an errata we need to read the COP0 CacheErr (Dcache) - * before any cache/DRAM access */ - - rdhwr k0, $0 /* get core_id */ - PTR_LA k1, cache_err_dcache - sll k0, k0, 3 - PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ - - dmfc0 k0, CP0_CACHEERR, 1 - sd k0, (k1) - dmtc0 $0, CP0_CACHEERR, 1 - - /* check whether this is a nested exception */ - mfc0 k1, CP0_STATUS - andi k1, k1, ST0_EXL - beqz k1, 1f - nop - j cache_parity_error_octeon_non_recoverable - nop - - /* exception is recoverable */ -1: j handle_cache_err - nop - - .set pop - END(except_vec2_octeon) - - /* We need to jump to handle_cache_err so that the previous handler - * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX - * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ - LEAF(handle_cache_err) - .set push - .set noreorder - .set noat - - SAVE_ALL - KMODE - jal cache_parity_error_octeon_recoverable - nop - j ret_from_exception - nop - - .set pop - END(handle_cache_err) diff --git a/trunk/arch/mips/mm/dma-default.c b/trunk/arch/mips/mm/dma-default.c index 546e6977d4ff..e6708b3ad343 100644 --- a/trunk/arch/mips/mm/dma-default.c +++ b/trunk/arch/mips/mm/dma-default.c @@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent); void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { - plat_unmap_dma_mem(dev, dma_handle); + plat_unmap_dma_mem(dma_handle); free_pages((unsigned long) vaddr, get_order(size)); } @@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, { unsigned long addr = (unsigned long) vaddr; - plat_unmap_dma_mem(dev, dma_handle); + plat_unmap_dma_mem(dma_handle); if (!plat_device_is_coherent(dev)) addr = CAC_ADDR(addr); @@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, __dma_sync(dma_addr_to_virt(dma_addr), size, direction); - plat_unmap_dma_mem(dev, dma_addr); + plat_unmap_dma_mem(dma_addr); } EXPORT_SYMBOL(dma_unmap_single); @@ -229,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, dma_cache_wback_inv(addr, size); } - plat_unmap_dma_mem(dev, dma_address); + plat_unmap_dma_mem(dma_address); } EXPORT_SYMBOL(dma_unmap_page); @@ -249,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, if (addr) __dma_sync(addr, sg->length, direction); } - plat_unmap_dma_mem(dev, sg->dma_address); + plat_unmap_dma_mem(sg->dma_address); } } @@ -275,7 +275,6 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, { BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) { unsigned long addr; @@ -306,7 +305,6 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, { BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) { unsigned long addr; @@ -353,14 +351,22 @@ EXPORT_SYMBOL(dma_sync_sg_for_device); int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - return plat_dma_mapping_error(dev, dma_addr); + return 0; } EXPORT_SYMBOL(dma_mapping_error); int dma_supported(struct device *dev, u64 mask) { - return plat_dma_supported(dev, mask); + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; } EXPORT_SYMBOL(dma_supported); @@ -377,7 +383,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, { BUG_ON(direction == DMA_NONE); - plat_extra_sync_for_device(dev); if (!plat_device_is_coherent(dev)) __dma_sync((unsigned long)vaddr, size, direction); } diff --git a/trunk/arch/mips/mm/tlb-r4k.c b/trunk/arch/mips/mm/tlb-r4k.c index 9619f66e531e..5ce2fa745626 100644 --- a/trunk/arch/mips/mm/tlb-r4k.c +++ b/trunk/arch/mips/mm/tlb-r4k.c @@ -478,10 +478,7 @@ void __cpuinit tlb_init(void) probe_tlb(config); write_c0_pagemask(PM_DEFAULT_MASK); write_c0_wired(0); - if (current_cpu_type() == CPU_R10000 || - current_cpu_type() == CPU_R12000 || - current_cpu_type() == CPU_R14000) - write_c0_framemask(0); + write_c0_framemask(0); temp_tlb_entry = current_cpu_data.tlbsize - 1; /* From this point on the ARC firmware is dead. */ diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c index 42942038d0fd..979cf9197282 100644 --- a/trunk/arch/mips/mm/tlbex.c +++ b/trunk/arch/mips/mm/tlbex.c @@ -317,7 +317,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM3302: case CPU_BCM4710: case CPU_LOONGSON2: - case CPU_CAVIUM_OCTEON: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); diff --git a/trunk/arch/mips/sgi-ip22/ip22-int.c b/trunk/arch/mips/sgi-ip22/ip22-int.c index 0ecd5fe9486e..f8b18af141a1 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-int.c +++ b/trunk/arch/mips/sgi-ip22/ip22-int.c @@ -155,7 +155,7 @@ static void indy_buserror_irq(void) int irq = SGI_BUSERR_IRQ; irq_enter(); - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[irq]++; ip22_be_interrupt(irq); irq_exit(); } diff --git a/trunk/arch/mips/sgi-ip22/ip22-time.c b/trunk/arch/mips/sgi-ip22/ip22-time.c index c8f7d2328b24..3dcb27ec0c53 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-time.c +++ b/trunk/arch/mips/sgi-ip22/ip22-time.c @@ -122,7 +122,7 @@ void indy_8254timer_irq(void) char c; irq_enter(); - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[irq]++; printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); ArcRead(0, &c, 1, &cnt); ArcEnterInteractiveMode(); diff --git a/trunk/arch/mips/sibyte/bcm1480/smp.c b/trunk/arch/mips/sibyte/bcm1480/smp.c index 314691648c97..dddfda8e8294 100644 --- a/trunk/arch/mips/sibyte/bcm1480/smp.c +++ b/trunk/arch/mips/sibyte/bcm1480/smp.c @@ -178,10 +178,9 @@ struct plat_smp_ops bcm1480_smp_ops = { void bcm1480_mailbox_interrupt(void) { int cpu = smp_processor_id(); - int irq = K_BCM1480_INT_MBOX_0_0; unsigned int action; - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; /* Load the mailbox register to figure out what we're supposed to do */ action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; diff --git a/trunk/arch/mips/sibyte/sb1250/smp.c b/trunk/arch/mips/sibyte/sb1250/smp.c index cad14003b84f..5950a288a7da 100644 --- a/trunk/arch/mips/sibyte/sb1250/smp.c +++ b/trunk/arch/mips/sibyte/sb1250/smp.c @@ -166,10 +166,9 @@ struct plat_smp_ops sb_smp_ops = { void sb1250_mailbox_interrupt(void) { int cpu = smp_processor_id(); - int irq = K_INT_MBOX_0; unsigned int action; - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[K_INT_MBOX_0]++; /* Load the mailbox register to figure out what we're supposed to do */ action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; diff --git a/trunk/arch/mn10300/kernel/mn10300-watchdog.c b/trunk/arch/mn10300/kernel/mn10300-watchdog.c index 2e370d88a87a..10811e981d20 100644 --- a/trunk/arch/mn10300/kernel/mn10300-watchdog.c +++ b/trunk/arch/mn10300/kernel/mn10300-watchdog.c @@ -130,7 +130,6 @@ void watchdog_interrupt(struct pt_regs *regs, enum exception_code excep) * the stack NMI-atomically, it's safe to use smp_processor_id(). */ int sum, cpu = smp_processor_id(); - int irq = NMIIRQ; u8 wdt, tmp; wdt = WDCTR & ~WDCTR_WDCNE; @@ -139,7 +138,7 @@ void watchdog_interrupt(struct pt_regs *regs, enum exception_code excep) NMICR = NMICR_WDIF; nmi_count(cpu)++; - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + kstat_this_cpu.irqs[NMIIRQ]++; sum = irq_stat[cpu].__irq_count; if (last_irq_sums[cpu] == sum) { diff --git a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts index e78c355c7bac..9708b3423bbd 100644 --- a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts +++ b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts @@ -88,21 +88,6 @@ compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; }; - - wdt@4,2000 { - compatible = "gef,fpga-wdt"; - reg = <0x4 0x2000 0x8>; - interrupts = <0x1a 0x4>; - interrupt-parent = <&gef_pic>; - }; - /* Second watchdog available, driver currently supports one. - wdt@4,2010 { - compatible = "gef,fpga-wdt"; - reg = <0x4 0x2010 0x8>; - interrupts = <0x1b 0x4>; - interrupt-parent = <&gef_pic>; - }; - */ gef_pic: pic@4,4000 { #interrupt-cells = <1>; interrupt-controller; diff --git a/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig index 391874c7b436..cd1ffa449327 100644 --- a/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/trunk/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -1164,7 +1164,6 @@ CONFIG_WATCHDOG=y # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_8xxx_WDT is not set -CONFIG_GEF_WDT=y # # PCI-based Watchdog Cards diff --git a/trunk/arch/powerpc/platforms/cell/cbe_cpufreq.c b/trunk/arch/powerpc/platforms/cell/cbe_cpufreq.c index e6506cd0ff94..ec7c8f45a215 100644 --- a/trunk/arch/powerpc/platforms/cell/cbe_cpufreq.c +++ b/trunk/arch/powerpc/platforms/cell/cbe_cpufreq.c @@ -118,7 +118,7 @@ static int cbe_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->cur = cbe_freqs[cur_pmode].frequency; #ifdef CONFIG_SMP - cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu)); + policy->cpus = per_cpu(cpu_sibling_map, policy->cpu); #endif cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu); diff --git a/trunk/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/trunk/arch/powerpc/platforms/cell/cpufreq_spudemand.c index 968c1c0b4d5b..a3c6c01bd6db 100644 --- a/trunk/arch/powerpc/platforms/cell/cpufreq_spudemand.c +++ b/trunk/arch/powerpc/platforms/cell/cpufreq_spudemand.c @@ -110,7 +110,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event) } /* initialize spu_gov_info for all affected cpus */ - for_each_cpu(i, policy->cpus) { + for_each_cpu_mask(i, policy->cpus) { affected_info = &per_cpu(spu_gov_info, i); affected_info->policy = policy; } @@ -127,7 +127,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event) spu_gov_cancel_work(info); /* clean spu_gov_info for all affected cpus */ - for_each_cpu (i, policy->cpus) { + for_each_cpu_mask (i, policy->cpus) { info = &per_cpu(spu_gov_info, i); info->policy = NULL; } diff --git a/trunk/arch/powerpc/platforms/pasemi/cpufreq.c b/trunk/arch/powerpc/platforms/pasemi/cpufreq.c index be2527a516ea..86db47c1b665 100644 --- a/trunk/arch/powerpc/platforms/pasemi/cpufreq.c +++ b/trunk/arch/powerpc/platforms/pasemi/cpufreq.c @@ -213,7 +213,7 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) pr_debug("current astate is at %d\n",cur_astate); policy->cur = pas_freqs[cur_astate].frequency; - cpumask_copy(policy->cpus, &cpu_online_map); + policy->cpus = cpu_online_map; ppc_proc_freq = policy->cur * 1000ul; diff --git a/trunk/arch/powerpc/platforms/powermac/cpufreq_64.c b/trunk/arch/powerpc/platforms/powermac/cpufreq_64.c index beb38333b6d2..4dfb4bc242b5 100644 --- a/trunk/arch/powerpc/platforms/powermac/cpufreq_64.c +++ b/trunk/arch/powerpc/platforms/powermac/cpufreq_64.c @@ -362,7 +362,7 @@ static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) /* secondary CPUs are tied to the primary one by the * cpufreq core if in the secondary policy we tell it that * it actually must be one policy together with all others. */ - cpumask_copy(policy->cpus, &cpu_online_map); + policy->cpus = cpu_online_map; cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); return cpufreq_frequency_table_cpuinfo(policy, diff --git a/trunk/arch/sparc/configs/sparc32_defconfig b/trunk/arch/sparc/configs/sparc32_defconfig index 09ab46e4c59d..2e3a149ea0e7 100644 --- a/trunk/arch/sparc/configs/sparc32_defconfig +++ b/trunk/arch/sparc/configs/sparc32_defconfig @@ -1,21 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.28 -# Thu Jan 8 16:45:44 2009 +# Linux kernel version: 2.6.25 +# Tue Apr 29 01:28:58 2008 # -# CONFIG_64BIT is not set -CONFIG_SPARC=y -CONFIG_SPARC32=y -# CONFIG_SPARC64 is not set -CONFIG_ARCH_DEFCONFIG="arch/sparc/configs/sparc32_defconfig" -CONFIG_BITS=32 -CONFIG_AUDIT_ARCH=y CONFIG_MMU=y CONFIG_HIGHMEM=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_ARCH_NO_VIRT_TO_BUS=y CONFIG_OF=y +CONFIG_HZ=100 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -72,30 +66,31 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -110,73 +105,59 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_FREEZER is not set # -# Processor type and features +# General machine setup # # CONFIG_SMP is not set -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set +CONFIG_SPARC=y +CONFIG_SPARC32=y +CONFIG_SBUS=y +CONFIG_SBUSCHAR=y +CONFIG_SERIAL_CONSOLE=y +CONFIG_SUN_AUXIO=y +CONFIG_SUN_IO=y CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_EMULATED_CMPXCHG=y +CONFIG_SUN_PM=y +# CONFIG_SUN4 is not set +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_NO_DMA is not set +CONFIG_SUN_OPENPROMFS=m +# CONFIG_SPARC_LED is not set +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=m CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_SUN_PM=y -# CONFIG_SPARC_LED is not set -CONFIG_SERIAL_CONSOLE=y # -# Bus options (PCI etc.) +# Networking # -CONFIG_SBUS=y -CONFIG_SBUSCHAR=y -CONFIG_PCI=y -CONFIG_PCI_SYSCALL=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_STUB is not set -# CONFIG_PCCARD is not set -CONFIG_SUN_OPENPROMFS=m -CONFIG_SPARC32_PCI=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -CONFIG_BINFMT_MISC=m CONFIG_NET=y # # Networking options # -# CONFIG_NET_NS is not set -CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -185,7 +166,6 @@ CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=y CONFIG_NET_KEY=m # CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y @@ -241,7 +221,6 @@ CONFIG_IPV6_TUNNEL=m # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -252,7 +231,6 @@ CONFIG_IPV6_TUNNEL=m # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -263,14 +241,14 @@ CONFIG_NET_PKTGEN=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set -CONFIG_WIRELESS=y + +# +# Wireless +# # CONFIG_CFG80211 is not set -CONFIG_WIRELESS_OLD_REGULATORY=y # CONFIG_WIRELESS_EXT is not set -# CONFIG_LIB80211 is not set # CONFIG_MAC80211 is not set -# CONFIG_WIMAX is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -284,9 +262,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -310,15 +286,12 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_C2PORT is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -362,7 +335,6 @@ CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_CXGB3_ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_ACARD is not set @@ -376,8 +348,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_HPTIOP is not set -# CONFIG_LIBFC is not set -# CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set @@ -397,7 +367,6 @@ CONFIG_SCSI_QLOGICPTI=m # CONFIG_SCSI_DEBUG is not set CONFIG_SCSI_SUNESP=y # CONFIG_SCSI_SRP is not set -# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_FUSION is not set @@ -405,14 +374,11 @@ CONFIG_SCSI_SUNESP=y # # IEEE 1394 (FireWire) support # - -# -# Enable only one of the two stacks, unless you know what you are doing -# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set CONFIG_DUMMY=m # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -436,16 +402,14 @@ CONFIG_SUNQE=m # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set -# CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_MYRI_SBUS is not set @@ -461,25 +425,18 @@ CONFIG_NETDEV_1000=y # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_JME is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_CHELSIO_T3 is not set -# CONFIG_ENIC is not set # CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_NIU is not set -# CONFIG_MLX4_EN is not set # CONFIG_MLX4_CORE is not set # CONFIG_TEHUTI is not set # CONFIG_BNX2X is not set -# CONFIG_QLGE is not set -# CONFIG_SFC is not set # CONFIG_TR is not set # @@ -488,10 +445,6 @@ CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -539,11 +492,9 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=m # CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -565,18 +516,15 @@ CONFIG_SERIO_LIBPS2=m # Character devices # CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set # # Serial drivers # -# CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support @@ -592,20 +540,23 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m +CONFIG_JS_RTC=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set + +# +# SPI support +# # CONFIG_SPI is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set +# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y @@ -626,38 +577,25 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # @@ -678,17 +616,15 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_PROM_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set -# CONFIG_HID_PID is not set - -# -# Special HID drivers -# -CONFIG_HID_COMPAT=y CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -696,70 +632,31 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set # -# Enable Host or Gadget support to see Inventra options -# - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -CONFIG_RTC_DRV_M48T59=y -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set +# CONFIG_RTC_CLASS is not set # CONFIG_UIO is not set -# CONFIG_STAGING is not set # # Misc Linux/SPARC drivers # CONFIG_SUN_OPENPROMIO=m +CONFIG_SUN_MOSTEK_RTC=m +# CONFIG_SUN_BPP is not set +# CONFIG_SUN_VIDEOPIX is not set # CONFIG_TADPOLE_TS102_UCTRL is not set # CONFIG_SUN_JSFLASH is not set +# +# Unix98 PTY support +# +CONFIG_UNIX98_PTY_COUNT=256 + # # File systems # @@ -769,12 +666,11 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -806,12 +702,14 @@ CONFIG_ISO9660_FS=m CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -822,7 +720,6 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set CONFIG_ROMFS_FS=m @@ -832,13 +729,13 @@ CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set # CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -909,12 +806,9 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set @@ -928,59 +822,37 @@ CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set -CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set - -# -# Tracers -# -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y +CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB_SERIAL_CONSOLE=y CONFIG_KGDB_TESTS=y # CONFIG_KGDB_TESTS_ON_BOOT is not set # CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_STACK_DEBUG is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set CONFIG_CRYPTO_NULL=m # CONFIG_CRYPTO_CRYPTD is not set @@ -1018,10 +890,6 @@ CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m @@ -1053,21 +921,15 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # CONFIG_CRYPTO_DEFLATE=y # CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set diff --git a/trunk/arch/sparc/include/asm/oplib_32.h b/trunk/arch/sparc/include/asm/oplib_32.h index 33e31ce6b31f..73d45521db04 100644 --- a/trunk/arch/sparc/include/asm/oplib_32.h +++ b/trunk/arch/sparc/include/asm/oplib_32.h @@ -177,6 +177,17 @@ extern void prom_putsegment(int context, unsigned long virt_addr, /* PROM device tree traversal functions... */ +#ifdef PROMLIB_INTERNAL + +/* Internal version of prom_getchild. */ +extern int __prom_getchild(int parent_node); + +/* Internal version of prom_getsibling. */ +extern int __prom_getsibling(int node); + +#endif + + /* Get the child node of the given node, or zero if no child exists. */ extern int prom_getchild(int parent_node); diff --git a/trunk/arch/sparc/include/asm/oplib_64.h b/trunk/arch/sparc/include/asm/oplib_64.h index a5db0317b5fb..6d2c2ca98039 100644 --- a/trunk/arch/sparc/include/asm/oplib_64.h +++ b/trunk/arch/sparc/include/asm/oplib_64.h @@ -218,6 +218,16 @@ extern void prom_unmap(unsigned long size, unsigned long vaddr); /* PROM device tree traversal functions... */ +#ifdef PROMLIB_INTERNAL + +/* Internal version of prom_getchild. */ +extern int __prom_getchild(int parent_node); + +/* Internal version of prom_getsibling. */ +extern int __prom_getsibling(int node); + +#endif + /* Get the child node of the given node, or zero if no child exists. */ extern int prom_getchild(int parent_node); diff --git a/trunk/arch/sparc/include/asm/signal.h b/trunk/arch/sparc/include/asm/signal.h index cba45206b7f2..41535e77b255 100644 --- a/trunk/arch/sparc/include/asm/signal.h +++ b/trunk/arch/sparc/include/asm/signal.h @@ -84,11 +84,7 @@ #define __OLD_NSIG 32 #define __NEW_NSIG 64 -#ifdef __arch64__ #define _NSIG_BPW 64 -#else -#define _NSIG_BPW 32 -#endif #define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) #define SIGRTMIN 32 diff --git a/trunk/arch/sparc/include/asm/topology_64.h b/trunk/arch/sparc/include/asm/topology_64.h index 5bc0b8fd6374..b8a65b64e1df 100644 --- a/trunk/arch/sparc/include/asm/topology_64.h +++ b/trunk/arch/sparc/include/asm/topology_64.h @@ -47,10 +47,6 @@ static inline int pcibus_to_node(struct pci_bus *pbus) (pcibus_to_node(bus) == -1 ? \ CPU_MASK_ALL : \ node_to_cpumask(pcibus_to_node(bus))) -#define cpumask_of_pcibus(bus) \ - (pcibus_to_node(bus) == -1 ? \ - CPU_MASK_ALL_PTR : \ - cpumask_of_node(pcibus_to_node(bus))) #define SD_NODE_INIT (struct sched_domain) { \ .min_interval = 8, \ diff --git a/trunk/arch/sparc/kernel/auxio_32.c b/trunk/arch/sparc/kernel/auxio_32.c index 45c41232fc4c..09c857215a52 100644 --- a/trunk/arch/sparc/kernel/auxio_32.c +++ b/trunk/arch/sparc/kernel/auxio_32.c @@ -76,7 +76,6 @@ unsigned char get_auxio(void) return sbus_readb(auxio_register); return 0; } -EXPORT_SYMBOL(get_auxio); void set_auxio(unsigned char bits_on, unsigned char bits_off) { @@ -103,7 +102,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off) }; spin_unlock_irqrestore(&auxio_lock, flags); } -EXPORT_SYMBOL(set_auxio); + /* sun4m power control register (AUXIO2) */ diff --git a/trunk/arch/sparc/kernel/auxio_64.c b/trunk/arch/sparc/kernel/auxio_64.c index 9f52db2d441c..8b67347d4221 100644 --- a/trunk/arch/sparc/kernel/auxio_64.c +++ b/trunk/arch/sparc/kernel/auxio_64.c @@ -72,7 +72,6 @@ void auxio_set_led(int on) bit = (ebus ? AUXIO_PCIO_LED : AUXIO_AUX1_LED); __auxio_set_bit(bit, on, ebus); } -EXPORT_SYMBOL(auxio_set_led); static void __auxio_sbus_set_lte(int on) { @@ -91,7 +90,6 @@ void auxio_set_lte(int on) break; } } -EXPORT_SYMBOL(auxio_set_lte); static struct of_device_id __initdata auxio_match[] = { { diff --git a/trunk/arch/sparc/kernel/cpu.c b/trunk/arch/sparc/kernel/cpu.c index f0b825505da5..6c2da2420f76 100644 --- a/trunk/arch/sparc/kernel/cpu.c +++ b/trunk/arch/sparc/kernel/cpu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -21,7 +20,6 @@ #include "kernel.h" DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; -EXPORT_PER_CPU_SYMBOL(__cpu_data); struct cpu_info { int psr_vers; diff --git a/trunk/arch/sparc/kernel/idprom.c b/trunk/arch/sparc/kernel/idprom.c index 57922f69c3f7..c16135e0c151 100644 --- a/trunk/arch/sparc/kernel/idprom.c +++ b/trunk/arch/sparc/kernel/idprom.c @@ -8,14 +8,11 @@ #include #include #include -#include #include #include struct idprom *idprom; -EXPORT_SYMBOL(idprom); - static struct idprom idprom_buffer; #ifdef CONFIG_SPARC32 diff --git a/trunk/arch/sparc/kernel/ioport.c b/trunk/arch/sparc/kernel/ioport.c index 87ea0d03d975..7ce14f05eb48 100644 --- a/trunk/arch/sparc/kernel/ioport.c +++ b/trunk/arch/sparc/kernel/ioport.c @@ -120,7 +120,6 @@ void __iomem *ioremap(unsigned long offset, unsigned long size) sprintf(name, "phys_%08x", (u32)offset); return _sparc_alloc_io(0, offset, size, name); } -EXPORT_SYMBOL(ioremap); /* * Comlimentary to ioremap(). @@ -142,7 +141,6 @@ void iounmap(volatile void __iomem *virtual) kfree(res); } } -EXPORT_SYMBOL(iounmap); void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name) @@ -239,7 +237,6 @@ void sbus_set_sbus64(struct device *dev, int x) { printk("sbus_set_sbus64: unsupported\n"); } -EXPORT_SYMBOL(sbus_set_sbus64); /* * Allocate a chunk of memory suitable for DMA. @@ -439,7 +436,6 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t len, dma_addr_t *pba) *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ return (void *) res->start; } -EXPORT_SYMBOL(pci_alloc_consistent); /* Free and unmap a consistent DMA buffer. * cpu_addr is what was returned from pci_alloc_consistent, @@ -481,7 +477,6 @@ void pci_free_consistent(struct pci_dev *pdev, size_t n, void *p, dma_addr_t ba) free_pages(pgp, get_order(n)); } -EXPORT_SYMBOL(pci_free_consistent); /* Map a single buffer of the indicated size for DMA in streaming mode. * The 32-bit bus address to use is returned. @@ -496,7 +491,6 @@ dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, /* IIep is write-through, not flushing. */ return virt_to_phys(ptr); } -EXPORT_SYMBOL(pci_map_single); /* Unmap a single streaming mode DMA translation. The dma_addr and size * must match what was provided for in a previous pci_map_single call. All @@ -514,7 +508,6 @@ void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t ba, size_t size, (size + PAGE_SIZE-1) & PAGE_MASK); } } -EXPORT_SYMBOL(pci_unmap_single); /* * Same as pci_map_single, but with pages. @@ -526,7 +519,6 @@ dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page, /* IIep is write-through, not flushing. */ return page_to_phys(page) + offset; } -EXPORT_SYMBOL(pci_map_page); void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, size_t size, int direction) @@ -534,7 +526,6 @@ void pci_unmap_page(struct pci_dev *hwdev, BUG_ON(direction == PCI_DMA_NONE); /* mmu_inval_dma_area XXX */ } -EXPORT_SYMBOL(pci_unmap_page); /* Map a set of buffers described by scatterlist in streaming * mode for DMA. This is the scather-gather version of the @@ -566,7 +557,6 @@ int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, } return nents; } -EXPORT_SYMBOL(pci_map_sg); /* Unmap a set of streaming mode DMA translations. * Again, cpu read rules concerning calls here are the same as for @@ -588,7 +578,6 @@ void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, } } } -EXPORT_SYMBOL(pci_unmap_sg); /* Make physical memory consistent for a single * streaming mode DMA translation before or after a transfer. @@ -608,7 +597,6 @@ void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t ba, size_t si (size + PAGE_SIZE-1) & PAGE_MASK); } } -EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction) { @@ -618,7 +606,6 @@ void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t (size + PAGE_SIZE-1) & PAGE_MASK); } } -EXPORT_SYMBOL(pci_dma_sync_single_for_device); /* Make physical memory consistent for a set of streaming * mode DMA translations after a transfer. @@ -641,7 +628,6 @@ void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sgl, int } } } -EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction) { @@ -658,7 +644,6 @@ void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, } } } -EXPORT_SYMBOL(pci_dma_sync_sg_for_device); #endif /* CONFIG_PCI */ #ifdef CONFIG_PROC_FS diff --git a/trunk/arch/sparc/kernel/irq_32.c b/trunk/arch/sparc/kernel/irq_32.c index 44dd5ee64339..1eff942fe22f 100644 --- a/trunk/arch/sparc/kernel/irq_32.c +++ b/trunk/arch/sparc/kernel/irq_32.c @@ -294,7 +294,6 @@ void synchronize_irq(unsigned int irq) while (sparc_irq[cpu_irq].flags & SPARC_IRQ_INPROGRESS) cpu_relax(); } -EXPORT_SYMBOL(synchronize_irq); #endif /* SMP */ void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs) diff --git a/trunk/arch/sparc/kernel/pci.c b/trunk/arch/sparc/kernel/pci.c index 4638fba799e4..923e9bbb9fe2 100644 --- a/trunk/arch/sparc/kernel/pci.c +++ b/trunk/arch/sparc/kernel/pci.c @@ -1077,7 +1077,6 @@ int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) return (device_mask & dma_addr_mask) == dma_addr_mask; } -EXPORT_SYMBOL(pci_dma_supported); void pci_resource_to_user(const struct pci_dev *pdev, int bar, const struct resource *rp, resource_size_t *start, diff --git a/trunk/arch/sparc/kernel/pcic.c b/trunk/arch/sparc/kernel/pcic.c index 85e7037429b9..75ed98be3edf 100644 --- a/trunk/arch/sparc/kernel/pcic.c +++ b/trunk/arch/sparc/kernel/pcic.c @@ -956,7 +956,6 @@ void outsb(unsigned long addr, const void *src, unsigned long count) /* addr += 1; */ } } -EXPORT_SYMBOL(outsb); void outsw(unsigned long addr, const void *src, unsigned long count) { @@ -967,7 +966,6 @@ void outsw(unsigned long addr, const void *src, unsigned long count) /* addr += 2; */ } } -EXPORT_SYMBOL(outsw); void outsl(unsigned long addr, const void *src, unsigned long count) { @@ -978,7 +976,6 @@ void outsl(unsigned long addr, const void *src, unsigned long count) /* addr += 4; */ } } -EXPORT_SYMBOL(outsl); void insb(unsigned long addr, void *dst, unsigned long count) { @@ -989,7 +986,6 @@ void insb(unsigned long addr, void *dst, unsigned long count) /* addr += 1; */ } } -EXPORT_SYMBOL(insb); void insw(unsigned long addr, void *dst, unsigned long count) { @@ -1000,7 +996,6 @@ void insw(unsigned long addr, void *dst, unsigned long count) /* addr += 2; */ } } -EXPORT_SYMBOL(insw); void insl(unsigned long addr, void *dst, unsigned long count) { @@ -1014,6 +1009,5 @@ void insl(unsigned long addr, void *dst, unsigned long count) /* addr += 4; */ } } -EXPORT_SYMBOL(insl); subsys_initcall(pcic_init); diff --git a/trunk/arch/sparc/kernel/process_32.c b/trunk/arch/sparc/kernel/process_32.c index f4bee35a1b46..5a8d8ced33da 100644 --- a/trunk/arch/sparc/kernel/process_32.c +++ b/trunk/arch/sparc/kernel/process_32.c @@ -44,7 +44,6 @@ * Set in pm platform drivers (apc.c and pmc.c) */ void (*pm_idle)(void); -EXPORT_SYMBOL(pm_idle); /* * Power-off handler instantiation for pm.h compliance @@ -674,7 +673,6 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) "g1", "g2", "g3", "o0", "o1", "memory", "cc"); return retval; } -EXPORT_SYMBOL(kernel_thread); unsigned long get_wchan(struct task_struct *task) { diff --git a/trunk/arch/sparc/kernel/process_64.c b/trunk/arch/sparc/kernel/process_64.c index cc8b5604442c..d5e2acef9877 100644 --- a/trunk/arch/sparc/kernel/process_64.c +++ b/trunk/arch/sparc/kernel/process_64.c @@ -678,7 +678,6 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) "g1", "g2", "g3", "o0", "o1", "memory", "cc"); return retval; } -EXPORT_SYMBOL(kernel_thread); typedef struct { union { @@ -744,7 +743,6 @@ int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs) } return 1; } -EXPORT_SYMBOL(dump_fpu); /* * sparc_execve() executes a new program after the asm stub has set diff --git a/trunk/arch/sparc/kernel/psycho_common.c b/trunk/arch/sparc/kernel/psycho_common.c index 8f1478475421..40689ae3c9b0 100644 --- a/trunk/arch/sparc/kernel/psycho_common.c +++ b/trunk/arch/sparc/kernel/psycho_common.c @@ -11,19 +11,19 @@ #include "iommu_common.h" #include "psycho_common.h" -#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002ULL -#define PSYCHO_STCERR_WRITE 0x0000000000000002ULL -#define PSYCHO_STCERR_READ 0x0000000000000001ULL -#define PSYCHO_STCTAG_PPN 0x0fffffff00000000ULL -#define PSYCHO_STCTAG_VPN 0x00000000ffffe000ULL -#define PSYCHO_STCTAG_VALID 0x0000000000000002ULL -#define PSYCHO_STCTAG_WRITE 0x0000000000000001ULL -#define PSYCHO_STCLINE_LINDX 0x0000000001e00000ULL -#define PSYCHO_STCLINE_SPTR 0x00000000001f8000ULL -#define PSYCHO_STCLINE_LADDR 0x0000000000007f00ULL -#define PSYCHO_STCLINE_EPTR 0x00000000000000fcULL -#define PSYCHO_STCLINE_VALID 0x0000000000000002ULL -#define PSYCHO_STCLINE_FOFN 0x0000000000000001ULL +#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL +#define PSYCHO_STCERR_WRITE 0x0000000000000002UL +#define PSYCHO_STCERR_READ 0x0000000000000001UL +#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL +#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL +#define PSYCHO_STCTAG_VALID 0x0000000000000002UL +#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL +#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL +#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL +#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL +#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL +#define PSYCHO_STCLINE_VALID 0x0000000000000002UL +#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL static DEFINE_SPINLOCK(stc_buf_lock); static unsigned long stc_error_buf[128]; @@ -144,10 +144,10 @@ static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm, #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) -#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffULL +#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) -#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL +#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, u64 *tag, u64 *data) @@ -190,7 +190,7 @@ static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, pbm->name, i, ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), - (data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); + (data_val & PSYCHO_IOMMU_DATA_PPAGE)< #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PCI +#include +#endif +#include +#ifdef CONFIG_HIGHMEM +#include +#endif -#include -#include +#include #include +#include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include +#ifdef CONFIG_SBUS #include +#endif +#include +#include + +extern spinlock_t rtc_lock; struct poll { int fd; @@ -20,15 +55,72 @@ struct poll { short revents; }; -/* from entry.S */ +extern void (*__copy_1page)(void *, const void *); +extern void __memmove(void *, const void *, __kernel_size_t); +extern void (*bzero_1page)(void *); +extern void *__bzero(void *, size_t); +extern void *__memscan_zero(void *, size_t); +extern void *__memscan_generic(void *, int, size_t); +extern int __strncmp(const char *, const char *, __kernel_size_t); + +extern int __ashrdi3(int, int); +extern int __ashldi3(int, int); +extern int __lshrdi3(int, int); +extern int __muldi3(int, int); +extern int __divdi3(int, int); + +/* Private functions with odd calling conventions. */ +extern void ___atomic24_add(void); +extern void ___atomic24_sub(void); +extern void ___rw_read_enter(void); +extern void ___rw_read_try(void); +extern void ___rw_read_exit(void); +extern void ___rw_write_enter(void); + +/* Alias functions whose names begin with "." and export the aliases. + * The module references will be fixed up by module_frob_arch_sections. + */ +extern int _Div(int, int); +extern int _Mul(int, int); +extern int _Rem(int, int); +extern unsigned _Udiv(unsigned, unsigned); +extern unsigned _Umul(unsigned, unsigned); +extern unsigned _Urem(unsigned, unsigned); + +/* used by various drivers */ +EXPORT_SYMBOL(sparc_cpu_model); +EXPORT_SYMBOL(kernel_thread); +#ifdef CONFIG_SMP +// XXX find what uses (or used) these. AV: see asm/spinlock.h +EXPORT_SYMBOL(___rw_read_enter); +EXPORT_SYMBOL(___rw_read_try); +EXPORT_SYMBOL(___rw_read_exit); +EXPORT_SYMBOL(___rw_write_enter); +#endif + +EXPORT_SYMBOL(sparc_valid_addr_bitmap); +EXPORT_SYMBOL(phys_base); +EXPORT_SYMBOL(pfn_base); + +/* Atomic operations. */ +EXPORT_SYMBOL(___atomic24_add); +EXPORT_SYMBOL(___atomic24_sub); + +/* Per-CPU information table */ +EXPORT_PER_CPU_SYMBOL(__cpu_data); + +#ifdef CONFIG_SMP +/* IRQ implementation. */ +EXPORT_SYMBOL(synchronize_irq); +#endif + EXPORT_SYMBOL(__udelay); EXPORT_SYMBOL(__ndelay); +EXPORT_SYMBOL(rtc_lock); +EXPORT_SYMBOL(set_auxio); +EXPORT_SYMBOL(get_auxio); +EXPORT_SYMBOL(io_remap_pfn_range); -/* from head_32.S */ -EXPORT_SYMBOL(__ret_efault); -EXPORT_SYMBOL(empty_zero_page); - -/* Defined using magic */ #ifndef CONFIG_SMP EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); #else @@ -40,7 +132,122 @@ EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl)); EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one)); EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl)); EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one)); + EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); -/* Exporting a symbol from /init/main.c */ +#ifdef CONFIG_SBUS +EXPORT_SYMBOL(sbus_set_sbus64); +#endif +#ifdef CONFIG_PCI +EXPORT_SYMBOL(insb); +EXPORT_SYMBOL(outsb); +EXPORT_SYMBOL(insw); +EXPORT_SYMBOL(outsw); +EXPORT_SYMBOL(insl); +EXPORT_SYMBOL(outsl); +EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(pci_free_consistent); +EXPORT_SYMBOL(pci_map_single); +EXPORT_SYMBOL(pci_unmap_single); +EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); +EXPORT_SYMBOL(pci_dma_sync_single_for_device); +EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); +EXPORT_SYMBOL(pci_dma_sync_sg_for_device); +EXPORT_SYMBOL(pci_map_sg); +EXPORT_SYMBOL(pci_unmap_sg); +EXPORT_SYMBOL(pci_map_page); +EXPORT_SYMBOL(pci_unmap_page); +/* Actually, ioremap/iounmap are not PCI specific. But it is ok for drivers. */ +EXPORT_SYMBOL(ioremap); +EXPORT_SYMBOL(iounmap); +#endif + +/* in arch/sparc/mm/highmem.c */ +#ifdef CONFIG_HIGHMEM +EXPORT_SYMBOL(kmap_atomic); +EXPORT_SYMBOL(kunmap_atomic); +#endif + +/* prom symbols */ +EXPORT_SYMBOL(idprom); +EXPORT_SYMBOL(prom_root_node); +EXPORT_SYMBOL(prom_getchild); +EXPORT_SYMBOL(prom_getsibling); +EXPORT_SYMBOL(prom_searchsiblings); +EXPORT_SYMBOL(prom_firstprop); +EXPORT_SYMBOL(prom_nextprop); +EXPORT_SYMBOL(prom_getproplen); +EXPORT_SYMBOL(prom_getproperty); +EXPORT_SYMBOL(prom_node_has_property); +EXPORT_SYMBOL(prom_setprop); EXPORT_SYMBOL(saved_command_line); +EXPORT_SYMBOL(prom_apply_obio_ranges); +EXPORT_SYMBOL(prom_feval); +EXPORT_SYMBOL(prom_getbool); +EXPORT_SYMBOL(prom_getstring); +EXPORT_SYMBOL(prom_getint); +EXPORT_SYMBOL(prom_getintdefault); +EXPORT_SYMBOL(prom_finddevice); +EXPORT_SYMBOL(romvec); +EXPORT_SYMBOL(__prom_getchild); +EXPORT_SYMBOL(__prom_getsibling); + +/* sparc library symbols */ +EXPORT_SYMBOL(memscan); +EXPORT_SYMBOL(strlen); +EXPORT_SYMBOL(strncmp); +EXPORT_SYMBOL(page_kernel); + +/* Special internal versions of library functions. */ +EXPORT_SYMBOL(__copy_1page); +EXPORT_SYMBOL(__memcpy); +EXPORT_SYMBOL(__memset); +EXPORT_SYMBOL(bzero_1page); +EXPORT_SYMBOL(__bzero); +EXPORT_SYMBOL(__memscan_zero); +EXPORT_SYMBOL(__memscan_generic); +EXPORT_SYMBOL(__strncmp); +EXPORT_SYMBOL(__memmove); + +/* Moving data to/from userspace. */ +EXPORT_SYMBOL(__copy_user); +EXPORT_SYMBOL(__strncpy_from_user); +EXPORT_SYMBOL(__strnlen_user); + +/* Networking helper routines. */ +EXPORT_SYMBOL(__csum_partial_copy_sparc_generic); +EXPORT_SYMBOL(csum_partial); + +/* Cache flushing. */ +EXPORT_SYMBOL(sparc_flush_page_to_ram); + +/* For when serial stuff is built as modules. */ +EXPORT_SYMBOL(sun_do_break); + +EXPORT_SYMBOL(__ret_efault); + +EXPORT_SYMBOL(memcmp); +EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memset); +EXPORT_SYMBOL(memmove); +EXPORT_SYMBOL(__ashrdi3); +EXPORT_SYMBOL(__ashldi3); +EXPORT_SYMBOL(__lshrdi3); +EXPORT_SYMBOL(__muldi3); +EXPORT_SYMBOL(__divdi3); + +EXPORT_SYMBOL(_Rem); +EXPORT_SYMBOL(_Urem); +EXPORT_SYMBOL(_Mul); +EXPORT_SYMBOL(_Umul); +EXPORT_SYMBOL(_Div); +EXPORT_SYMBOL(_Udiv); + +#ifdef CONFIG_DEBUG_BUGVERBOSE +EXPORT_SYMBOL(do_BUG); +#endif + +/* Sun Power Management Idle Handler */ +EXPORT_SYMBOL(pm_idle); + +EXPORT_SYMBOL(empty_zero_page); diff --git a/trunk/arch/sparc/kernel/sparc_ksyms_64.c b/trunk/arch/sparc/kernel/sparc_ksyms_64.c index da8f804feb49..0133211ab634 100644 --- a/trunk/arch/sparc/kernel/sparc_ksyms_64.c +++ b/trunk/arch/sparc/kernel/sparc_ksyms_64.c @@ -5,16 +5,50 @@ * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) */ +/* Tell string.h we don't want memcpy etc. as cpp defines */ +#define EXPORT_SYMTAB_STROPS +#define PROMLIB_INTERNAL + #include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include #include +#include +#include -#include +#include #include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include -#include +#include +#include +#include +#include +#ifdef CONFIG_SBUS +#include +#endif +#include +#include +#include +#include #include struct poll { @@ -23,6 +57,42 @@ struct poll { short revents; }; +extern void die_if_kernel(char *str, struct pt_regs *regs); +extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); +extern void *__bzero(void *, size_t); +extern void *__memscan_zero(void *, size_t); +extern void *__memscan_generic(void *, int, size_t); +extern __kernel_size_t strlen(const char *); +extern void sys_sigsuspend(void); +extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg); +extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *); +extern long sparc32_open(const char __user * filename, int flags, int mode); +extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, + unsigned long pfn, unsigned long size, pgprot_t prot); + +extern int __ashrdi3(int, int); + +extern int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs); + +extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *); +extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *, + unsigned long *); +extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *, + unsigned long *, unsigned long *); +extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *, + unsigned long *, unsigned long *, unsigned long *); + +extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *); +extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *, + unsigned long *); +extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *, + unsigned long *, unsigned long *); +extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *, + unsigned long *, unsigned long *, unsigned long *); + +/* Per-CPU information table */ +EXPORT_PER_CPU_SYMBOL(__cpu_data); + /* used by various drivers */ #ifdef CONFIG_SMP /* Out of line rw-locking implementation. */ @@ -33,24 +103,68 @@ EXPORT_SYMBOL(__write_unlock); EXPORT_SYMBOL(__write_trylock); #endif /* CONFIG_SMP */ -/* from helpers.S */ +#ifdef CONFIG_MCOUNT +EXPORT_SYMBOL(_mcount); +#endif + +EXPORT_SYMBOL(sparc64_get_clock_tick); + +/* RW semaphores */ +EXPORT_SYMBOL(__down_read); +EXPORT_SYMBOL(__down_read_trylock); +EXPORT_SYMBOL(__down_write); +EXPORT_SYMBOL(__down_write_trylock); +EXPORT_SYMBOL(__up_read); +EXPORT_SYMBOL(__up_write); +EXPORT_SYMBOL(__downgrade_write); + +/* Atomic counter implementation. */ +EXPORT_SYMBOL(atomic_add); +EXPORT_SYMBOL(atomic_add_ret); +EXPORT_SYMBOL(atomic_sub); +EXPORT_SYMBOL(atomic_sub_ret); +EXPORT_SYMBOL(atomic64_add); +EXPORT_SYMBOL(atomic64_add_ret); +EXPORT_SYMBOL(atomic64_sub); +EXPORT_SYMBOL(atomic64_sub_ret); + +/* Atomic bit operations. */ +EXPORT_SYMBOL(test_and_set_bit); +EXPORT_SYMBOL(test_and_clear_bit); +EXPORT_SYMBOL(test_and_change_bit); +EXPORT_SYMBOL(set_bit); +EXPORT_SYMBOL(clear_bit); +EXPORT_SYMBOL(change_bit); + EXPORT_SYMBOL(__flushw_user); -EXPORT_SYMBOL_GPL(real_hard_smp_processor_id); -/* from head_64.S */ -EXPORT_SYMBOL(__ret_efault); EXPORT_SYMBOL(tlb_type); EXPORT_SYMBOL(sun4v_chip_type); -EXPORT_SYMBOL(prom_root_node); +EXPORT_SYMBOL(get_fb_unmapped_area); +EXPORT_SYMBOL(flush_icache_range); + +EXPORT_SYMBOL(flush_dcache_page); +#ifdef DCACHE_ALIASING_POSSIBLE +EXPORT_SYMBOL(__flush_dcache_range); +#endif -/* from hvcalls.S */ EXPORT_SYMBOL(sun4v_niagara_getperf); EXPORT_SYMBOL(sun4v_niagara_setperf); EXPORT_SYMBOL(sun4v_niagara2_getperf); EXPORT_SYMBOL(sun4v_niagara2_setperf); +EXPORT_SYMBOL(auxio_set_led); +EXPORT_SYMBOL(auxio_set_lte); +#ifdef CONFIG_SBUS +EXPORT_SYMBOL(sbus_set_sbus64); +#endif +EXPORT_SYMBOL(outsb); +EXPORT_SYMBOL(outsw); +EXPORT_SYMBOL(outsl); +EXPORT_SYMBOL(insb); +EXPORT_SYMBOL(insw); +EXPORT_SYMBOL(insl); #ifdef CONFIG_PCI -/* inline functions in asm/pci_64.h */ EXPORT_SYMBOL(pci_alloc_consistent); EXPORT_SYMBOL(pci_free_consistent); EXPORT_SYMBOL(pci_map_single); @@ -59,7 +173,112 @@ EXPORT_SYMBOL(pci_map_sg); EXPORT_SYMBOL(pci_unmap_sg); EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); +EXPORT_SYMBOL(pci_dma_supported); #endif -/* Exporting a symbol from /init/main.c */ +/* I/O device mmaping on Sparc64. */ +EXPORT_SYMBOL(io_remap_pfn_range); + +EXPORT_SYMBOL(dump_fpu); + +/* math-emu wants this */ +EXPORT_SYMBOL(die_if_kernel); + +/* Kernel thread creation. */ +EXPORT_SYMBOL(kernel_thread); + +/* prom symbols */ +EXPORT_SYMBOL(idprom); +EXPORT_SYMBOL(prom_root_node); +EXPORT_SYMBOL(prom_getchild); +EXPORT_SYMBOL(prom_getsibling); +EXPORT_SYMBOL(prom_searchsiblings); +EXPORT_SYMBOL(prom_firstprop); +EXPORT_SYMBOL(prom_nextprop); +EXPORT_SYMBOL(prom_getproplen); +EXPORT_SYMBOL(prom_getproperty); +EXPORT_SYMBOL(prom_node_has_property); +EXPORT_SYMBOL(prom_setprop); EXPORT_SYMBOL(saved_command_line); +EXPORT_SYMBOL(prom_finddevice); +EXPORT_SYMBOL(prom_feval); +EXPORT_SYMBOL(prom_getbool); +EXPORT_SYMBOL(prom_getstring); +EXPORT_SYMBOL(prom_getint); +EXPORT_SYMBOL(prom_getintdefault); +EXPORT_SYMBOL(__prom_getchild); +EXPORT_SYMBOL(__prom_getsibling); + +/* sparc library symbols */ +EXPORT_SYMBOL(strlen); +EXPORT_SYMBOL(__strlen_user); +EXPORT_SYMBOL(__strnlen_user); + +/* Special internal versions of library functions. */ +EXPORT_SYMBOL(_clear_page); +EXPORT_SYMBOL(clear_user_page); +EXPORT_SYMBOL(copy_user_page); +EXPORT_SYMBOL(__bzero); +EXPORT_SYMBOL(__memscan_zero); +EXPORT_SYMBOL(__memscan_generic); +EXPORT_SYMBOL(__memset); + +EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_nocheck); +EXPORT_SYMBOL(__csum_partial_copy_from_user); +EXPORT_SYMBOL(__csum_partial_copy_to_user); +EXPORT_SYMBOL(ip_fast_csum); + +/* Moving data to/from/in userspace. */ +EXPORT_SYMBOL(___copy_to_user); +EXPORT_SYMBOL(___copy_from_user); +EXPORT_SYMBOL(___copy_in_user); +EXPORT_SYMBOL(copy_to_user_fixup); +EXPORT_SYMBOL(copy_from_user_fixup); +EXPORT_SYMBOL(copy_in_user_fixup); +EXPORT_SYMBOL(__strncpy_from_user); +EXPORT_SYMBOL(__clear_user); + +/* Various address conversion macros use this. */ +EXPORT_SYMBOL(sparc64_valid_addr_bitmap); + +/* No version information on this, heavily used in inline asm, + * and will always be 'void __ret_efault(void)'. + */ +EXPORT_SYMBOL(__ret_efault); + +/* No version information on these, as gcc produces such symbols. */ +EXPORT_SYMBOL(memcmp); +EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memset); +EXPORT_SYMBOL(memmove); +EXPORT_SYMBOL(strncmp); + +void VISenter(void); +/* RAID code needs this */ +EXPORT_SYMBOL(VISenter); + +/* for input/keybdev */ +EXPORT_SYMBOL(sun_do_break); +EXPORT_SYMBOL(stop_a_enabled); + +#ifdef CONFIG_DEBUG_BUGVERBOSE +EXPORT_SYMBOL(do_BUG); +#endif + +/* for ns8703 */ +EXPORT_SYMBOL(ns87303_lock); + +EXPORT_SYMBOL(tick_ops); + +EXPORT_SYMBOL(xor_vis_2); +EXPORT_SYMBOL(xor_vis_3); +EXPORT_SYMBOL(xor_vis_4); +EXPORT_SYMBOL(xor_vis_5); + +EXPORT_SYMBOL(xor_niagara_2); +EXPORT_SYMBOL(xor_niagara_3); +EXPORT_SYMBOL(xor_niagara_4); +EXPORT_SYMBOL(xor_niagara_5); + +EXPORT_SYMBOL_GPL(real_hard_smp_processor_id); diff --git a/trunk/arch/sparc/kernel/sun4d_smp.c b/trunk/arch/sparc/kernel/sun4d_smp.c index 50afaed99c8a..16ab0cb731c5 100644 --- a/trunk/arch/sparc/kernel/sun4d_smp.c +++ b/trunk/arch/sparc/kernel/sun4d_smp.c @@ -60,7 +60,7 @@ extern int __smp4d_processor_id(void); #define SMP_PRINTK(x) #endif -static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) +static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) { __asm__ __volatile__("swap [%1], %0\n\t" : "=&r" (val), "=&r" (ptr) : @@ -115,7 +115,7 @@ void __cpuinit smp4d_callin(void) local_flush_tlb_all(); /* Allow master to continue. */ - sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); + swap((unsigned long *)&cpu_callin_map[cpuid], 1); local_flush_cache_all(); local_flush_tlb_all(); diff --git a/trunk/arch/sparc/kernel/sys_sparc_64.c b/trunk/arch/sparc/kernel/sys_sparc_64.c index 09058fc39e73..39749e32dc7e 100644 --- a/trunk/arch/sparc/kernel/sys_sparc_64.c +++ b/trunk/arch/sparc/kernel/sys_sparc_64.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -355,7 +354,6 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u return addr; } -EXPORT_SYMBOL(get_fb_unmapped_area); /* Essentially the same as PowerPC... */ void arch_pick_mmap_layout(struct mm_struct *mm) diff --git a/trunk/arch/sparc/kernel/time_32.c b/trunk/arch/sparc/kernel/time_32.c index 614ac7b4a9dd..00f7383c7657 100644 --- a/trunk/arch/sparc/kernel/time_32.c +++ b/trunk/arch/sparc/kernel/time_32.c @@ -48,8 +48,6 @@ #include "irq.h" DEFINE_SPINLOCK(rtc_lock); -EXPORT_SYMBOL(rtc_lock); - static int set_rtc_mmss(unsigned long); static int sbus_do_settimeofday(struct timespec *tv); diff --git a/trunk/arch/sparc/kernel/time_64.c b/trunk/arch/sparc/kernel/time_64.c index db310aa00183..54405d362148 100644 --- a/trunk/arch/sparc/kernel/time_64.c +++ b/trunk/arch/sparc/kernel/time_64.c @@ -176,7 +176,6 @@ static struct sparc64_tick_ops tick_operations __read_mostly = { }; struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; -EXPORT_SYMBOL(tick_ops); static void stick_disable_irq(void) { @@ -640,7 +639,6 @@ unsigned long sparc64_get_clock_tick(unsigned int cpu) return ft->clock_tick_ref; return cpu_data(cpu).clock_tick; } -EXPORT_SYMBOL(sparc64_get_clock_tick); #ifdef CONFIG_CPU_FREQ @@ -729,7 +727,7 @@ void timer_interrupt(int irq, struct pt_regs *regs) irq_enter(); - kstat_incr_irqs_this_cpu(0, irq_to_desc(0)); + kstat_this_cpu.irqs[0]++; if (unlikely(!evt->event_handler)) { printk(KERN_WARNING diff --git a/trunk/arch/sparc/kernel/traps_32.c b/trunk/arch/sparc/kernel/traps_32.c index 358283341b47..213645be6e92 100644 --- a/trunk/arch/sparc/kernel/traps_32.c +++ b/trunk/arch/sparc/kernel/traps_32.c @@ -424,7 +424,6 @@ void do_BUG(const char *file, int line) // bust_spinlocks(1); XXX Not in our original BUG() printk("kernel BUG at %s:%d!\n", file, line); } -EXPORT_SYMBOL(do_BUG); #endif /* Since we have our mappings set up, on multiprocessors we can spin them diff --git a/trunk/arch/sparc/kernel/traps_64.c b/trunk/arch/sparc/kernel/traps_64.c index c2d153d46586..bca3b4e09c41 100644 --- a/trunk/arch/sparc/kernel/traps_64.c +++ b/trunk/arch/sparc/kernel/traps_64.c @@ -128,7 +128,6 @@ void do_BUG(const char *file, int line) bust_spinlocks(1); printk("kernel BUG at %s:%d!\n", file, line); } -EXPORT_SYMBOL(do_BUG); #endif static DEFINE_SPINLOCK(dimm_handler_lock); @@ -2262,7 +2261,6 @@ void die_if_kernel(char *str, struct pt_regs *regs) do_exit(SIGKILL); do_exit(SIGSEGV); } -EXPORT_SYMBOL(die_if_kernel); #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) diff --git a/trunk/arch/sparc/kernel/unaligned_64.c b/trunk/arch/sparc/kernel/unaligned_64.c index 379209982a07..f164d5a850f9 100644 --- a/trunk/arch/sparc/kernel/unaligned_64.c +++ b/trunk/arch/sparc/kernel/unaligned_64.c @@ -589,6 +589,7 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr unsigned long pc = regs->tpc; unsigned long tstate = regs->tstate; u32 insn; + u32 first, second; u64 value; u8 freg; int flag; @@ -600,20 +601,19 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr pc = (u32)pc; if (get_user(insn, (u32 __user *) pc) != -EFAULT) { int asi = decode_asi(insn, regs); - u32 first, second; int err; if ((asi > ASI_SNFL) || (asi < ASI_P)) goto daex; - first = second = 0; err = get_user(first, (u32 __user *)sfar); if (!err) err = get_user(second, (u32 __user *)(sfar + 4)); if (err) { - if (!(asi & 0x2)) + if (asi & 0x2) /* NF */ { + first = 0; second = 0; + } else goto daex; - first = second = 0; } save_and_clear_fpu(); freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20); diff --git a/trunk/arch/sparc/lib/Makefile b/trunk/arch/sparc/lib/Makefile index 273fc85269fc..375016e19144 100644 --- a/trunk/arch/sparc/lib/Makefile +++ b/trunk/arch/sparc/lib/Makefile @@ -42,4 +42,3 @@ lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o obj-y += iomap.o obj-$(CONFIG_SPARC32) += atomic32.o -obj-y += ksyms.o diff --git a/trunk/arch/sparc/lib/PeeCeeI.c b/trunk/arch/sparc/lib/PeeCeeI.c index 6529f8657597..46053e6ddd7b 100644 --- a/trunk/arch/sparc/lib/PeeCeeI.c +++ b/trunk/arch/sparc/lib/PeeCeeI.c @@ -4,8 +4,6 @@ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) */ -#include - #include #include @@ -17,7 +15,6 @@ void outsb(unsigned long __addr, const void *src, unsigned long count) while (count--) outb(*p++, addr); } -EXPORT_SYMBOL(outsb); void outsw(unsigned long __addr, const void *src, unsigned long count) { @@ -28,7 +25,6 @@ void outsw(unsigned long __addr, const void *src, unsigned long count) src += sizeof(u16); } } -EXPORT_SYMBOL(outsw); void outsl(unsigned long __addr, const void *src, unsigned long count) { @@ -82,7 +78,6 @@ void outsl(unsigned long __addr, const void *src, unsigned long count) break; } } -EXPORT_SYMBOL(outsl); void insb(unsigned long __addr, void *dst, unsigned long count) { @@ -110,7 +105,6 @@ void insb(unsigned long __addr, void *dst, unsigned long count) *pb++ = inb(addr); } } -EXPORT_SYMBOL(insb); void insw(unsigned long __addr, void *dst, unsigned long count) { @@ -138,7 +132,6 @@ void insw(unsigned long __addr, void *dst, unsigned long count) *ps = le16_to_cpu(inw(addr)); } } -EXPORT_SYMBOL(insw); void insl(unsigned long __addr, void *dst, unsigned long count) { @@ -207,5 +200,4 @@ void insl(unsigned long __addr, void *dst, unsigned long count) } } } -EXPORT_SYMBOL(insl); diff --git a/trunk/arch/sparc/lib/ksyms.c b/trunk/arch/sparc/lib/ksyms.c deleted file mode 100644 index 704b12668388..000000000000 --- a/trunk/arch/sparc/lib/ksyms.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Export of symbols defined in assembler - */ - -/* Tell string.h we don't want memcpy etc. as cpp defines */ -#define EXPORT_SYMTAB_STROPS - -#include -#include -#include - -#include -#include -#include - -/* string functions */ -EXPORT_SYMBOL(strlen); -EXPORT_SYMBOL(__strlen_user); -EXPORT_SYMBOL(__strnlen_user); -EXPORT_SYMBOL(strncmp); - -/* mem* functions */ -extern void *__memscan_zero(void *, size_t); -extern void *__memscan_generic(void *, int, size_t); -extern void *__bzero(void *, size_t); - -EXPORT_SYMBOL(memscan); -EXPORT_SYMBOL(__memscan_zero); -EXPORT_SYMBOL(__memscan_generic); -EXPORT_SYMBOL(memcmp); -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memset); -EXPORT_SYMBOL(__memset); -EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(__bzero); - -/* Moving data to/from/in userspace. */ -EXPORT_SYMBOL(__strncpy_from_user); - -/* Networking helper routines. */ -EXPORT_SYMBOL(csum_partial); - -#ifdef CONFIG_MCOUNT -EXPORT_SYMBOL(_mcount); -#endif - -/* - * sparc - */ -#ifdef CONFIG_SPARC32 -extern int __ashrdi3(int, int); -extern int __ashldi3(int, int); -extern int __lshrdi3(int, int); -extern int __muldi3(int, int); -extern int __divdi3(int, int); - -extern void (*__copy_1page)(void *, const void *); -extern void (*bzero_1page)(void *); - -extern int __strncmp(const char *, const char *, __kernel_size_t); - -extern void ___rw_read_enter(void); -extern void ___rw_read_try(void); -extern void ___rw_read_exit(void); -extern void ___rw_write_enter(void); -extern void ___atomic24_add(void); -extern void ___atomic24_sub(void); - -/* Alias functions whose names begin with "." and export the aliases. - * The module references will be fixed up by module_frob_arch_sections. - */ -extern int _Div(int, int); -extern int _Mul(int, int); -extern int _Rem(int, int); -extern unsigned _Udiv(unsigned, unsigned); -extern unsigned _Umul(unsigned, unsigned); -extern unsigned _Urem(unsigned, unsigned); - -/* Networking helper routines. */ -EXPORT_SYMBOL(__csum_partial_copy_sparc_generic); - -/* Special internal versions of library functions. */ -EXPORT_SYMBOL(__copy_1page); -EXPORT_SYMBOL(__memcpy); -EXPORT_SYMBOL(__memmove); -EXPORT_SYMBOL(bzero_1page); - -/* string functions */ -EXPORT_SYMBOL(__strncmp); - -/* Moving data to/from/in userspace. */ -EXPORT_SYMBOL(__copy_user); - -/* Used by asm/spinlock.h */ -#ifdef CONFIG_SMP -EXPORT_SYMBOL(___rw_read_enter); -EXPORT_SYMBOL(___rw_read_try); -EXPORT_SYMBOL(___rw_read_exit); -EXPORT_SYMBOL(___rw_write_enter); -#endif - -/* Atomic operations. */ -EXPORT_SYMBOL(___atomic24_add); -EXPORT_SYMBOL(___atomic24_sub); - -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__muldi3); -EXPORT_SYMBOL(__divdi3); - -EXPORT_SYMBOL(_Rem); -EXPORT_SYMBOL(_Urem); -EXPORT_SYMBOL(_Mul); -EXPORT_SYMBOL(_Umul); -EXPORT_SYMBOL(_Div); -EXPORT_SYMBOL(_Udiv); -#endif - -/* - * sparc64 - */ -#ifdef CONFIG_SPARC64 -/* Networking helper routines. */ -EXPORT_SYMBOL(csum_partial_copy_nocheck); -EXPORT_SYMBOL(__csum_partial_copy_from_user); -EXPORT_SYMBOL(__csum_partial_copy_to_user); -EXPORT_SYMBOL(ip_fast_csum); - -/* Moving data to/from/in userspace. */ -EXPORT_SYMBOL(___copy_to_user); -EXPORT_SYMBOL(___copy_from_user); -EXPORT_SYMBOL(___copy_in_user); -EXPORT_SYMBOL(__clear_user); - -/* RW semaphores */ -EXPORT_SYMBOL(__down_read); -EXPORT_SYMBOL(__down_read_trylock); -EXPORT_SYMBOL(__down_write); -EXPORT_SYMBOL(__down_write_trylock); -EXPORT_SYMBOL(__up_read); -EXPORT_SYMBOL(__up_write); -EXPORT_SYMBOL(__downgrade_write); - -/* Atomic counter implementation. */ -EXPORT_SYMBOL(atomic_add); -EXPORT_SYMBOL(atomic_add_ret); -EXPORT_SYMBOL(atomic_sub); -EXPORT_SYMBOL(atomic_sub_ret); -EXPORT_SYMBOL(atomic64_add); -EXPORT_SYMBOL(atomic64_add_ret); -EXPORT_SYMBOL(atomic64_sub); -EXPORT_SYMBOL(atomic64_sub_ret); - -/* Atomic bit operations. */ -EXPORT_SYMBOL(test_and_set_bit); -EXPORT_SYMBOL(test_and_clear_bit); -EXPORT_SYMBOL(test_and_change_bit); -EXPORT_SYMBOL(set_bit); -EXPORT_SYMBOL(clear_bit); -EXPORT_SYMBOL(change_bit); - -/* Special internal versions of library functions. */ -EXPORT_SYMBOL(_clear_page); -EXPORT_SYMBOL(clear_user_page); -EXPORT_SYMBOL(copy_user_page); - -/* RAID code needs this */ -void VISenter(void); -EXPORT_SYMBOL(VISenter); - -extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *); -extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *, - unsigned long *); -extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *, - unsigned long *, unsigned long *); -extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *, - unsigned long *, unsigned long *, unsigned long *); -EXPORT_SYMBOL(xor_vis_2); -EXPORT_SYMBOL(xor_vis_3); -EXPORT_SYMBOL(xor_vis_4); -EXPORT_SYMBOL(xor_vis_5); - -extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *); -extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *, - unsigned long *); -extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *, - unsigned long *, unsigned long *); -extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *, - unsigned long *, unsigned long *, unsigned long *); - -EXPORT_SYMBOL(xor_niagara_2); -EXPORT_SYMBOL(xor_niagara_3); -EXPORT_SYMBOL(xor_niagara_4); -EXPORT_SYMBOL(xor_niagara_5); -#endif diff --git a/trunk/arch/sparc/lib/user_fixup.c b/trunk/arch/sparc/lib/user_fixup.c index ac96ae236709..05a361b0a1a4 100644 --- a/trunk/arch/sparc/lib/user_fixup.c +++ b/trunk/arch/sparc/lib/user_fixup.c @@ -7,8 +7,6 @@ #include #include #include -#include - #include /* Calculating the exact fault address when using @@ -42,7 +40,6 @@ unsigned long copy_from_user_fixup(void *to, const void __user *from, unsigned l return size; } -EXPORT_SYMBOL(copy_from_user_fixup); unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size) { @@ -50,7 +47,6 @@ unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned lon return compute_size((unsigned long) to, size, &offset); } -EXPORT_SYMBOL(copy_to_user_fixup); unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size) { @@ -68,4 +64,3 @@ unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned lo return size; } -EXPORT_SYMBOL(copy_in_user_fixup); diff --git a/trunk/arch/sparc/mm/generic_32.c b/trunk/arch/sparc/mm/generic_32.c index 5edcac184eaf..a289261da9fd 100644 --- a/trunk/arch/sparc/mm/generic_32.c +++ b/trunk/arch/sparc/mm/generic_32.c @@ -95,4 +95,3 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, flush_tlb_range(vma, beg, end); return error; } -EXPORT_SYMBOL(io_remap_pfn_range); diff --git a/trunk/arch/sparc/mm/generic_64.c b/trunk/arch/sparc/mm/generic_64.c index 04f2bf4cd571..f362c2037013 100644 --- a/trunk/arch/sparc/mm/generic_64.c +++ b/trunk/arch/sparc/mm/generic_64.c @@ -161,4 +161,3 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from, flush_tlb_range(vma, beg, end); return error; } -EXPORT_SYMBOL(io_remap_pfn_range); diff --git a/trunk/arch/sparc/mm/highmem.c b/trunk/arch/sparc/mm/highmem.c index 752d0c9fb544..01fc6c254292 100644 --- a/trunk/arch/sparc/mm/highmem.c +++ b/trunk/arch/sparc/mm/highmem.c @@ -62,7 +62,6 @@ void *kmap_atomic(struct page *page, enum km_type type) return (void*) vaddr; } -EXPORT_SYMBOL(kmap_atomic); void kunmap_atomic(void *kvaddr, enum km_type type) { @@ -99,7 +98,6 @@ void kunmap_atomic(void *kvaddr, enum km_type type) pagefault_enable(); } -EXPORT_SYMBOL(kunmap_atomic); /* We may be fed a pagetable here by ptep_to_xxx and others. */ struct page *kmap_atomic_to_page(void *ptr) diff --git a/trunk/arch/sparc/mm/init_32.c b/trunk/arch/sparc/mm/init_32.c index cbb282dab5a7..fec926021f49 100644 --- a/trunk/arch/sparc/mm/init_32.c +++ b/trunk/arch/sparc/mm/init_32.c @@ -38,16 +38,11 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); unsigned long *sparc_valid_addr_bitmap; -EXPORT_SYMBOL(sparc_valid_addr_bitmap); unsigned long phys_base; -EXPORT_SYMBOL(phys_base); - unsigned long pfn_base; -EXPORT_SYMBOL(pfn_base); unsigned long page_kernel; -EXPORT_SYMBOL(page_kernel); struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; unsigned long sparc_unmapped_base; @@ -527,4 +522,3 @@ void sparc_flush_page_to_ram(struct page *page) if (vaddr) __flush_page_to_ram(vaddr); } -EXPORT_SYMBOL(sparc_flush_page_to_ram); diff --git a/trunk/arch/sparc/mm/init_64.c b/trunk/arch/sparc/mm/init_64.c index 00373ce2d8fb..c77c7ef5d5d4 100644 --- a/trunk/arch/sparc/mm/init_64.c +++ b/trunk/arch/sparc/mm/init_64.c @@ -146,7 +146,6 @@ static void __init read_obp_memory(const char *property, } unsigned long *sparc64_valid_addr_bitmap __read_mostly; -EXPORT_SYMBOL(sparc64_valid_addr_bitmap); /* Kernel physical address base and size in bytes. */ unsigned long kern_base __read_mostly; @@ -370,7 +369,6 @@ void flush_dcache_page(struct page *page) out: put_cpu(); } -EXPORT_SYMBOL(flush_dcache_page); void __kprobes flush_icache_range(unsigned long start, unsigned long end) { @@ -398,7 +396,6 @@ void __kprobes flush_icache_range(unsigned long start, unsigned long end) } } } -EXPORT_SYMBOL(flush_icache_range); void mmu_info(struct seq_file *m) { @@ -602,7 +599,6 @@ void __flush_dcache_range(unsigned long start, unsigned long end) "i" (ASI_DCACHE_INVALIDATE)); } } -EXPORT_SYMBOL(__flush_dcache_range); /* get_new_mmu_context() uses "cache + 1". */ DEFINE_SPINLOCK(ctx_alloc_lock); diff --git a/trunk/arch/sparc/prom/init_32.c b/trunk/arch/sparc/prom/init_32.c index 6193c33ed4d4..873217c6d823 100644 --- a/trunk/arch/sparc/prom/init_32.c +++ b/trunk/arch/sparc/prom/init_32.c @@ -8,20 +8,16 @@ #include #include -#include #include #include struct linux_romvec *romvec; -EXPORT_SYMBOL(romvec); - enum prom_major_version prom_vers; unsigned int prom_rev, prom_prev; /* The root node of the prom device tree. */ int prom_root_node; -EXPORT_SYMBOL(prom_root_node); /* Pointer to the device tree operations structure. */ struct linux_nodeops *prom_nodeops; diff --git a/trunk/arch/sparc/prom/misc_32.c b/trunk/arch/sparc/prom/misc_32.c index 4d61c540bb3d..cf6c3f6d36c3 100644 --- a/trunk/arch/sparc/prom/misc_32.c +++ b/trunk/arch/sparc/prom/misc_32.c @@ -8,8 +8,6 @@ #include #include #include -#include - #include #include #include @@ -46,7 +44,6 @@ prom_feval(char *fstring) restore_current(); spin_unlock_irqrestore(&prom_lock, flags); } -EXPORT_SYMBOL(prom_feval); /* Drop into the prom, with the chance to continue with the 'go' * prom command. diff --git a/trunk/arch/sparc/prom/misc_64.c b/trunk/arch/sparc/prom/misc_64.c index eedffb4fec2d..9b0c0760901e 100644 --- a/trunk/arch/sparc/prom/misc_64.c +++ b/trunk/arch/sparc/prom/misc_64.c @@ -11,8 +11,6 @@ #include #include #include -#include - #include #include #include @@ -56,7 +54,6 @@ void prom_feval(const char *fstring) p1275_cmd("interpret", P1275_ARG(0, P1275_ARG_IN_STRING) | P1275_INOUT(1, 1), fstring); } -EXPORT_SYMBOL(prom_feval); #ifdef CONFIG_SMP extern void smp_capture(void); diff --git a/trunk/arch/sparc/prom/ranges.c b/trunk/arch/sparc/prom/ranges.c index cd5790853ff6..64579a376419 100644 --- a/trunk/arch/sparc/prom/ranges.c +++ b/trunk/arch/sparc/prom/ranges.c @@ -6,8 +6,6 @@ */ #include -#include - #include #include #include @@ -64,7 +62,6 @@ prom_apply_obio_ranges(struct linux_prom_registers *regs, int nregs) if(num_obio_ranges) prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges); } -EXPORT_SYMBOL(prom_apply_obio_ranges); void __init prom_ranges_init(void) { diff --git a/trunk/arch/sparc/prom/tree_32.c b/trunk/arch/sparc/prom/tree_32.c index 646d244b1fdb..6d8187357331 100644 --- a/trunk/arch/sparc/prom/tree_32.c +++ b/trunk/arch/sparc/prom/tree_32.c @@ -5,12 +5,13 @@ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) */ +#define PROMLIB_INTERNAL + #include #include #include #include #include -#include #include #include @@ -49,7 +50,6 @@ int prom_getchild(int node) return cnode; } -EXPORT_SYMBOL(prom_getchild); /* Internal version of prom_getsibling that does not alter return values. */ int __prom_getsibling(int node) @@ -81,7 +81,6 @@ int prom_getsibling(int node) return sibnode; } -EXPORT_SYMBOL(prom_getsibling); /* Return the length in bytes of property 'prop' at node 'node'. * Return -1 on error. @@ -100,7 +99,6 @@ int prom_getproplen(int node, const char *prop) spin_unlock_irqrestore(&prom_lock, flags); return ret; } -EXPORT_SYMBOL(prom_getproplen); /* Acquire a property 'prop' at node 'node' and place it in * 'buffer' which has a size of 'bufsize'. If the acquisition @@ -121,7 +119,6 @@ int prom_getproperty(int node, const char *prop, char *buffer, int bufsize) spin_unlock_irqrestore(&prom_lock, flags); return ret; } -EXPORT_SYMBOL(prom_getproperty); /* Acquire an integer property and return its value. Returns -1 * on failure. @@ -135,7 +132,6 @@ int prom_getint(int node, char *prop) return -1; } -EXPORT_SYMBOL(prom_getint); /* Acquire an integer property, upon error return the passed default * integer. @@ -149,7 +145,6 @@ int prom_getintdefault(int node, char *property, int deflt) return retval; } -EXPORT_SYMBOL(prom_getintdefault); /* Acquire a boolean property, 1=TRUE 0=FALSE. */ int prom_getbool(int node, char *prop) @@ -160,7 +155,6 @@ int prom_getbool(int node, char *prop) if(retval == -1) return 0; return 1; } -EXPORT_SYMBOL(prom_getbool); /* Acquire a property whose value is a string, returns a null * string on error. The char pointer is the user supplied string @@ -175,7 +169,6 @@ void prom_getstring(int node, char *prop, char *user_buf, int ubuf_size) user_buf[0] = 0; return; } -EXPORT_SYMBOL(prom_getstring); /* Does the device at node 'node' have name 'name'? @@ -211,7 +204,6 @@ int prom_searchsiblings(int node_start, char *nodename) return 0; } -EXPORT_SYMBOL(prom_searchsiblings); /* Interal version of nextprop that does not alter return values. */ char * __prom_nextprop(int node, char * oprop) @@ -236,7 +228,6 @@ char * prom_firstprop(int node, char *bufer) return __prom_nextprop(node, ""); } -EXPORT_SYMBOL(prom_firstprop); /* Return the property type string after property type 'oprop' * at node 'node' . Returns empty string if no more @@ -249,7 +240,6 @@ char * prom_nextprop(int node, char *oprop, char *buffer) return __prom_nextprop(node, oprop); } -EXPORT_SYMBOL(prom_nextprop); int prom_finddevice(char *name) { @@ -297,7 +287,6 @@ int prom_finddevice(char *name) } return node; } -EXPORT_SYMBOL(prom_finddevice); int prom_node_has_property(int node, char *prop) { @@ -310,7 +299,6 @@ int prom_node_has_property(int node, char *prop) } while (*current_property); return 0; } -EXPORT_SYMBOL(prom_node_has_property); /* Set property 'pname' at node 'node' to value 'value' which has a length * of 'size' bytes. Return the number of bytes the prom accepted. @@ -328,7 +316,6 @@ int prom_setprop(int node, const char *pname, char *value, int size) spin_unlock_irqrestore(&prom_lock, flags); return ret; } -EXPORT_SYMBOL(prom_setprop); int prom_inst2pkg(int inst) { diff --git a/trunk/arch/sparc/prom/tree_64.c b/trunk/arch/sparc/prom/tree_64.c index 8ea73ddc61dc..281aea44790b 100644 --- a/trunk/arch/sparc/prom/tree_64.c +++ b/trunk/arch/sparc/prom/tree_64.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -33,7 +32,6 @@ inline int prom_getchild(int node) if(cnode == -1) return 0; return (int)cnode; } -EXPORT_SYMBOL(prom_getchild); inline int prom_getparent(int node) { @@ -65,7 +63,6 @@ inline int prom_getsibling(int node) return sibnode; } -EXPORT_SYMBOL(prom_getsibling); /* Return the length in bytes of property 'prop' at node 'node'. * Return -1 on error. @@ -78,7 +75,6 @@ inline int prom_getproplen(int node, const char *prop) P1275_INOUT(2, 1), node, prop); } -EXPORT_SYMBOL(prom_getproplen); /* Acquire a property 'prop' at node 'node' and place it in * 'buffer' which has a size of 'bufsize'. If the acquisition @@ -101,7 +97,6 @@ inline int prom_getproperty(int node, const char *prop, node, prop, buffer, P1275_SIZE(plen)); } } -EXPORT_SYMBOL(prom_getproperty); /* Acquire an integer property and return its value. Returns -1 * on failure. @@ -115,7 +110,6 @@ inline int prom_getint(int node, const char *prop) return -1; } -EXPORT_SYMBOL(prom_getint); /* Acquire an integer property, upon error return the passed default * integer. @@ -130,7 +124,6 @@ int prom_getintdefault(int node, const char *property, int deflt) return retval; } -EXPORT_SYMBOL(prom_getintdefault); /* Acquire a boolean property, 1=TRUE 0=FALSE. */ int prom_getbool(int node, const char *prop) @@ -141,7 +134,6 @@ int prom_getbool(int node, const char *prop) if(retval == -1) return 0; return 1; } -EXPORT_SYMBOL(prom_getbool); /* Acquire a property whose value is a string, returns a null * string on error. The char pointer is the user supplied string @@ -156,7 +148,7 @@ void prom_getstring(int node, const char *prop, char *user_buf, int ubuf_size) user_buf[0] = 0; return; } -EXPORT_SYMBOL(prom_getstring); + /* Does the device at node 'node' have name 'name'? * YES = 1 NO = 0 @@ -189,7 +181,6 @@ int prom_searchsiblings(int node_start, const char *nodename) return 0; } -EXPORT_SYMBOL(prom_searchsiblings); /* Return the first property type for node 'node'. * buffer should be at least 32B in length @@ -203,7 +194,6 @@ inline char *prom_firstprop(int node, char *buffer) node, (char *) 0x0, buffer); return buffer; } -EXPORT_SYMBOL(prom_firstprop); /* Return the property type string after property type 'oprop' * at node 'node' . Returns NULL string if no more @@ -227,7 +217,6 @@ inline char *prom_nextprop(int node, const char *oprop, char *buffer) node, oprop, buffer); return buffer; } -EXPORT_SYMBOL(prom_nextprop); int prom_finddevice(const char *name) @@ -239,7 +228,6 @@ prom_finddevice(const char *name) P1275_INOUT(1, 1), name); } -EXPORT_SYMBOL(prom_finddevice); int prom_node_has_property(int node, const char *prop) { @@ -253,8 +241,7 @@ int prom_node_has_property(int node, const char *prop) } while (*buf); return 0; } -EXPORT_SYMBOL(prom_node_has_property); - + /* Set property 'pname' at node 'node' to value 'value' which has a length * of 'size' bytes. Return the number of bytes the prom accepted. */ @@ -277,7 +264,6 @@ prom_setprop(int node, const char *pname, char *value, int size) P1275_INOUT(4, 1), node, pname, value, P1275_SIZE(size)); } -EXPORT_SYMBOL(prom_setprop); inline int prom_inst2pkg(int inst) { diff --git a/trunk/arch/x86/include/asm/mach-default/mach_wakecpu.h b/trunk/arch/x86/include/asm/mach-default/mach_wakecpu.h index 89897a6a65b9..ceb013660146 100644 --- a/trunk/arch/x86/include/asm/mach-default/mach_wakecpu.h +++ b/trunk/arch/x86/include/asm/mach-default/mach_wakecpu.h @@ -24,13 +24,7 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low) { } -#ifdef CONFIG_SMP extern void __inquire_remote_apic(int apicid); -#else /* CONFIG_SMP */ -static inline void __inquire_remote_apic(int apicid) -{ -} -#endif /* CONFIG_SMP */ static inline void inquire_remote_apic(int apicid) { diff --git a/trunk/arch/x86/include/asm/mtrr.h b/trunk/arch/x86/include/asm/mtrr.h index 14080d22edb3..cb988aab716d 100644 --- a/trunk/arch/x86/include/asm/mtrr.h +++ b/trunk/arch/x86/include/asm/mtrr.h @@ -58,15 +58,15 @@ struct mtrr_gentry { #endif /* !__i386__ */ struct mtrr_var_range { - __u32 base_lo; - __u32 base_hi; - __u32 mask_lo; - __u32 mask_hi; + u32 base_lo; + u32 base_hi; + u32 mask_lo; + u32 mask_hi; }; /* In the Intel processor's MTRR interface, the MTRR type is always held in an 8 bit field: */ -typedef __u8 mtrr_type; +typedef u8 mtrr_type; #define MTRR_NUM_FIXED_RANGES 88 #define MTRR_MAX_VAR_RANGES 256 diff --git a/trunk/arch/x86/include/asm/pgtable.h b/trunk/arch/x86/include/asm/pgtable.h index 06bbcbd66e9c..83e69f4a37f0 100644 --- a/trunk/arch/x86/include/asm/pgtable.h +++ b/trunk/arch/x86/include/asm/pgtable.h @@ -341,25 +341,6 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) #define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) -static inline int is_new_memtype_allowed(unsigned long flags, - unsigned long new_flags) -{ - /* - * Certain new memtypes are not allowed with certain - * requested memtype: - * - request is uncached, return cannot be write-back - * - request is write-combine, return cannot be write-back - */ - if ((flags == _PAGE_CACHE_UC_MINUS && - new_flags == _PAGE_CACHE_WB) || - (flags == _PAGE_CACHE_WC && - new_flags == _PAGE_CACHE_WB)) { - return 0; - } - - return 1; -} - #ifndef __ASSEMBLY__ /* Indicate that x86 has its own track and untrack pfn vma functions */ #define __HAVE_PFNMAP_TRACKING diff --git a/trunk/arch/x86/include/asm/topology.h b/trunk/arch/x86/include/asm/topology.h index 4e2f2e0aab27..d0c68e291635 100644 --- a/trunk/arch/x86/include/asm/topology.h +++ b/trunk/arch/x86/include/asm/topology.h @@ -192,9 +192,20 @@ extern int __node_distance(int, int); #else /* !CONFIG_NUMA */ -#define numa_node_id() 0 -#define cpu_to_node(cpu) 0 -#define early_cpu_to_node(cpu) 0 +static inline int numa_node_id(void) +{ + return 0; +} + +static inline int cpu_to_node(int cpu) +{ + return 0; +} + +static inline int early_cpu_to_node(int cpu) +{ + return 0; +} static inline const cpumask_t *cpumask_of_node(int node) { diff --git a/trunk/arch/x86/kernel/apic.c b/trunk/arch/x86/kernel/apic.c index 0f830e4f5675..566a08466b19 100644 --- a/trunk/arch/x86/kernel/apic.c +++ b/trunk/arch/x86/kernel/apic.c @@ -47,7 +47,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/trunk/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c index 019276717a7f..06fcd8f9323c 100644 --- a/trunk/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/trunk/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c @@ -145,13 +145,14 @@ typedef union { struct drv_cmd { unsigned int type; - const struct cpumask *mask; + cpumask_var_t mask; drv_addr_union addr; u32 val; }; -static void do_drv_read(struct drv_cmd *cmd) +static long do_drv_read(void *_cmd) { + struct drv_cmd *cmd = _cmd; u32 h; switch (cmd->type) { @@ -166,10 +167,12 @@ static void do_drv_read(struct drv_cmd *cmd) default: break; } + return 0; } -static void do_drv_write(struct drv_cmd *cmd) +static long do_drv_write(void *_cmd) { + struct drv_cmd *cmd = _cmd; u32 lo, hi; switch (cmd->type) { @@ -186,30 +189,23 @@ static void do_drv_write(struct drv_cmd *cmd) default: break; } + return 0; } static void drv_read(struct drv_cmd *cmd) { - cpumask_t saved_mask = current->cpus_allowed; cmd->val = 0; - set_cpus_allowed_ptr(current, cmd->mask); - do_drv_read(cmd); - set_cpus_allowed_ptr(current, &saved_mask); + work_on_cpu(cpumask_any(cmd->mask), do_drv_read, cmd); } static void drv_write(struct drv_cmd *cmd) { - cpumask_t saved_mask = current->cpus_allowed; unsigned int i; for_each_cpu(i, cmd->mask) { - set_cpus_allowed_ptr(current, cpumask_of(i)); - do_drv_write(cmd); + work_on_cpu(i, do_drv_write, cmd); } - - set_cpus_allowed_ptr(current, &saved_mask); - return; } static u32 get_cur_val(const struct cpumask *mask) @@ -235,9 +231,15 @@ static u32 get_cur_val(const struct cpumask *mask) return 0; } - cmd.mask = mask; + if (unlikely(!alloc_cpumask_var(&cmd.mask, GFP_KERNEL))) + return 0; + + cpumask_copy(cmd.mask, mask); + drv_read(&cmd); + free_cpumask_var(cmd.mask); + dprintk("get_cur_val = %u\n", cmd.val); return cmd.val; @@ -402,6 +404,9 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, return -ENODEV; } + if (unlikely(!alloc_cpumask_var(&cmd.mask, GFP_KERNEL))) + return -ENOMEM; + perf = data->acpi_data; result = cpufreq_frequency_table_target(policy, data->freq_table, @@ -446,9 +451,9 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, /* cpufreq holds the hotplug lock, so we are safe from here on */ if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) - cmd.mask = policy->cpus; + cpumask_and(cmd.mask, cpu_online_mask, policy->cpus); else - cmd.mask = cpumask_of(policy->cpu); + cpumask_copy(cmd.mask, cpumask_of(policy->cpu)); freqs.old = perf->states[perf->state].core_frequency * 1000; freqs.new = data->freq_table[next_state].frequency; @@ -475,6 +480,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy, perf->state = next_perf_state; out: + free_cpumask_var(cmd.mask); return result; } diff --git a/trunk/arch/x86/kernel/entry_32.S b/trunk/arch/x86/kernel/entry_32.S index 46469029e9d3..d6f0490a7391 100644 --- a/trunk/arch/x86/kernel/entry_32.S +++ b/trunk/arch/x86/kernel/entry_32.S @@ -1203,6 +1203,7 @@ nmi_stack_correct: pushl %eax CFI_ADJUST_CFA_OFFSET 4 SAVE_ALL + TRACE_IRQS_OFF xorl %edx,%edx # zero error code movl %esp,%eax # pt_regs pointer call do_nmi @@ -1243,6 +1244,7 @@ nmi_espfix_stack: pushl %eax CFI_ADJUST_CFA_OFFSET 4 SAVE_ALL + TRACE_IRQS_OFF FIXUP_ESPFIX_STACK # %eax == %esp xorl %edx,%edx # zero error code call do_nmi diff --git a/trunk/arch/x86/kernel/mpparse.c b/trunk/arch/x86/kernel/mpparse.c index a649a4ccad43..c0601c2848a1 100644 --- a/trunk/arch/x86/kernel/mpparse.c +++ b/trunk/arch/x86/kernel/mpparse.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #ifdef CONFIG_X86_32 diff --git a/trunk/arch/x86/kernel/tlb_64.c b/trunk/arch/x86/kernel/tlb_64.c index 7f4141d3b661..54ee2ecb5e26 100644 --- a/trunk/arch/x86/kernel/tlb_64.c +++ b/trunk/arch/x86/kernel/tlb_64.c @@ -188,8 +188,7 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask, * We have to send the IPI only to * CPUs affected. */ - send_IPI_mask(to_cpumask(f->flush_cpumask), - INVALIDATE_TLB_VECTOR_START + sender); + send_IPI_mask(f->flush_cpumask, INVALIDATE_TLB_VECTOR_START + sender); while (!cpumask_empty(to_cpumask(f->flush_cpumask))) cpu_relax(); diff --git a/trunk/arch/x86/mm/fault.c b/trunk/arch/x86/mm/fault.c index 90dfae511a41..9e268b6b204e 100644 --- a/trunk/arch/x86/mm/fault.c +++ b/trunk/arch/x86/mm/fault.c @@ -534,7 +534,7 @@ static int vmalloc_fault(unsigned long address) happen within a race in page table update. In the later case just flush. */ - pgd = pgd_offset(current->active_mm, address); + pgd = pgd_offset(current->mm ?: &init_mm, address); pgd_ref = pgd_offset_k(address); if (pgd_none(*pgd_ref)) return -1; diff --git a/trunk/arch/x86/mm/pageattr.c b/trunk/arch/x86/mm/pageattr.c index 4cf30dee8161..e89d24815f26 100644 --- a/trunk/arch/x86/mm/pageattr.c +++ b/trunk/arch/x86/mm/pageattr.c @@ -555,12 +555,10 @@ static int __change_page_attr(struct cpa_data *cpa, int primary) if (!pte_val(old_pte)) { if (!primary) return 0; - - /* - * Special error value returned, indicating that the mapping - * did not exist at this address. - */ - return -EFAULT; + WARN(1, KERN_WARNING "CPA: called for zero pte. " + "vaddr = %lx cpa->vaddr = %lx\n", address, + *cpa->vaddr); + return -EINVAL; } if (level == PG_LEVEL_4K) { diff --git a/trunk/arch/x86/mm/pat.c b/trunk/arch/x86/mm/pat.c index 160c42d3eb8f..85cbd3cd3723 100644 --- a/trunk/arch/x86/mm/pat.c +++ b/trunk/arch/x86/mm/pat.c @@ -505,35 +505,6 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size) } #endif /* CONFIG_STRICT_DEVMEM */ -/* - * Change the memory type for the physial address range in kernel identity - * mapping space if that range is a part of identity map. - */ -static int kernel_map_sync_memtype(u64 base, unsigned long size, - unsigned long flags) -{ - unsigned long id_sz; - int ret; - - if (!pat_enabled || base >= __pa(high_memory)) - return 0; - - id_sz = (__pa(high_memory) < base + size) ? - __pa(high_memory) - base : - size; - - ret = ioremap_change_attr((unsigned long)__va(base), id_sz, flags); - /* - * -EFAULT return means that the addr was not valid and did not have - * any identity mapping. That case is a success for - * kernel_map_sync_memtype. - */ - if (ret == -EFAULT) - ret = 0; - - return ret; -} - int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, unsigned long size, pgprot_t *vma_prot) { @@ -584,7 +555,9 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, if (retval < 0) return 0; - if (kernel_map_sync_memtype(offset, size, flags)) { + if (((pfn < max_low_pfn_mapped) || + (pfn >= (1UL<<(32 - PAGE_SHIFT)) && pfn < max_pfn_mapped)) && + ioremap_change_attr((unsigned long)__va(offset), size, flags) < 0) { free_memtype(offset, offset + size); printk(KERN_INFO "%s:%d /dev/mem ioremap_change_attr failed %s for %Lx-%Lx\n", @@ -628,13 +601,12 @@ void unmap_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot) * Reserved non RAM regions only and after successful reserve_memtype, * this func also keeps identity mapping (if any) in sync with this new prot. */ -static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot, - int strict_prot) +static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t vma_prot) { int is_ram = 0; - int ret; + int id_sz, ret; unsigned long flags; - unsigned long want_flags = (pgprot_val(*vma_prot) & _PAGE_CACHE_MASK); + unsigned long want_flags = (pgprot_val(vma_prot) & _PAGE_CACHE_MASK); is_ram = pagerange_is_ram(paddr, paddr + size); @@ -653,27 +625,26 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot, return ret; if (flags != want_flags) { - if (strict_prot || !is_new_memtype_allowed(want_flags, flags)) { - free_memtype(paddr, paddr + size); - printk(KERN_ERR "%s:%d map pfn expected mapping type %s" - " for %Lx-%Lx, got %s\n", - current->comm, current->pid, - cattr_name(want_flags), - (unsigned long long)paddr, - (unsigned long long)(paddr + size), - cattr_name(flags)); - return -EINVAL; - } - /* - * We allow returning different type than the one requested in - * non strict case. - */ - *vma_prot = __pgprot((pgprot_val(*vma_prot) & - (~_PAGE_CACHE_MASK)) | - flags); + free_memtype(paddr, paddr + size); + printk(KERN_ERR + "%s:%d map pfn expected mapping type %s for %Lx-%Lx, got %s\n", + current->comm, current->pid, + cattr_name(want_flags), + (unsigned long long)paddr, + (unsigned long long)(paddr + size), + cattr_name(flags)); + return -EINVAL; } - if (kernel_map_sync_memtype(paddr, size, flags)) { + /* Need to keep identity mapping in sync */ + if (paddr >= __pa(high_memory)) + return 0; + + id_sz = (__pa(high_memory) < paddr + size) ? + __pa(high_memory) - paddr : + size; + + if (ioremap_change_attr((unsigned long)__va(paddr), id_sz, flags) < 0) { free_memtype(paddr, paddr + size); printk(KERN_ERR "%s:%d reserve_pfn_range ioremap_change_attr failed %s " @@ -718,7 +689,6 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) unsigned long vma_start = vma->vm_start; unsigned long vma_end = vma->vm_end; unsigned long vma_size = vma_end - vma_start; - pgprot_t pgprot; if (!pat_enabled) return 0; @@ -732,8 +702,7 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) WARN_ON_ONCE(1); return -EINVAL; } - pgprot = __pgprot(prot); - return reserve_pfn_range(paddr, vma_size, &pgprot, 1); + return reserve_pfn_range(paddr, vma_size, __pgprot(prot)); } /* reserve entire vma page by page, using pfn and prot from pte */ @@ -741,8 +710,7 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) if (follow_phys(vma, vma_start + i, 0, &prot, &paddr)) continue; - pgprot = __pgprot(prot); - retval = reserve_pfn_range(paddr, PAGE_SIZE, &pgprot, 1); + retval = reserve_pfn_range(paddr, PAGE_SIZE, __pgprot(prot)); if (retval) goto cleanup_ret; } @@ -773,7 +741,7 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) * Note that this function can be called with caller trying to map only a * subrange/page inside the vma. */ -int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot, +int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, unsigned long pfn, unsigned long size) { int retval = 0; @@ -790,14 +758,14 @@ int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot, if (is_linear_pfn_mapping(vma)) { /* reserve the whole chunk starting from vm_pgoff */ paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT; - return reserve_pfn_range(paddr, vma_size, prot, 0); + return reserve_pfn_range(paddr, vma_size, prot); } /* reserve page by page using pfn and size */ base_paddr = (resource_size_t)pfn << PAGE_SHIFT; for (i = 0; i < size; i += PAGE_SIZE) { paddr = base_paddr + i; - retval = reserve_pfn_range(paddr, PAGE_SIZE, prot, 0); + retval = reserve_pfn_range(paddr, PAGE_SIZE, prot); if (retval) goto cleanup_ret; } diff --git a/trunk/arch/x86/pci/i386.c b/trunk/arch/x86/pci/i386.c index 5ead808dd70c..f884740da318 100644 --- a/trunk/arch/x86/pci/i386.c +++ b/trunk/arch/x86/pci/i386.c @@ -314,7 +314,17 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return retval; if (flags != new_flags) { - if (!is_new_memtype_allowed(flags, new_flags)) { + /* + * Do not fallback to certain memory types with certain + * requested type: + * - request is uncached, return cannot be write-back + * - request is uncached, return cannot be write-combine + * - request is write-combine, return cannot be write-back + */ + if ((flags == _PAGE_CACHE_UC_MINUS && + (new_flags == _PAGE_CACHE_WB)) || + (flags == _PAGE_CACHE_WC && + new_flags == _PAGE_CACHE_WB)) { free_memtype(addr, addr+len); return -EINVAL; } diff --git a/trunk/drivers/ata/libata-sff.c b/trunk/drivers/ata/libata-sff.c index 5a4aad123c42..0eae9b453556 100644 --- a/trunk/drivers/ata/libata-sff.c +++ b/trunk/drivers/ata/libata-sff.c @@ -1013,12 +1013,9 @@ static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) qc->cursg_ofs = 0; } - /* - * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); - * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN - * check correctly as it doesn't know if it is the last request being - * made. Somebody should implement a proper sanity check. - */ + /* consumed can be larger than count only for the last transfer */ + WARN_ON_ONCE(qc->cursg && count != consumed); + if (bytes) goto next_sg; return 0; diff --git a/trunk/drivers/ata/pata_it821x.c b/trunk/drivers/ata/pata_it821x.c index f1bb2f9fecbf..f828a29d7756 100644 --- a/trunk/drivers/ata/pata_it821x.c +++ b/trunk/drivers/ata/pata_it821x.c @@ -80,7 +80,7 @@ #define DRV_NAME "pata_it821x" -#define DRV_VERSION "0.4.2" +#define DRV_VERSION "0.4.0" struct it821x_dev { @@ -494,6 +494,8 @@ static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unus * special. In our case we need to lock the sector count to avoid * blowing the brains out of the firmware with large LBA48 requests * + * FIXME: When FUA appears we need to block FUA too. And SMART and + * basically we need to filter commands for this chip. */ static void it821x_dev_config(struct ata_device *adev) @@ -885,13 +887,6 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) .port_ops = &it821x_passthru_port_ops }; static const struct ata_port_info info_rdc = { - .flags = ATA_FLAG_SLAVE_POSS, - .pio_mask = 0x1f, - .mwdma_mask = 0x07, - .udma_mask = ATA_UDMA6, - .port_ops = &it821x_rdc_port_ops - }; - static const struct ata_port_info info_rdc_11 = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, .mwdma_mask = 0x07, @@ -908,11 +903,7 @@ static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) return rc; if (pdev->vendor == PCI_VENDOR_ID_RDC) { - /* Deal with Vortex86SX */ - if (pdev->revision == 0x11) - ppi[0] = &info_rdc_11; - else - ppi[0] = &info_rdc; + ppi[0] = &info_rdc; } else { /* Force the card into bypass mode if so requested */ if (it8212_noraid) { diff --git a/trunk/drivers/block/amiflop.c b/trunk/drivers/block/amiflop.c index 8df436ff7068..4b1d4ac960f1 100644 --- a/trunk/drivers/block/amiflop.c +++ b/trunk/drivers/block/amiflop.c @@ -156,7 +156,7 @@ static volatile int fdc_busy = -1; static volatile int fdc_nested; static DECLARE_WAIT_QUEUE_HEAD(fdc_wait); -static DECLARE_COMPLETION(motor_on_completion); +static DECLARE_WAIT_QUEUE_HEAD(motor_wait); static volatile int selected = -1; /* currently selected drive */ @@ -184,7 +184,8 @@ static unsigned char mfmencode[16]={ static unsigned char mfmdecode[128]; /* floppy internal millisecond timer stuff */ -static DECLARE_COMPLETION(ms_wait_completion); +static volatile int ms_busy = -1; +static DECLARE_WAIT_QUEUE_HEAD(ms_wait); #define MS_TICKS ((amiga_eclock+50)/1000) /* @@ -210,7 +211,8 @@ static int fd_device[4] = { 0, 0, 0, 0 }; static irqreturn_t ms_isr(int irq, void *dummy) { - complete(&ms_wait_completion); + ms_busy = -1; + wake_up(&ms_wait); return IRQ_HANDLED; } @@ -218,17 +220,19 @@ static irqreturn_t ms_isr(int irq, void *dummy) A more generic routine would do a schedule a la timer.device */ static void ms_delay(int ms) { + unsigned long flags; int ticks; - static DEFINE_MUTEX(mutex); - if (ms > 0) { - mutex_lock(&mutex); + local_irq_save(flags); + while (ms_busy == 0) + sleep_on(&ms_wait); + ms_busy = 0; + local_irq_restore(flags); ticks = MS_TICKS*ms-1; ciaa.tblo=ticks%256; ciaa.tbhi=ticks/256; ciaa.crb=0x19; /*count eclock, force load, one-shoot, start */ - wait_for_completion(&ms_wait_completion); - mutex_unlock(&mutex); + sleep_on(&ms_wait); } } @@ -250,7 +254,8 @@ static void get_fdc(int drive) printk("get_fdc: drive %d fdc_busy %d fdc_nested %d\n",drive,fdc_busy,fdc_nested); #endif local_irq_save(flags); - wait_event(fdc_wait, try_fdc(drive)); + while (!try_fdc(drive)) + sleep_on(&fdc_wait); fdc_busy = drive; fdc_nested++; local_irq_restore(flags); @@ -325,7 +330,7 @@ static void fd_deselect (int drive) static void motor_on_callback(unsigned long nr) { if (!(ciaa.pra & DSKRDY) || --on_attempts == 0) { - complete_all(&motor_on_completion); + wake_up (&motor_wait); } else { motor_on_timer.expires = jiffies + HZ/10; add_timer(&motor_on_timer); @@ -342,12 +347,11 @@ static int fd_motor_on(int nr) unit[nr].motor = 1; fd_select(nr); - INIT_COMPLETION(motor_on_completion); motor_on_timer.data = nr; mod_timer(&motor_on_timer, jiffies + HZ/2); on_attempts = 10; - wait_for_completion(&motor_on_completion); + sleep_on (&motor_wait); fd_deselect(nr); } @@ -578,7 +582,8 @@ static void raw_read(int drive) { drive&=3; get_fdc(drive); - wait_event(wait_fd_block, !block_flag); + while (block_flag) + sleep_on(&wait_fd_block); fd_select(drive); /* setup adkcon bits correctly */ custom.adkcon = ADK_MSBSYNC; @@ -593,7 +598,8 @@ static void raw_read(int drive) block_flag = 1; - wait_event(wait_fd_block, !block_flag); + while (block_flag) + sleep_on (&wait_fd_block); custom.dsklen = 0; fd_deselect(drive); @@ -610,7 +616,8 @@ static int raw_write(int drive) rel_fdc(); return 0; } - wait_event(wait_fd_block, !block_flag); + while (block_flag) + sleep_on(&wait_fd_block); fd_select(drive); /* clear adkcon bits */ custom.adkcon = ADK_PRECOMP1|ADK_PRECOMP0|ADK_WORDSYNC|ADK_MSBSYNC; @@ -1287,7 +1294,8 @@ static int non_int_flush_track (unsigned long nr) writepending = 0; return 0; } - wait_event(wait_fd_block, block_flag != 2); + while (block_flag == 2) + sleep_on (&wait_fd_block); } else { local_irq_restore(flags); diff --git a/trunk/drivers/char/amiserial.c b/trunk/drivers/char/amiserial.c index a58869ea8513..4e0cfdeab146 100644 --- a/trunk/drivers/char/amiserial.c +++ b/trunk/drivers/char/amiserial.c @@ -1963,7 +1963,6 @@ static int __init rs_init(void) { unsigned long flags; struct serial_state * state; - int error; if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(AMI_SERIAL)) return -ENODEV; @@ -1976,11 +1975,8 @@ static int __init rs_init(void) * We request SERDAT and SERPER only, because the serial registers are * too spreaded over the custom register space */ - if (!request_mem_region(CUSTOM_PHYSADDR+0x30, 4, - "amiserial [Paula]")) { - error = -EBUSY; - goto fail_put_tty_driver; - } + if (!request_mem_region(CUSTOM_PHYSADDR+0x30, 4, "amiserial [Paula]")) + return -EBUSY; IRQ_ports = NULL; @@ -2001,9 +1997,8 @@ static int __init rs_init(void) serial_driver->flags = TTY_DRIVER_REAL_RAW; tty_set_operations(serial_driver, &serial_ops); - error = tty_register_driver(serial_driver); - if (error) - goto fail_release_mem_region; + if (tty_register_driver(serial_driver)) + panic("Couldn't register serial driver\n"); state = rs_table; state->magic = SSTATE_MAGIC; @@ -2029,14 +2024,8 @@ static int __init rs_init(void) local_irq_save(flags); /* set ISRs, and then disable the rx interrupts */ - error = request_irq(IRQ_AMIGA_TBE, ser_tx_int, 0, "serial TX", state); - if (error) - goto fail_unregister; - - error = request_irq(IRQ_AMIGA_RBF, ser_rx_int, IRQF_DISABLED, - "serial RX", state); - if (error) - goto fail_free_irq; + request_irq(IRQ_AMIGA_TBE, ser_tx_int, 0, "serial TX", state); + request_irq(IRQ_AMIGA_RBF, ser_rx_int, IRQF_DISABLED, "serial RX", state); /* turn off Rx and Tx interrupts */ custom.intena = IF_RBF | IF_TBE; @@ -2056,16 +2045,6 @@ static int __init rs_init(void) ciab.ddra &= ~(SER_DCD | SER_CTS | SER_DSR); /* inputs */ return 0; - -fail_free_irq: - free_irq(IRQ_AMIGA_TBE, state); -fail_unregister: - tty_unregister_driver(serial_driver); -fail_release_mem_region: - release_mem_region(CUSTOM_PHYSADDR+0x30, 4); -fail_put_tty_driver: - put_tty_driver(serial_driver); - return error; } static __exit void rs_exit(void) @@ -2085,9 +2064,6 @@ static __exit void rs_exit(void) kfree(info); } - free_irq(IRQ_AMIGA_TBE, rs_table); - free_irq(IRQ_AMIGA_RBF, rs_table); - release_mem_region(CUSTOM_PHYSADDR+0x30, 4); } diff --git a/trunk/drivers/char/pty.c b/trunk/drivers/char/pty.c index 31038a0052a2..146c97613da0 100644 --- a/trunk/drivers/char/pty.c +++ b/trunk/drivers/char/pty.c @@ -230,7 +230,9 @@ static void pty_set_termios(struct tty_struct *tty, /** * pty_do_resize - resize event * @tty: tty being resized - * @ws: window size being set. + * @real_tty: real tty (not the same as tty if using a pty/tty pair) + * @rows: rows (character) + * @cols: cols (character) * * Update the termios variables and send the neccessary signals to * peform a terminal resize correctly diff --git a/trunk/drivers/char/ser_a2232.c b/trunk/drivers/char/ser_a2232.c index 33a2b531802e..33872a219df6 100644 --- a/trunk/drivers/char/ser_a2232.c +++ b/trunk/drivers/char/ser_a2232.c @@ -718,7 +718,6 @@ static int __init a2232board_init(void) u_char *from; volatile u_char *to; volatile struct a2232memory *mem; - int error, i; #ifdef CONFIG_SMP return -ENODEV; /* This driver is not SMP aware. Is there an SMP ZorroII-bus-machine? */ @@ -798,15 +797,8 @@ static int __init a2232board_init(void) */ if (a2232_init_drivers()) return -ENODEV; // maybe we should use a different -Exxx? - error = request_irq(IRQ_AMIGA_VERTB, a2232_vbl_inter, 0, - "A2232 serial VBL", a2232_driver_ID); - if (error) { - for (i = 0; i < nr_a2232; i++) - zorro_release_device(zd_a2232[i]); - tty_unregister_driver(a2232_driver); - put_tty_driver(a2232_driver); - } - return error; + request_irq(IRQ_AMIGA_VERTB, a2232_vbl_inter, 0, "A2232 serial VBL", a2232_driver_ID); + return 0; } static void __exit a2232board_exit(void) diff --git a/trunk/drivers/char/vme_scc.c b/trunk/drivers/char/vme_scc.c index 994e1a58b987..0e8234bd0e19 100644 --- a/trunk/drivers/char/vme_scc.c +++ b/trunk/drivers/char/vme_scc.c @@ -198,7 +198,6 @@ static void scc_init_portstructs(void) static int mvme147_scc_init(void) { struct scc_port *port; - int error; printk(KERN_INFO "SCC: MVME147 Serial Driver\n"); /* Init channel A */ @@ -208,23 +207,14 @@ static int mvme147_scc_init(void) port->datap = port->ctrlp + 1; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(MVME147_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, "SCC-A TX", port); - if (error) - goto fail; - error = request_irq(MVME147_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, "SCC-A status", port); - if (error) - goto fail_free_a_tx; - error = request_irq(MVME147_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, "SCC-A RX", port); - if (error) - goto fail_free_a_stat; - error = request_irq(MVME147_IRQ_SCCA_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-A special cond", port); - if (error) - goto fail_free_a_rx; - + request_irq(MVME147_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-A special cond", port); { SCC_ACCESS_INIT(port); @@ -244,23 +234,14 @@ static int mvme147_scc_init(void) port->datap = port->ctrlp + 1; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(MVME147_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, "SCC-B TX", port); - if (error) - goto fail_free_a_spcond; - error = request_irq(MVME147_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, "SCC-B status", port); - if (error) - goto fail_free_b_tx; - error = request_irq(MVME147_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, + request_irq(MVME147_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, "SCC-B RX", port); - if (error) - goto fail_free_b_stat; - error = request_irq(MVME147_IRQ_SCCB_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-B special cond", port); - if (error) - goto fail_free_b_rx; - + request_irq(MVME147_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-B special cond", port); { SCC_ACCESS_INIT(port); @@ -276,23 +257,6 @@ static int mvme147_scc_init(void) scc_init_drivers(); return 0; - -fail_free_b_rx: - free_irq(MVME147_IRQ_SCCB_RX, port); -fail_free_b_stat: - free_irq(MVME147_IRQ_SCCB_STAT, port); -fail_free_b_tx: - free_irq(MVME147_IRQ_SCCB_TX, port); -fail_free_a_spcond: - free_irq(MVME147_IRQ_SCCA_SPCOND, port); -fail_free_a_rx: - free_irq(MVME147_IRQ_SCCA_RX, port); -fail_free_a_stat: - free_irq(MVME147_IRQ_SCCA_STAT, port); -fail_free_a_tx: - free_irq(MVME147_IRQ_SCCA_TX, port); -fail: - return error; } #endif @@ -301,7 +265,6 @@ static int mvme147_scc_init(void) static int mvme162_scc_init(void) { struct scc_port *port; - int error; if (!(mvme16x_config & MVME16x_CONFIG_GOT_SCCA)) return (-ENODEV); @@ -314,23 +277,14 @@ static int mvme162_scc_init(void) port->datap = port->ctrlp + 2; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(MVME162_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, "SCC-A TX", port); - if (error) - goto fail; - error = request_irq(MVME162_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, "SCC-A status", port); - if (error) - goto fail_free_a_tx; - error = request_irq(MVME162_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, "SCC-A RX", port); - if (error) - goto fail_free_a_stat; - error = request_irq(MVME162_IRQ_SCCA_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-A special cond", port); - if (error) - goto fail_free_a_rx; - + request_irq(MVME162_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-A special cond", port); { SCC_ACCESS_INIT(port); @@ -350,22 +304,14 @@ static int mvme162_scc_init(void) port->datap = port->ctrlp + 2; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(MVME162_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, "SCC-B TX", port); - if (error) - goto fail_free_a_spcond; - error = request_irq(MVME162_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, "SCC-B status", port); - if (error) - goto fail_free_b_tx; - error = request_irq(MVME162_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, + request_irq(MVME162_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, "SCC-B RX", port); - if (error) - goto fail_free_b_stat; - error = request_irq(MVME162_IRQ_SCCB_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-B special cond", port); - if (error) - goto fail_free_b_rx; + request_irq(MVME162_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-B special cond", port); { SCC_ACCESS_INIT(port); /* Either channel will do */ @@ -382,23 +328,6 @@ static int mvme162_scc_init(void) scc_init_drivers(); return 0; - -fail_free_b_rx: - free_irq(MVME162_IRQ_SCCB_RX, port); -fail_free_b_stat: - free_irq(MVME162_IRQ_SCCB_STAT, port); -fail_free_b_tx: - free_irq(MVME162_IRQ_SCCB_TX, port); -fail_free_a_spcond: - free_irq(MVME162_IRQ_SCCA_SPCOND, port); -fail_free_a_rx: - free_irq(MVME162_IRQ_SCCA_RX, port); -fail_free_a_stat: - free_irq(MVME162_IRQ_SCCA_STAT, port); -fail_free_a_tx: - free_irq(MVME162_IRQ_SCCA_TX, port); -fail: - return error; } #endif @@ -407,7 +336,6 @@ static int mvme162_scc_init(void) static int bvme6000_scc_init(void) { struct scc_port *port; - int error; printk(KERN_INFO "SCC: BVME6000 Serial Driver\n"); /* Init channel A */ @@ -417,23 +345,14 @@ static int bvme6000_scc_init(void) port->datap = port->ctrlp + 4; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(BVME_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCA_TX, scc_tx_int, IRQF_DISABLED, "SCC-A TX", port); - if (error) - goto fail; - error = request_irq(BVME_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCA_STAT, scc_stat_int, IRQF_DISABLED, "SCC-A status", port); - if (error) - goto fail_free_a_tx; - error = request_irq(BVME_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCA_RX, scc_rx_int, IRQF_DISABLED, "SCC-A RX", port); - if (error) - goto fail_free_a_stat; - error = request_irq(BVME_IRQ_SCCA_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-A special cond", port); - if (error) - goto fail_free_a_rx; - + request_irq(BVME_IRQ_SCCA_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-A special cond", port); { SCC_ACCESS_INIT(port); @@ -453,22 +372,14 @@ static int bvme6000_scc_init(void) port->datap = port->ctrlp + 4; port->port_a = &scc_ports[0]; port->port_b = &scc_ports[1]; - error = request_irq(BVME_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCB_TX, scc_tx_int, IRQF_DISABLED, "SCC-B TX", port); - if (error) - goto fail_free_a_spcond; - error = request_irq(BVME_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCB_STAT, scc_stat_int, IRQF_DISABLED, "SCC-B status", port); - if (error) - goto fail_free_b_tx; - error = request_irq(BVME_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, + request_irq(BVME_IRQ_SCCB_RX, scc_rx_int, IRQF_DISABLED, "SCC-B RX", port); - if (error) - goto fail_free_b_stat; - error = request_irq(BVME_IRQ_SCCB_SPCOND, scc_spcond_int, - IRQF_DISABLED, "SCC-B special cond", port); - if (error) - goto fail_free_b_rx; + request_irq(BVME_IRQ_SCCB_SPCOND, scc_spcond_int, IRQF_DISABLED, + "SCC-B special cond", port); { SCC_ACCESS_INIT(port); /* Either channel will do */ @@ -482,23 +393,6 @@ static int bvme6000_scc_init(void) scc_init_drivers(); return 0; - -fail: - free_irq(BVME_IRQ_SCCA_STAT, port); -fail_free_a_tx: - free_irq(BVME_IRQ_SCCA_RX, port); -fail_free_a_stat: - free_irq(BVME_IRQ_SCCA_SPCOND, port); -fail_free_a_rx: - free_irq(BVME_IRQ_SCCB_TX, port); -fail_free_a_spcond: - free_irq(BVME_IRQ_SCCB_STAT, port); -fail_free_b_tx: - free_irq(BVME_IRQ_SCCB_RX, port); -fail_free_b_stat: - free_irq(BVME_IRQ_SCCB_SPCOND, port); -fail_free_b_rx: - return error; } #endif diff --git a/trunk/drivers/dio/dio-sysfs.c b/trunk/drivers/dio/dio-sysfs.c index ee1a3b59bd4e..f46463038847 100644 --- a/trunk/drivers/dio/dio-sysfs.c +++ b/trunk/drivers/dio/dio-sysfs.c @@ -58,25 +58,20 @@ static ssize_t dio_show_resource(struct device *dev, struct device_attribute *at struct dio_dev *d = to_dio_dev(dev); return sprintf(buf, "0x%08lx 0x%08lx 0x%08lx\n", - (unsigned long)dio_resource_start(d), - (unsigned long)dio_resource_end(d), + dio_resource_start(d), dio_resource_end(d), dio_resource_flags(d)); } static DEVICE_ATTR(resource, S_IRUGO, dio_show_resource, NULL); -int dio_create_sysfs_dev_files(struct dio_dev *d) +void dio_create_sysfs_dev_files(struct dio_dev *d) { struct device *dev = &d->dev; - int error; /* current configuration's attributes */ - if ((error = device_create_file(dev, &dev_attr_id)) || - (error = device_create_file(dev, &dev_attr_ipl)) || - (error = device_create_file(dev, &dev_attr_secid)) || - (error = device_create_file(dev, &dev_attr_name)) || - (error = device_create_file(dev, &dev_attr_resource))) - return error; - - return 0; + device_create_file(dev, &dev_attr_id); + device_create_file(dev, &dev_attr_ipl); + device_create_file(dev, &dev_attr_secid); + device_create_file(dev, &dev_attr_name); + device_create_file(dev, &dev_attr_resource); } diff --git a/trunk/drivers/dio/dio.c b/trunk/drivers/dio/dio.c index 10c3c498358c..07f274f853d9 100644 --- a/trunk/drivers/dio/dio.c +++ b/trunk/drivers/dio/dio.c @@ -173,7 +173,6 @@ static int __init dio_init(void) mm_segment_t fs; int i; struct dio_dev *dev; - int error; if (!MACH_IS_HP300) return 0; @@ -183,11 +182,7 @@ static int __init dio_init(void) /* Initialize the DIO bus */ INIT_LIST_HEAD(&dio_bus.devices); strcpy(dio_bus.dev.bus_id, "dio"); - error = device_register(&dio_bus.dev); - if (error) { - pr_err("DIO: Error registering dio_bus\n"); - return error; - } + device_register(&dio_bus.dev); /* Request all resources */ dio_bus.num_resources = (hp300_model == HP_320 ? 1 : 2); @@ -257,15 +252,8 @@ static int __init dio_init(void) if (scode >= DIOII_SCBASE) iounmap(va); - error = device_register(&dev->dev); - if (error) { - pr_err("DIO: Error registering device %s\n", - dev->name); - continue; - } - error = dio_create_sysfs_dev_files(dev); - if (error) - dev_err(&dev->dev, "Error creating sysfs files\n"); + device_register(&dev->dev); + dio_create_sysfs_dev_files(dev); } return 0; } diff --git a/trunk/drivers/infiniband/hw/ehca/ehca_main.c b/trunk/drivers/infiniband/hw/ehca/ehca_main.c index c7b8a506af65..3b77b674cbf6 100644 --- a/trunk/drivers/infiniband/hw/ehca/ehca_main.c +++ b/trunk/drivers/infiniband/hw/ehca/ehca_main.c @@ -955,7 +955,7 @@ void ehca_poll_eqs(unsigned long data) struct ehca_eq *eq = &shca->eq; int max = 3; volatile u64 q_ofs, q_ofs2; - unsigned long flags; + u64 flags; spin_lock_irqsave(&eq->spinlock, flags); q_ofs = eq->ipz_queue.current_q_offset; spin_unlock_irqrestore(&eq->spinlock, flags); diff --git a/trunk/drivers/infiniband/hw/mlx4/main.c b/trunk/drivers/infiniband/hw/mlx4/main.c index 61588bd273bd..dcefe1fceb5c 100644 --- a/trunk/drivers/infiniband/hw/mlx4/main.c +++ b/trunk/drivers/infiniband/hw/mlx4/main.c @@ -543,21 +543,14 @@ static void *mlx4_ib_add(struct mlx4_dev *dev) { static int mlx4_ib_version_printed; struct mlx4_ib_dev *ibdev; - int num_ports = 0; int i; + if (!mlx4_ib_version_printed) { printk(KERN_INFO "%s", mlx4_ib_version); ++mlx4_ib_version_printed; } - mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) - num_ports++; - - /* No point in registering a device with no ports... */ - if (num_ports == 0) - return NULL; - ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev); if (!ibdev) { dev_err(&dev->pdev->dev, "Device struct alloc failed\n"); @@ -581,7 +574,9 @@ static void *mlx4_ib_add(struct mlx4_dev *dev) ibdev->ib_dev.owner = THIS_MODULE; ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; - ibdev->num_ports = num_ports; + ibdev->num_ports = 0; + mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) + ibdev->num_ports++; ibdev->ib_dev.phys_port_cnt = ibdev->num_ports; ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; ibdev->ib_dev.dma_device = &dev->pdev->dev; diff --git a/trunk/drivers/infiniband/hw/nes/nes_cm.c b/trunk/drivers/infiniband/hw/nes/nes_cm.c index a01b4488208b..6ba57e91d7ab 100644 --- a/trunk/drivers/infiniband/hw/nes/nes_cm.c +++ b/trunk/drivers/infiniband/hw/nes/nes_cm.c @@ -778,13 +778,12 @@ static struct nes_cm_node *find_node(struct nes_cm_core *cm_core, unsigned long flags; struct list_head *hte; struct nes_cm_node *cm_node; - __be32 tmp_addr = cpu_to_be32(loc_addr); /* get a handle on the hte */ hte = &cm_core->connected_nodes; nes_debug(NES_DBG_CM, "Searching for an owner node: %pI4:%x from core %p->%p\n", - &tmp_addr, loc_port, cm_core, hte); + &loc_addr, loc_port, cm_core, hte); /* walk list and find cm_node associated with this session ID */ spin_lock_irqsave(&cm_core->ht_lock, flags); @@ -817,7 +816,6 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core, { unsigned long flags; struct nes_cm_listener *listen_node; - __be32 tmp_addr = cpu_to_be32(dst_addr); /* walk list and find cm_node associated with this session ID */ spin_lock_irqsave(&cm_core->listen_list_lock, flags); @@ -835,7 +833,7 @@ static struct nes_cm_listener *find_listener(struct nes_cm_core *cm_core, spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); nes_debug(NES_DBG_CM, "Unable to find listener for %pI4:%x\n", - &tmp_addr, dst_port); + &dst_addr, dst_port); /* no listener */ return NULL; @@ -2061,7 +2059,6 @@ static int mini_cm_recv_pkt(struct nes_cm_core *cm_core, struct tcphdr *tcph; struct nes_cm_info nfo; int skb_handled = 1; - __be32 tmp_daddr, tmp_saddr; if (!skb) return 0; @@ -2077,11 +2074,8 @@ static int mini_cm_recv_pkt(struct nes_cm_core *cm_core, nfo.rem_addr = ntohl(iph->saddr); nfo.rem_port = ntohs(tcph->source); - tmp_daddr = cpu_to_be32(iph->daddr); - tmp_saddr = cpu_to_be32(iph->saddr); - nes_debug(NES_DBG_CM, "Received packet: dest=%pI4:0x%04X src=%pI4:0x%04X\n", - &tmp_daddr, tcph->dest, &tmp_saddr, tcph->source); + &iph->daddr, tcph->dest, &iph->saddr, tcph->source); do { cm_node = find_node(cm_core, diff --git a/trunk/drivers/infiniband/hw/nes/nes_utils.c b/trunk/drivers/infiniband/hw/nes/nes_utils.c index 6f3bc1b6bf22..aa9b7348c728 100644 --- a/trunk/drivers/infiniband/hw/nes/nes_utils.c +++ b/trunk/drivers/infiniband/hw/nes/nes_utils.c @@ -655,7 +655,6 @@ int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 acti struct nes_adapter *nesadapter = nesdev->nesadapter; int arp_index; int err = 0; - __be32 tmp_addr; for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) { if (nesadapter->arp_table[arp_index].ip_addr == ip_addr) @@ -683,9 +682,8 @@ int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 acti /* DELETE or RESOLVE */ if (arp_index == nesadapter->arp_table_size) { - tmp_addr = cpu_to_be32(ip_addr); nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n", - &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete"); + &ip_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete"); return -1; } diff --git a/trunk/drivers/infiniband/ulp/ipoib/ipoib_main.c b/trunk/drivers/infiniband/ulp/ipoib/ipoib_main.c index dce0443f9d69..19e06bc38b39 100644 --- a/trunk/drivers/infiniband/ulp/ipoib/ipoib_main.c +++ b/trunk/drivers/infiniband/ulp/ipoib/ipoib_main.c @@ -711,26 +711,26 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev) neigh = *to_ipoib_neigh(skb->dst->neighbour); - if (unlikely((memcmp(&neigh->dgid.raw, - skb->dst->neighbour->ha + 4, - sizeof(union ib_gid))) || - (neigh->dev != dev))) { - spin_lock_irqsave(&priv->lock, flags); - /* - * It's safe to call ipoib_put_ah() inside - * priv->lock here, because we know that - * path->ah will always hold one more reference, - * so ipoib_put_ah() will never do more than - * decrement the ref count. - */ - if (neigh->ah) + if (neigh->ah) + if (unlikely((memcmp(&neigh->dgid.raw, + skb->dst->neighbour->ha + 4, + sizeof(union ib_gid))) || + (neigh->dev != dev))) { + spin_lock_irqsave(&priv->lock, flags); + /* + * It's safe to call ipoib_put_ah() inside + * priv->lock here, because we know that + * path->ah will always hold one more reference, + * so ipoib_put_ah() will never do more than + * decrement the ref count. + */ ipoib_put_ah(neigh->ah); - list_del(&neigh->list); - ipoib_neigh_free(dev, neigh); - spin_unlock_irqrestore(&priv->lock, flags); - ipoib_path_lookup(skb, dev); - return NETDEV_TX_OK; - } + list_del(&neigh->list); + ipoib_neigh_free(dev, neigh); + spin_unlock_irqrestore(&priv->lock, flags); + ipoib_path_lookup(skb, dev); + return NETDEV_TX_OK; + } if (ipoib_cm_get(neigh)) { if (ipoib_cm_up(neigh)) { diff --git a/trunk/drivers/infiniband/ulp/ipoib/ipoib_multicast.c b/trunk/drivers/infiniband/ulp/ipoib/ipoib_multicast.c index 59d02e0b8df1..a2eb3b9789eb 100644 --- a/trunk/drivers/infiniband/ulp/ipoib/ipoib_multicast.c +++ b/trunk/drivers/infiniband/ulp/ipoib/ipoib_multicast.c @@ -529,9 +529,6 @@ void ipoib_mcast_join_task(struct work_struct *work) if (!priv->broadcast) { struct ipoib_mcast *broadcast; - if (!test_bit(IPOIB_FLAG_ADMIN_UP, &priv->flags)) - return; - broadcast = ipoib_mcast_alloc(dev, 1); if (!broadcast) { ipoib_warn(priv, "failed to allocate broadcast group\n"); diff --git a/trunk/drivers/infiniband/ulp/iser/Kconfig b/trunk/drivers/infiniband/ulp/iser/Kconfig index b411c51842da..77dedba829e6 100644 --- a/trunk/drivers/infiniband/ulp/iser/Kconfig +++ b/trunk/drivers/infiniband/ulp/iser/Kconfig @@ -1,6 +1,6 @@ config INFINIBAND_ISER tristate "iSCSI Extensions for RDMA (iSER)" - depends on SCSI && INET && INFINIBAND_ADDR_TRANS + depends on SCSI && INET select SCSI_ISCSI_ATTRS ---help--- Support for the iSCSI Extensions for RDMA (iSER) Protocol diff --git a/trunk/drivers/input/misc/Kconfig b/trunk/drivers/input/misc/Kconfig index 67e5553f699a..199055db5082 100644 --- a/trunk/drivers/input/misc/Kconfig +++ b/trunk/drivers/input/misc/Kconfig @@ -220,11 +220,4 @@ config HP_SDC_RTC Say Y here if you want to support the built-in real time clock of the HP SDC controller. -config INPUT_PCF50633_PMU - tristate "PCF50633 PMU events" - depends on MFD_PCF50633 - help - Say Y to include support for delivering PMU events via input - layer on NXP PCF50633. - endif diff --git a/trunk/drivers/input/misc/Makefile b/trunk/drivers/input/misc/Makefile index bb62e6efacf3..d7db2aeb8a98 100644 --- a/trunk/drivers/input/misc/Makefile +++ b/trunk/drivers/input/misc/Makefile @@ -21,4 +21,3 @@ obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o obj-$(CONFIG_INPUT_UINPUT) += uinput.o obj-$(CONFIG_INPUT_APANEL) += apanel.o obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o -obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o diff --git a/trunk/drivers/input/misc/pcf50633-input.c b/trunk/drivers/input/misc/pcf50633-input.c deleted file mode 100644 index 039dcb00ebd9..000000000000 --- a/trunk/drivers/input/misc/pcf50633-input.c +++ /dev/null @@ -1,132 +0,0 @@ -/* NXP PCF50633 Input Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte, Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -#include - -#define PCF50633_OOCSTAT_ONKEY 0x01 -#define PCF50633_REG_OOCSTAT 0x12 -#define PCF50633_REG_OOCMODE 0x10 - -struct pcf50633_input { - struct pcf50633 *pcf; - struct input_dev *input_dev; -}; - -static void -pcf50633_input_irq(int irq, void *data) -{ - struct pcf50633_input *input; - int onkey_released; - - input = data; - - /* We report only one event depending on the key press status */ - onkey_released = pcf50633_reg_read(input->pcf, PCF50633_REG_OOCSTAT) - & PCF50633_OOCSTAT_ONKEY; - - if (irq == PCF50633_IRQ_ONKEYF && !onkey_released) - input_report_key(input->input_dev, KEY_POWER, 1); - else if (irq == PCF50633_IRQ_ONKEYR && onkey_released) - input_report_key(input->input_dev, KEY_POWER, 0); - - input_sync(input->input_dev); -} - -static int __devinit pcf50633_input_probe(struct platform_device *pdev) -{ - struct pcf50633_input *input; - struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; - struct input_dev *input_dev; - int ret; - - - input = kzalloc(sizeof(*input), GFP_KERNEL); - if (!input) - return -ENOMEM; - - input_dev = input_allocate_device(); - if (!input_dev) { - kfree(input); - return -ENOMEM; - } - - platform_set_drvdata(pdev, input); - input->pcf = pdata->pcf; - input->input_dev = input_dev; - - input_dev->name = "PCF50633 PMU events"; - input_dev->id.bustype = BUS_I2C; - input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR); - set_bit(KEY_POWER, input_dev->keybit); - - ret = input_register_device(input_dev); - if (ret) { - input_free_device(input_dev); - kfree(input); - return ret; - } - pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ONKEYR, - pcf50633_input_irq, input); - pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ONKEYF, - pcf50633_input_irq, input); - - return 0; -} - -static int __devexit pcf50633_input_remove(struct platform_device *pdev) -{ - struct pcf50633_input *input = platform_get_drvdata(pdev); - - pcf50633_free_irq(input->pcf, PCF50633_IRQ_ONKEYR); - pcf50633_free_irq(input->pcf, PCF50633_IRQ_ONKEYF); - - input_unregister_device(input->input_dev); - kfree(input); - - return 0; -} - -static struct platform_driver pcf50633_input_driver = { - .driver = { - .name = "pcf50633-input", - }, - .probe = pcf50633_input_probe, - .remove = __devexit_p(pcf50633_input_remove), -}; - -static int __init pcf50633_input_init(void) -{ - return platform_driver_register(&pcf50633_input_driver); -} -module_init(pcf50633_input_init); - -static void __exit pcf50633_input_exit(void) -{ - platform_driver_unregister(&pcf50633_input_driver); -} -module_exit(pcf50633_input_exit); - -MODULE_AUTHOR("Balaji Rao "); -MODULE_DESCRIPTION("PCF50633 input driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pcf50633-input"); diff --git a/trunk/drivers/isdn/hardware/mISDN/hfcmulti.c b/trunk/drivers/isdn/hardware/mISDN/hfcmulti.c index 595ba8eb4a07..97f4708b3879 100644 --- a/trunk/drivers/isdn/hardware/mISDN/hfcmulti.c +++ b/trunk/drivers/isdn/hardware/mISDN/hfcmulti.c @@ -3615,7 +3615,7 @@ hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) static void ph_state_change(struct dchannel *dch) { - struct hfc_multi *hc; + struct hfc_multi *hc = dch->hw; int ch, i; if (!dch) { @@ -3623,7 +3623,6 @@ ph_state_change(struct dchannel *dch) __func__); return; } - hc = dch->hw; ch = dch->slot; if (hc->type == 1) { diff --git a/trunk/drivers/isdn/hardware/mISDN/hfcpci.c b/trunk/drivers/isdn/hardware/mISDN/hfcpci.c index f0e14dfcf71d..917bf41a293b 100644 --- a/trunk/drivers/isdn/hardware/mISDN/hfcpci.c +++ b/trunk/drivers/isdn/hardware/mISDN/hfcpci.c @@ -61,7 +61,7 @@ u32 hfc_jiffies; MODULE_AUTHOR("Karsten Keil"); MODULE_LICENSE("GPL"); -module_param(debug, uint, S_IRUGO | S_IWUSR); +module_param(debug, uint, 0); module_param(poll, uint, S_IRUGO | S_IWUSR); enum { diff --git a/trunk/drivers/isdn/mISDN/dsp_cmx.c b/trunk/drivers/isdn/mISDN/dsp_cmx.c index 58c43e429f73..0ac67bff303a 100644 --- a/trunk/drivers/isdn/mISDN/dsp_cmx.c +++ b/trunk/drivers/isdn/mISDN/dsp_cmx.c @@ -1579,7 +1579,7 @@ dsp_cmx_send_member(struct dsp *dsp, int len, s32 *c, int members) schedule_work(&dsp->workq); } -static u32 jittercount; /* counter for jitter check */ +static u32 jittercount; /* counter for jitter check */; struct timer_list dsp_spl_tl; u32 dsp_spl_jiffies; /* calculate the next time to fire */ static u16 dsp_count; /* last sample count */ @@ -1893,7 +1893,7 @@ dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb) /* in case of hardware (echo) */ if (dsp->pcm_slot_tx >= 0) return; - if (dsp->echo) { + if (dsp->echo) nskb = skb_clone(skb, GFP_ATOMIC); if (nskb) { hh = mISDN_HEAD_P(nskb); @@ -1902,7 +1902,6 @@ dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb) skb_queue_tail(&dsp->sendq, nskb); schedule_work(&dsp->workq); } - } return; } /* in case of hardware conference */ diff --git a/trunk/drivers/isdn/mISDN/dsp_pipeline.c b/trunk/drivers/isdn/mISDN/dsp_pipeline.c index 18cf87c113e7..bf999bdc41c3 100644 --- a/trunk/drivers/isdn/mISDN/dsp_pipeline.c +++ b/trunk/drivers/isdn/mISDN/dsp_pipeline.c @@ -110,7 +110,8 @@ int mISDN_dsp_element_register(struct mISDN_dsp_element *elem) } list_add_tail(&entry->list, &dsp_elements); - for (i = 0; i < ARRAY_SIZE(element_attributes); ++i) { + for (i = 0; i < (sizeof(element_attributes) + / sizeof(struct device_attribute)); ++i) ret = device_create_file(&entry->dev, &element_attributes[i]); if (ret) { @@ -118,7 +119,6 @@ int mISDN_dsp_element_register(struct mISDN_dsp_element *elem) __func__); goto err2; } - } #ifdef PIPELINE_DEBUG printk(KERN_DEBUG "%s: %s registered\n", __func__, elem->name); diff --git a/trunk/drivers/mfd/Kconfig b/trunk/drivers/mfd/Kconfig index 06a2b0f7737c..416f9e7286ba 100644 --- a/trunk/drivers/mfd/Kconfig +++ b/trunk/drivers/mfd/Kconfig @@ -217,29 +217,6 @@ config MFD_WM8350_I2C I2C as the control interface. Additional options must be selected to enable support for the functionality of the chip. -config MFD_PCF50633 - tristate "Support for NXP PCF50633" - depends on I2C - help - Say yes here if you have NXP PCF50633 chip on your board. - This core driver provides register access and IRQ handling - facilities, and registers devices for the various functions - so that function-specific drivers can bind to them. - -config PCF50633_ADC - tristate "Support for NXP PCF50633 ADC" - depends on MFD_PCF50633 - help - Say yes here if you want to include support for ADC in the - NXP PCF50633 chip. - -config PCF50633_GPIO - tristate "Support for NXP PCF50633 GPIO" - depends on MFD_PCF50633 - help - Say yes here if you want to include support GPIO for pins on - the PCF50633 chip. - endmenu menu "Multimedia Capabilities Port drivers" diff --git a/trunk/drivers/mfd/Makefile b/trunk/drivers/mfd/Makefile index 3afb5192e4da..0c9418b36c26 100644 --- a/trunk/drivers/mfd/Makefile +++ b/trunk/drivers/mfd/Makefile @@ -37,7 +37,3 @@ endif obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o obj-$(CONFIG_PMIC_DA903X) += da903x.o - -obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o -obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o -obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o \ No newline at end of file diff --git a/trunk/drivers/mfd/dm355evm_msp.c b/trunk/drivers/mfd/dm355evm_msp.c index 7ac12cb0be4a..4214b3f72426 100644 --- a/trunk/drivers/mfd/dm355evm_msp.c +++ b/trunk/drivers/mfd/dm355evm_msp.c @@ -107,9 +107,6 @@ static const u8 msp_gpios[] = { MSP_GPIO(0, SWITCH1), MSP_GPIO(1, SWITCH1), MSP_GPIO(2, SWITCH1), MSP_GPIO(3, SWITCH1), MSP_GPIO(4, SWITCH1), - /* switches on MMC/SD sockets */ - MSP_GPIO(1, SDMMC), MSP_GPIO(2, SDMMC), /* mmc0 WP, nCD */ - MSP_GPIO(3, SDMMC), MSP_GPIO(4, SDMMC), /* mmc1 WP, nCD */ }; #define MSP_GPIO_REG(offset) (msp_gpios[(offset)] >> 3) @@ -307,13 +304,6 @@ static int add_children(struct i2c_client *client) gpio_export(gpio, false); } - /* MMC/SD inputs -- right after the last config input */ - if (client->dev.platform_data) { - void (*mmcsd_setup)(unsigned) = client->dev.platform_data; - - mmcsd_setup(dm355evm_msp_gpio.base + 8 + 5); - } - /* RTC is a 32 bit counter, no alarm */ if (msp_has_rtc()) { child = add_child(client, "rtc-dm355evm", diff --git a/trunk/drivers/mfd/pcf50633-adc.c b/trunk/drivers/mfd/pcf50633-adc.c deleted file mode 100644 index c2d05becfa97..000000000000 --- a/trunk/drivers/mfd/pcf50633-adc.c +++ /dev/null @@ -1,277 +0,0 @@ -/* NXP PCF50633 ADC Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte, Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * NOTE: This driver does not yet support subtractive ADC mode, which means - * you can do only one measurement per read request. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -struct pcf50633_adc_request { - int mux; - int avg; - int result; - void (*callback)(struct pcf50633 *, void *, int); - void *callback_param; - - /* Used in case of sync requests */ - struct completion completion; - -}; - -#define PCF50633_MAX_ADC_FIFO_DEPTH 8 - -struct pcf50633_adc { - struct pcf50633 *pcf; - - /* Private stuff */ - struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH]; - int queue_head; - int queue_tail; - struct mutex queue_mutex; -}; - -static inline struct pcf50633_adc *__to_adc(struct pcf50633 *pcf) -{ - return platform_get_drvdata(pcf->adc_pdev); -} - -static void adc_setup(struct pcf50633 *pcf, int channel, int avg) -{ - channel &= PCF50633_ADCC1_ADCMUX_MASK; - - /* kill ratiometric, but enable ACCSW biasing */ - pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00); - pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01); - - /* start ADC conversion on selected channel */ - pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg | - PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT); -} - -static void trigger_next_adc_job_if_any(struct pcf50633 *pcf) -{ - struct pcf50633_adc *adc = __to_adc(pcf); - int head; - - mutex_lock(&adc->queue_mutex); - - head = adc->queue_head; - - if (!adc->queue[head]) { - mutex_unlock(&adc->queue_mutex); - return; - } - mutex_unlock(&adc->queue_mutex); - - adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); -} - -static int -adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req) -{ - struct pcf50633_adc *adc = __to_adc(pcf); - int head, tail; - - mutex_lock(&adc->queue_mutex); - - head = adc->queue_head; - tail = adc->queue_tail; - - if (adc->queue[tail]) { - mutex_unlock(&adc->queue_mutex); - return -EBUSY; - } - - adc->queue[tail] = req; - adc->queue_tail = (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1); - - mutex_unlock(&adc->queue_mutex); - - trigger_next_adc_job_if_any(pcf); - - return 0; -} - -static void -pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result) -{ - struct pcf50633_adc_request *req = param; - - req->result = result; - complete(&req->completion); -} - -int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) -{ - struct pcf50633_adc_request *req; - - /* req is freed when the result is ready, in interrupt handler */ - req = kzalloc(sizeof(*req), GFP_KERNEL); - if (!req) - return -ENOMEM; - - req->mux = mux; - req->avg = avg; - req->callback = pcf50633_adc_sync_read_callback; - req->callback_param = req; - - init_completion(&req->completion); - adc_enqueue_request(pcf, req); - wait_for_completion(&req->completion); - - return req->result; -} -EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read); - -int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, - void (*callback)(struct pcf50633 *, void *, int), - void *callback_param) -{ - struct pcf50633_adc_request *req; - - /* req is freed when the result is ready, in interrupt handler */ - req = kmalloc(sizeof(*req), GFP_KERNEL); - if (!req) - return -ENOMEM; - - req->mux = mux; - req->avg = avg; - req->callback = callback; - req->callback_param = callback_param; - - adc_enqueue_request(pcf, req); - - return 0; -} -EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); - -static int adc_result(struct pcf50633 *pcf) -{ - u8 adcs1, adcs3; - u16 result; - - adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1); - adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3); - result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK); - - dev_dbg(pcf->dev, "adc result = %d\n", result); - - return result; -} - -static void pcf50633_adc_irq(int irq, void *data) -{ - struct pcf50633_adc *adc = data; - struct pcf50633 *pcf = adc->pcf; - struct pcf50633_adc_request *req; - int head; - - mutex_lock(&adc->queue_mutex); - head = adc->queue_head; - - req = adc->queue[head]; - if (WARN_ON(!req)) { - dev_err(pcf->dev, "pcf50633-adc irq: ADC queue empty!\n"); - mutex_unlock(&adc->queue_mutex); - return; - } - adc->queue[head] = NULL; - adc->queue_head = (head + 1) & - (PCF50633_MAX_ADC_FIFO_DEPTH - 1); - - mutex_unlock(&adc->queue_mutex); - - req->callback(pcf, req->callback_param, adc_result(pcf)); - kfree(req); - - trigger_next_adc_job_if_any(pcf); -} - -static int __devinit pcf50633_adc_probe(struct platform_device *pdev) -{ - struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; - struct pcf50633_adc *adc; - - adc = kzalloc(sizeof(*adc), GFP_KERNEL); - if (!adc) - return -ENOMEM; - - adc->pcf = pdata->pcf; - platform_set_drvdata(pdev, adc); - - pcf50633_register_irq(pdata->pcf, PCF50633_IRQ_ADCRDY, - pcf50633_adc_irq, adc); - - mutex_init(&adc->queue_mutex); - - return 0; -} - -static int __devexit pcf50633_adc_remove(struct platform_device *pdev) -{ - struct pcf50633_adc *adc = platform_get_drvdata(pdev); - int i, head; - - pcf50633_free_irq(adc->pcf, PCF50633_IRQ_ADCRDY); - - mutex_lock(&adc->queue_mutex); - head = adc->queue_head; - - if (WARN_ON(adc->queue[head])) - dev_err(adc->pcf->dev, - "adc driver removed with request pending\n"); - - for (i = 0; i < PCF50633_MAX_ADC_FIFO_DEPTH; i++) - kfree(adc->queue[i]); - - mutex_unlock(&adc->queue_mutex); - kfree(adc); - - return 0; -} - -static struct platform_driver pcf50633_adc_driver = { - .driver = { - .name = "pcf50633-adc", - }, - .probe = pcf50633_adc_probe, - .remove = __devexit_p(pcf50633_adc_remove), -}; - -static int __init pcf50633_adc_init(void) -{ - return platform_driver_register(&pcf50633_adc_driver); -} -module_init(pcf50633_adc_init); - -static void __exit pcf50633_adc_exit(void) -{ - platform_driver_unregister(&pcf50633_adc_driver); -} -module_exit(pcf50633_adc_exit); - -MODULE_AUTHOR("Balaji Rao "); -MODULE_DESCRIPTION("PCF50633 adc driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pcf50633-adc"); - diff --git a/trunk/drivers/mfd/pcf50633-core.c b/trunk/drivers/mfd/pcf50633-core.c deleted file mode 100644 index 24508e28e3fb..000000000000 --- a/trunk/drivers/mfd/pcf50633-core.c +++ /dev/null @@ -1,710 +0,0 @@ -/* NXP PCF50633 Power Management Unit (PMU) driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Harald Welte - * Balaji Rao - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Two MBCS registers used during cold start */ -#define PCF50633_REG_MBCS1 0x4b -#define PCF50633_REG_MBCS2 0x4c -#define PCF50633_MBCS1_USBPRES 0x01 -#define PCF50633_MBCS1_ADAPTPRES 0x01 - -static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data) -{ - int ret; - - ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg, - num, data); - if (ret < 0) - dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg); - - return ret; -} - -static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data) -{ - int ret; - - ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg, - num, data); - if (ret < 0) - dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg); - - return ret; - -} - -/* Read a block of upto 32 regs */ -int pcf50633_read_block(struct pcf50633 *pcf, u8 reg, - int nr_regs, u8 *data) -{ - int ret; - - mutex_lock(&pcf->lock); - ret = __pcf50633_read(pcf, reg, nr_regs, data); - mutex_unlock(&pcf->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_read_block); - -/* Write a block of upto 32 regs */ -int pcf50633_write_block(struct pcf50633 *pcf , u8 reg, - int nr_regs, u8 *data) -{ - int ret; - - mutex_lock(&pcf->lock); - ret = __pcf50633_write(pcf, reg, nr_regs, data); - mutex_unlock(&pcf->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_write_block); - -u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg) -{ - u8 val; - - mutex_lock(&pcf->lock); - __pcf50633_read(pcf, reg, 1, &val); - mutex_unlock(&pcf->lock); - - return val; -} -EXPORT_SYMBOL_GPL(pcf50633_reg_read); - -int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val) -{ - int ret; - - mutex_lock(&pcf->lock); - ret = __pcf50633_write(pcf, reg, 1, &val); - mutex_unlock(&pcf->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_reg_write); - -int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) -{ - int ret; - u8 tmp; - - val &= mask; - - mutex_lock(&pcf->lock); - ret = __pcf50633_read(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - tmp &= ~mask; - tmp |= val; - ret = __pcf50633_write(pcf, reg, 1, &tmp); - -out: - mutex_unlock(&pcf->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask); - -int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val) -{ - int ret; - u8 tmp; - - mutex_lock(&pcf->lock); - ret = __pcf50633_read(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - tmp &= ~val; - ret = __pcf50633_write(pcf, reg, 1, &tmp); - -out: - mutex_unlock(&pcf->lock); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits); - -/* sysfs attributes */ -static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr, - char *buf) -{ - struct pcf50633 *pcf = dev_get_drvdata(dev); - u8 dump[16]; - int n, n1, idx = 0; - char *buf1 = buf; - static u8 address_no_read[] = { /* must be ascending */ - PCF50633_REG_INT1, - PCF50633_REG_INT2, - PCF50633_REG_INT3, - PCF50633_REG_INT4, - PCF50633_REG_INT5, - 0 /* terminator */ - }; - - for (n = 0; n < 256; n += sizeof(dump)) { - for (n1 = 0; n1 < sizeof(dump); n1++) - if (n == address_no_read[idx]) { - idx++; - dump[n1] = 0x00; - } else - dump[n1] = pcf50633_reg_read(pcf, n + n1); - - hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0); - buf1 += strlen(buf1); - *buf1++ = '\n'; - *buf1 = '\0'; - } - - return buf1 - buf; -} -static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL); - -static ssize_t show_resume_reason(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct pcf50633 *pcf = dev_get_drvdata(dev); - int n; - - n = sprintf(buf, "%02x%02x%02x%02x%02x\n", - pcf->resume_reason[0], - pcf->resume_reason[1], - pcf->resume_reason[2], - pcf->resume_reason[3], - pcf->resume_reason[4]); - - return n; -} -static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL); - -static struct attribute *pcf_sysfs_entries[] = { - &dev_attr_dump_regs.attr, - &dev_attr_resume_reason.attr, - NULL, -}; - -static struct attribute_group pcf_attr_group = { - .name = NULL, /* put in device directory */ - .attrs = pcf_sysfs_entries, -}; - -int pcf50633_register_irq(struct pcf50633 *pcf, int irq, - void (*handler) (int, void *), void *data) -{ - if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler) - return -EINVAL; - - if (WARN_ON(pcf->irq_handler[irq].handler)) - return -EBUSY; - - mutex_lock(&pcf->lock); - pcf->irq_handler[irq].handler = handler; - pcf->irq_handler[irq].data = data; - mutex_unlock(&pcf->lock); - - return 0; -} -EXPORT_SYMBOL_GPL(pcf50633_register_irq); - -int pcf50633_free_irq(struct pcf50633 *pcf, int irq) -{ - if (irq < 0 || irq > PCF50633_NUM_IRQ) - return -EINVAL; - - mutex_lock(&pcf->lock); - pcf->irq_handler[irq].handler = NULL; - mutex_unlock(&pcf->lock); - - return 0; -} -EXPORT_SYMBOL_GPL(pcf50633_free_irq); - -static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) -{ - u8 reg, bits, tmp; - int ret = 0, idx; - - idx = irq >> 3; - reg = PCF50633_REG_INT1M + idx; - bits = 1 << (irq & 0x07); - - mutex_lock(&pcf->lock); - - if (mask) { - ret = __pcf50633_read(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - tmp |= bits; - - ret = __pcf50633_write(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - pcf->mask_regs[idx] &= ~bits; - pcf->mask_regs[idx] |= bits; - } else { - ret = __pcf50633_read(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - tmp &= ~bits; - - ret = __pcf50633_write(pcf, reg, 1, &tmp); - if (ret < 0) - goto out; - - pcf->mask_regs[idx] &= ~bits; - } -out: - mutex_unlock(&pcf->lock); - - return ret; -} - -int pcf50633_irq_mask(struct pcf50633 *pcf, int irq) -{ - dev_info(pcf->dev, "Masking IRQ %d\n", irq); - - return __pcf50633_irq_mask_set(pcf, irq, 1); -} -EXPORT_SYMBOL_GPL(pcf50633_irq_mask); - -int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq) -{ - dev_info(pcf->dev, "Unmasking IRQ %d\n", irq); - - return __pcf50633_irq_mask_set(pcf, irq, 0); -} -EXPORT_SYMBOL_GPL(pcf50633_irq_unmask); - -int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq) -{ - u8 reg, bits; - - reg = irq >> 3; - bits = 1 << (irq & 0x07); - - return pcf->mask_regs[reg] & bits; -} -EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get); - -static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq) -{ - if (pcf->irq_handler[irq].handler) - pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data); -} - -/* Maximum amount of time ONKEY is held before emergency action is taken */ -#define PCF50633_ONKEY1S_TIMEOUT 8 - -static void pcf50633_irq_worker(struct work_struct *work) -{ - struct pcf50633 *pcf; - int ret, i, j; - u8 pcf_int[5], chgstat; - - pcf = container_of(work, struct pcf50633, irq_work); - - /* Read the 5 INT regs in one transaction */ - ret = pcf50633_read_block(pcf, PCF50633_REG_INT1, - ARRAY_SIZE(pcf_int), pcf_int); - if (ret != ARRAY_SIZE(pcf_int)) { - dev_err(pcf->dev, "Error reading INT registers\n"); - - /* - * If this doesn't ACK the interrupt to the chip, we'll be - * called once again as we're level triggered. - */ - goto out; - } - - /* We immediately read the usb and adapter status. We thus make sure - * only of USBINS/USBREM IRQ handlers are called */ - if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) { - chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); - if (chgstat & (0x3 << 4)) - pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM); - else - pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS); - } - - /* Make sure only one of ADPINS or ADPREM is set */ - if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) { - chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); - if (chgstat & (0x3 << 4)) - pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM); - else - pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS); - } - - dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x " - "INT4=0x%02x INT5=0x%02x\n", pcf_int[0], - pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]); - - /* Some revisions of the chip don't have a 8s standby mode on - * ONKEY1S press. We try to manually do it in such cases. */ - if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) { - dev_info(pcf->dev, "ONKEY1S held for %d secs\n", - pcf->onkey1s_held); - if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT) - if (pcf->pdata->force_shutdown) - pcf->pdata->force_shutdown(pcf); - } - - if (pcf_int[2] & PCF50633_INT3_ONKEY1S) { - dev_info(pcf->dev, "ONKEY1S held\n"); - pcf->onkey1s_held = 1 ; - - /* Unmask IRQ_SECOND */ - pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, - PCF50633_INT1_SECOND); - - /* Unmask IRQ_ONKEYR */ - pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M, - PCF50633_INT2_ONKEYR); - } - - if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) { - pcf->onkey1s_held = 0; - - /* Mask SECOND and ONKEYR interrupts */ - if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) - pcf50633_reg_set_bit_mask(pcf, - PCF50633_REG_INT1M, - PCF50633_INT1_SECOND, - PCF50633_INT1_SECOND); - - if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) - pcf50633_reg_set_bit_mask(pcf, - PCF50633_REG_INT2M, - PCF50633_INT2_ONKEYR, - PCF50633_INT2_ONKEYR); - } - - /* Have we just resumed ? */ - if (pcf->is_suspended) { - pcf->is_suspended = 0; - - /* Set the resume reason filtering out non resumers */ - for (i = 0; i < ARRAY_SIZE(pcf_int); i++) - pcf->resume_reason[i] = pcf_int[i] & - pcf->pdata->resumers[i]; - - /* Make sure we don't pass on any ONKEY events to - * userspace now */ - pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF); - } - - for (i = 0; i < ARRAY_SIZE(pcf_int); i++) { - /* Unset masked interrupts */ - pcf_int[i] &= ~pcf->mask_regs[i]; - - for (j = 0; j < 8 ; j++) - if (pcf_int[i] & (1 << j)) - pcf50633_irq_call_handler(pcf, (i * 8) + j); - } - -out: - put_device(pcf->dev); - enable_irq(pcf->irq); -} - -static irqreturn_t pcf50633_irq(int irq, void *data) -{ - struct pcf50633 *pcf = data; - - dev_dbg(pcf->dev, "pcf50633_irq\n"); - - get_device(pcf->dev); - disable_irq(pcf->irq); - schedule_work(&pcf->irq_work); - - return IRQ_HANDLED; -} - -static void -pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name, - struct platform_device **pdev) -{ - struct pcf50633_subdev_pdata *subdev_pdata; - int ret; - - *pdev = platform_device_alloc(name, -1); - if (!*pdev) { - dev_err(pcf->dev, "Falied to allocate %s\n", name); - return; - } - - subdev_pdata = kmalloc(sizeof(*subdev_pdata), GFP_KERNEL); - if (!subdev_pdata) { - dev_err(pcf->dev, "Error allocating subdev pdata\n"); - platform_device_put(*pdev); - } - - subdev_pdata->pcf = pcf; - platform_device_add_data(*pdev, subdev_pdata, sizeof(*subdev_pdata)); - - (*pdev)->dev.parent = pcf->dev; - - ret = platform_device_add(*pdev); - if (ret) { - dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret); - platform_device_put(*pdev); - *pdev = NULL; - } -} - -#ifdef CONFIG_PM -static int pcf50633_suspend(struct device *dev, pm_message_t state) -{ - struct pcf50633 *pcf; - int ret = 0, i; - u8 res[5]; - - pcf = dev_get_drvdata(dev); - - /* Make sure our interrupt handlers are not called - * henceforth */ - disable_irq(pcf->irq); - - /* Make sure that any running IRQ worker has quit */ - cancel_work_sync(&pcf->irq_work); - - /* Save the masks */ - ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M, - ARRAY_SIZE(pcf->suspend_irq_masks), - pcf->suspend_irq_masks); - if (ret < 0) { - dev_err(pcf->dev, "error saving irq masks\n"); - goto out; - } - - /* Write wakeup irq masks */ - for (i = 0; i < ARRAY_SIZE(res); i++) - res[i] = ~pcf->pdata->resumers[i]; - - ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, - ARRAY_SIZE(res), &res[0]); - if (ret < 0) { - dev_err(pcf->dev, "error writing wakeup irq masks\n"); - goto out; - } - - pcf->is_suspended = 1; - -out: - return ret; -} - -static int pcf50633_resume(struct device *dev) -{ - struct pcf50633 *pcf; - int ret; - - pcf = dev_get_drvdata(dev); - - /* Write the saved mask registers */ - ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, - ARRAY_SIZE(pcf->suspend_irq_masks), - pcf->suspend_irq_masks); - if (ret < 0) - dev_err(pcf->dev, "Error restoring saved suspend masks\n"); - - /* Restore regulators' state */ - - - get_device(pcf->dev); - - /* - * Clear any pending interrupts and set resume reason if any. - * This will leave with enable_irq() - */ - pcf50633_irq_worker(&pcf->irq_work); - - return 0; -} -#else -#define pcf50633_suspend NULL -#define pcf50633_resume NULL -#endif - -static int __devinit pcf50633_probe(struct i2c_client *client, - const struct i2c_device_id *ids) -{ - struct pcf50633 *pcf; - struct pcf50633_platform_data *pdata = client->dev.platform_data; - int i, ret = 0; - int version, variant; - - pcf = kzalloc(sizeof(*pcf), GFP_KERNEL); - if (!pcf) - return -ENOMEM; - - pcf->pdata = pdata; - - mutex_init(&pcf->lock); - - i2c_set_clientdata(client, pcf); - pcf->dev = &client->dev; - pcf->i2c_client = client; - pcf->irq = client->irq; - - INIT_WORK(&pcf->irq_work, pcf50633_irq_worker); - - version = pcf50633_reg_read(pcf, 0); - variant = pcf50633_reg_read(pcf, 1); - if (version < 0 || variant < 0) { - dev_err(pcf->dev, "Unable to probe pcf50633\n"); - ret = -ENODEV; - goto err; - } - - dev_info(pcf->dev, "Probed device version %d variant %d\n", - version, variant); - - /* Enable all interrupts except RTC SECOND */ - pcf->mask_regs[0] = 0x80; - pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); - pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00); - pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00); - pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00); - pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00); - - /* Create sub devices */ - pcf50633_client_dev_register(pcf, "pcf50633-input", - &pcf->input_pdev); - pcf50633_client_dev_register(pcf, "pcf50633-rtc", - &pcf->rtc_pdev); - pcf50633_client_dev_register(pcf, "pcf50633-mbc", - &pcf->mbc_pdev); - pcf50633_client_dev_register(pcf, "pcf50633-adc", - &pcf->adc_pdev); - - for (i = 0; i < PCF50633_NUM_REGULATORS; i++) { - struct platform_device *pdev; - - pdev = platform_device_alloc("pcf50633-regltr", i); - if (!pdev) { - dev_err(pcf->dev, "Cannot create regulator\n"); - continue; - } - - pdev->dev.parent = pcf->dev; - pdev->dev.platform_data = &pdata->reg_init_data[i]; - pdev->dev.driver_data = pcf; - pcf->regulator_pdev[i] = pdev; - - platform_device_add(pdev); - } - - if (client->irq) { - set_irq_handler(client->irq, handle_level_irq); - ret = request_irq(client->irq, pcf50633_irq, - IRQF_TRIGGER_LOW, "pcf50633", pcf); - - if (ret) { - dev_err(pcf->dev, "Failed to request IRQ %d\n", ret); - goto err; - } - } else { - dev_err(pcf->dev, "No IRQ configured\n"); - goto err; - } - - if (enable_irq_wake(client->irq) < 0) - dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source" - "in this hardware revision", client->irq); - - ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group); - if (ret) - dev_err(pcf->dev, "error creating sysfs entries\n"); - - if (pdata->probe_done) - pdata->probe_done(pcf); - - return 0; - -err: - kfree(pcf); - return ret; -} - -static int __devexit pcf50633_remove(struct i2c_client *client) -{ - struct pcf50633 *pcf = i2c_get_clientdata(client); - int i; - - free_irq(pcf->irq, pcf); - - platform_device_unregister(pcf->input_pdev); - platform_device_unregister(pcf->rtc_pdev); - platform_device_unregister(pcf->mbc_pdev); - platform_device_unregister(pcf->adc_pdev); - - for (i = 0; i < PCF50633_NUM_REGULATORS; i++) - platform_device_unregister(pcf->regulator_pdev[i]); - - kfree(pcf); - - return 0; -} - -static struct i2c_device_id pcf50633_id_table[] = { - {"pcf50633", 0x73}, -}; - -static struct i2c_driver pcf50633_driver = { - .driver = { - .name = "pcf50633", - .suspend = pcf50633_suspend, - .resume = pcf50633_resume, - }, - .id_table = pcf50633_id_table, - .probe = pcf50633_probe, - .remove = __devexit_p(pcf50633_remove), -}; - -static int __init pcf50633_init(void) -{ - return i2c_add_driver(&pcf50633_driver); -} - -static void __exit pcf50633_exit(void) -{ - i2c_del_driver(&pcf50633_driver); -} - -MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU"); -MODULE_AUTHOR("Harald Welte "); -MODULE_LICENSE("GPL"); - -module_init(pcf50633_init); -module_exit(pcf50633_exit); diff --git a/trunk/drivers/mfd/pcf50633-gpio.c b/trunk/drivers/mfd/pcf50633-gpio.c deleted file mode 100644 index 2fa2eca5c9cc..000000000000 --- a/trunk/drivers/mfd/pcf50633-gpio.c +++ /dev/null @@ -1,118 +0,0 @@ -/* NXP PCF50633 GPIO Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte, Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include - -#include -#include - -enum pcf50633_regulator_id { - PCF50633_REGULATOR_AUTO, - PCF50633_REGULATOR_DOWN1, - PCF50633_REGULATOR_DOWN2, - PCF50633_REGULATOR_LDO1, - PCF50633_REGULATOR_LDO2, - PCF50633_REGULATOR_LDO3, - PCF50633_REGULATOR_LDO4, - PCF50633_REGULATOR_LDO5, - PCF50633_REGULATOR_LDO6, - PCF50633_REGULATOR_HCLDO, - PCF50633_REGULATOR_MEMLDO, -}; - -#define PCF50633_REG_AUTOOUT 0x1a -#define PCF50633_REG_DOWN1OUT 0x1e -#define PCF50633_REG_DOWN2OUT 0x22 -#define PCF50633_REG_MEMLDOOUT 0x26 -#define PCF50633_REG_LDO1OUT 0x2d -#define PCF50633_REG_LDO2OUT 0x2f -#define PCF50633_REG_LDO3OUT 0x31 -#define PCF50633_REG_LDO4OUT 0x33 -#define PCF50633_REG_LDO5OUT 0x35 -#define PCF50633_REG_LDO6OUT 0x37 -#define PCF50633_REG_HCLDOOUT 0x39 - -static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = { - [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT, - [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT, - [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT, - [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT, - [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT, - [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT, - [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT, - [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT, - [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT, - [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT, - [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT, -}; - -int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) -{ - u8 reg; - - reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; - - return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); -} -EXPORT_SYMBOL_GPL(pcf50633_gpio_set); - -u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio) -{ - u8 reg, val; - - reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; - val = pcf50633_reg_read(pcf, reg) & 0x07; - - return val; -} -EXPORT_SYMBOL_GPL(pcf50633_gpio_get); - -int pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert) -{ - u8 val, reg; - - reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; - val = !!invert << 3; - - return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); -} -EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set); - -int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio) -{ - u8 reg, val; - - reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; - val = pcf50633_reg_read(pcf, reg); - - return val & (1 << 3); -} -EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get); - -int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf, - int gpio, int regulator, int on) -{ - u8 reg, val, mask; - - /* the *ENA register is always one after the *OUT register */ - reg = pcf50633_regulator_registers[regulator] + 1; - - val = !!on << (gpio - PCF50633_GPIO1); - mask = 1 << (gpio - PCF50633_GPIO1); - - return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); -} -EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set); diff --git a/trunk/drivers/mfd/sm501.c b/trunk/drivers/mfd/sm501.c index 0e5761f12634..170f9d47c2f9 100644 --- a/trunk/drivers/mfd/sm501.c +++ b/trunk/drivers/mfd/sm501.c @@ -41,7 +41,6 @@ struct sm501_gpio_chip { struct gpio_chip gpio; struct sm501_gpio *ourgpio; /* to get back to parent. */ void __iomem *regbase; - void __iomem *control; /* address of control reg. */ }; struct sm501_gpio { @@ -909,25 +908,6 @@ static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) return result & 1UL; } -static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, - unsigned long bit) -{ - unsigned long ctrl; - - /* check and modify if this pin is not set as gpio. */ - - if (readl(smchip->control) & bit) { - dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, - "changing mode of gpio, bit %08lx\n", bit); - - ctrl = readl(smchip->control); - ctrl &= ~bit; - writel(ctrl, smchip->control); - - sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); - } -} - static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { @@ -949,8 +929,6 @@ static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value) writel(val, regs); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); - sm501_gpio_ensure_gpio(smchip, bit); - spin_unlock_irqrestore(&smgpio->lock, save); } @@ -963,8 +941,8 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) unsigned long save; unsigned long ddr; - dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", - __func__, chip, offset); + dev_info(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", + __func__, chip, offset); spin_lock_irqsave(&smgpio->lock, save); @@ -972,8 +950,6 @@ static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); sm501_sync_regs(sm501_gpio_to_dev(smgpio)); - sm501_gpio_ensure_gpio(smchip, bit); - spin_unlock_irqrestore(&smgpio->lock, save); return 0; @@ -1036,11 +1012,9 @@ static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm, if (base > 0) base += 32; chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; - chip->control = sm->regs + SM501_GPIO63_32_CONTROL; gchip->label = "SM501-HIGH"; } else { chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; - chip->control = sm->regs + SM501_GPIO31_0_CONTROL; gchip->label = "SM501-LOW"; } diff --git a/trunk/drivers/mfd/twl4030-core.c b/trunk/drivers/mfd/twl4030-core.c index e7ab0035d305..b59c385cbc12 100644 --- a/trunk/drivers/mfd/twl4030-core.c +++ b/trunk/drivers/mfd/twl4030-core.c @@ -38,9 +38,6 @@ #include #include -#ifdef CONFIG_ARM -#include -#endif /* * The TWL4030 "Triton 2" is one of a family of a multi-function "Power @@ -649,7 +646,7 @@ static inline int __init unprotect_pm_master(void) return e; } -static void __init clocks_init(struct device *dev) +static void __init clocks_init(void) { int e = 0; struct clk *osc; @@ -658,9 +655,9 @@ static void __init clocks_init(struct device *dev) #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) if (cpu_is_omap2430()) - osc = clk_get(dev, "osc_ck"); + osc = clk_get(NULL, "osc_ck"); else - osc = clk_get(dev, "osc_sys_ck"); + osc = clk_get(NULL, "osc_sys_ck"); if (IS_ERR(osc)) { printk(KERN_WARNING "Skipping twl4030 internal clock init and " @@ -776,7 +773,7 @@ twl4030_probe(struct i2c_client *client, const struct i2c_device_id *id) inuse = true; /* setup clock framework */ - clocks_init(&client->dev); + clocks_init(); /* Maybe init the T2 Interrupt subsystem */ if (client->irq diff --git a/trunk/drivers/net/3c503.c b/trunk/drivers/net/3c503.c index 5b91a85fe107..c092c3929224 100644 --- a/trunk/drivers/net/3c503.c +++ b/trunk/drivers/net/3c503.c @@ -177,7 +177,6 @@ static const struct net_device_ops el2_netdev_ops = { .ndo_get_stats = eip_get_stats, .ndo_set_multicast_list = eip_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = eip_poll, diff --git a/trunk/drivers/net/3c59x.c b/trunk/drivers/net/3c59x.c index cdbbb6226fc5..665e7fdf27a1 100644 --- a/trunk/drivers/net/3c59x.c +++ b/trunk/drivers/net/3c59x.c @@ -3109,8 +3109,6 @@ static void acpi_set_WOL(struct net_device *dev) struct vortex_private *vp = netdev_priv(dev); void __iomem *ioaddr = vp->ioaddr; - device_set_wakeup_enable(vp->gendev, vp->enable_wol); - if (vp->enable_wol) { /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ EL3WINDOW(7); diff --git a/trunk/drivers/net/8139cp.c b/trunk/drivers/net/8139cp.c index 4e19ae3ce6be..dd7ac8290aec 100644 --- a/trunk/drivers/net/8139cp.c +++ b/trunk/drivers/net/8139cp.c @@ -1821,7 +1821,6 @@ static const struct net_device_ops cp_netdev_ops = { .ndo_open = cp_open, .ndo_stop = cp_close, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_set_multicast_list = cp_set_rx_mode, .ndo_get_stats = cp_get_stats, .ndo_do_ioctl = cp_ioctl, @@ -1833,7 +1832,6 @@ static const struct net_device_ops cp_netdev_ops = { #ifdef BROKEN .ndo_change_mtu = cp_change_mtu, #endif - #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = cp_poll_controller, #endif diff --git a/trunk/drivers/net/8139too.c b/trunk/drivers/net/8139too.c index a5b24202d564..fe370f805793 100644 --- a/trunk/drivers/net/8139too.c +++ b/trunk/drivers/net/8139too.c @@ -917,7 +917,6 @@ static const struct net_device_ops rtl8139_netdev_ops = { .ndo_stop = rtl8139_close, .ndo_get_stats = rtl8139_get_stats, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_start_xmit = rtl8139_start_xmit, .ndo_set_multicast_list = rtl8139_set_rx_mode, .ndo_do_ioctl = netdev_ioctl, @@ -925,6 +924,7 @@ static const struct net_device_ops rtl8139_netdev_ops = { #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = rtl8139_poll_controller, #endif + }; static int __devinit rtl8139_init_one (struct pci_dev *pdev, diff --git a/trunk/drivers/net/8390.c b/trunk/drivers/net/8390.c index ec3e22e6306f..fbe609a51e02 100644 --- a/trunk/drivers/net/8390.c +++ b/trunk/drivers/net/8390.c @@ -63,7 +63,6 @@ const struct net_device_ops ei_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/8390p.c b/trunk/drivers/net/8390p.c index da863c91d1d0..ee70b358a816 100644 --- a/trunk/drivers/net/8390p.c +++ b/trunk/drivers/net/8390p.c @@ -68,7 +68,6 @@ const struct net_device_ops eip_netdev_ops = { .ndo_get_stats = eip_get_stats, .ndo_set_multicast_list = eip_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = eip_poll, diff --git a/trunk/drivers/net/Kconfig b/trunk/drivers/net/Kconfig index 9fe8cb7d43ac..65afda4a62d9 100644 --- a/trunk/drivers/net/Kconfig +++ b/trunk/drivers/net/Kconfig @@ -1600,7 +1600,7 @@ config 8139_OLD_RX_RESET old RX-reset behavior. If unsure, say N. config R6040 - tristate "RDC R6040 Fast Ethernet Adapter support" + tristate "RDC R6040 Fast Ethernet Adapter support (EXPERIMENTAL)" depends on NET_PCI && PCI select CRC32 select MII diff --git a/trunk/drivers/net/acenic.c b/trunk/drivers/net/acenic.c index 9589d620639d..5b396ff6c83f 100644 --- a/trunk/drivers/net/acenic.c +++ b/trunk/drivers/net/acenic.c @@ -460,7 +460,6 @@ static const struct net_device_ops ace_netdev_ops = { .ndo_get_stats = ace_get_stats, .ndo_start_xmit = ace_start_xmit, .ndo_set_multicast_list = ace_set_multicast_list, - .ndo_validate_addr = eth_validate_addr, .ndo_set_mac_address = ace_set_mac_addr, .ndo_change_mtu = ace_change_mtu, #if ACENIC_DO_VLAN diff --git a/trunk/drivers/net/arm/etherh.c b/trunk/drivers/net/arm/etherh.c index 745ac188babe..6278606d1049 100644 --- a/trunk/drivers/net/arm/etherh.c +++ b/trunk/drivers/net/arm/etherh.c @@ -646,7 +646,6 @@ static const struct net_device_ops etherh_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_addr = eth_set_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/arm/ks8695net.c b/trunk/drivers/net/arm/ks8695net.c index 1cf2f949c0b4..9ad22d1b00fd 100644 --- a/trunk/drivers/net/arm/ks8695net.c +++ b/trunk/drivers/net/arm/ks8695net.c @@ -1357,7 +1357,6 @@ static const struct net_device_ops ks8695_netdev_ops = { .ndo_start_xmit = ks8695_start_xmit, .ndo_tx_timeout = ks8695_timeout, .ndo_set_mac_address = ks8695_set_mac, - .ndo_validate_addr = eth_validate_addr, .ndo_set_multicast_list = ks8695_set_multicast, }; diff --git a/trunk/drivers/net/b44.c b/trunk/drivers/net/b44.c index 5ae131c147f9..6926ebedfdc9 100644 --- a/trunk/drivers/net/b44.c +++ b/trunk/drivers/net/b44.c @@ -73,8 +73,8 @@ (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP)) #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1)) -#define RX_PKT_OFFSET (RX_HEADER_LEN + 2) -#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET) +#define RX_PKT_OFFSET 30 +#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64) /* minimum number of free TX descriptors required to wake up TX process */ #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4) @@ -682,6 +682,7 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) } rh = (struct rx_header *) skb->data; + skb_reserve(skb, RX_PKT_OFFSET); rh->len = 0; rh->flags = 0; @@ -692,13 +693,13 @@ static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked) if (src_map != NULL) src_map->skb = NULL; - ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ); + ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET)); if (dest_idx == (B44_RX_RING_SIZE - 1)) ctrl |= DESC_CTRL_EOT; dp = &bp->rx_ring[dest_idx]; dp->ctrl = cpu_to_le32(ctrl); - dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset); + dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset); if (bp->flags & B44_FLAG_RX_RING_HACK) b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma, @@ -808,8 +809,8 @@ static int b44_rx(struct b44 *bp, int budget) ssb_dma_unmap_single(bp->sdev, map, skb_size, DMA_FROM_DEVICE); /* Leave out rx_header */ - skb_put(skb, len + RX_PKT_OFFSET); - skb_pull(skb, RX_PKT_OFFSET); + skb_put(skb, len + RX_PKT_OFFSET); + skb_pull(skb, RX_PKT_OFFSET); } else { struct sk_buff *copy_skb; diff --git a/trunk/drivers/net/cxgb3/adapter.h b/trunk/drivers/net/cxgb3/adapter.h index a89d8cc51205..5b346f9eaa8b 100644 --- a/trunk/drivers/net/cxgb3/adapter.h +++ b/trunk/drivers/net/cxgb3/adapter.h @@ -50,17 +50,12 @@ struct vlan_group; struct adapter; struct sge_qset; -enum { /* rx_offload flags */ - T3_RX_CSUM = 1 << 0, - T3_LRO = 1 << 1, -}; - struct port_info { struct adapter *adapter; struct vlan_group *vlan_grp; struct sge_qset *qs; u8 port_id; - u8 rx_offload; + u8 rx_csum_offload; u8 nqsets; u8 first_qset; struct cphy phy; diff --git a/trunk/drivers/net/cxgb3/cxgb3_main.c b/trunk/drivers/net/cxgb3/cxgb3_main.c index 0089746b8d02..2847f947499d 100644 --- a/trunk/drivers/net/cxgb3/cxgb3_main.c +++ b/trunk/drivers/net/cxgb3/cxgb3_main.c @@ -546,7 +546,7 @@ static int setup_sge_qsets(struct adapter *adap) pi->qs = &adap->sge.qs[pi->first_qset]; for (j = pi->first_qset; j < pi->first_qset + pi->nqsets; ++j, ++qset_idx) { - set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO); + set_qset_lro(dev, qset_idx, pi->rx_csum_offload); err = t3_sge_alloc_qset(adap, qset_idx, 1, (adap->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, @@ -1657,19 +1657,17 @@ static u32 get_rx_csum(struct net_device *dev) { struct port_info *p = netdev_priv(dev); - return p->rx_offload & T3_RX_CSUM; + return p->rx_csum_offload; } static int set_rx_csum(struct net_device *dev, u32 data) { struct port_info *p = netdev_priv(dev); - if (data) { - p->rx_offload |= T3_RX_CSUM; - } else { + p->rx_csum_offload = data; + if (!data) { int i; - p->rx_offload &= ~(T3_RX_CSUM | T3_LRO); for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) set_qset_lro(dev, i, 0); } @@ -1832,18 +1830,15 @@ static int cxgb3_set_flags(struct net_device *dev, u32 data) int i; if (data & ETH_FLAG_LRO) { - if (!(pi->rx_offload & T3_RX_CSUM)) + if (!pi->rx_csum_offload) return -EINVAL; - pi->rx_offload |= T3_LRO; for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) set_qset_lro(dev, i, 1); - } else { - pi->rx_offload &= ~T3_LRO; + } else for (i = pi->first_qset; i < pi->first_qset + pi->nqsets; i++) set_qset_lro(dev, i, 0); - } return 0; } @@ -1931,7 +1926,7 @@ static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr) pi = adap2pinfo(adapter, i); if (t.qset_idx >= pi->first_qset && t.qset_idx < pi->first_qset + pi->nqsets && - !(pi->rx_offload & T3_RX_CSUM)) + !pi->rx_csum_offload) return -EINVAL; } @@ -2951,7 +2946,7 @@ static int __devinit init_one(struct pci_dev *pdev, adapter->port[i] = netdev; pi = netdev_priv(netdev); pi->adapter = adapter; - pi->rx_offload = T3_RX_CSUM | T3_LRO; + pi->rx_csum_offload = 1; pi->port_id = i; netif_carrier_off(netdev); netif_tx_stop_all_queues(netdev); @@ -2960,7 +2955,6 @@ static int __devinit init_one(struct pci_dev *pdev, netdev->mem_end = mmio_start + mmio_len - 1; netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; netdev->features |= NETIF_F_LLTX; - netdev->features |= NETIF_F_LRO; if (pci_using_dac) netdev->features |= NETIF_F_HIGHDMA; diff --git a/trunk/drivers/net/cxgb3/sge.c b/trunk/drivers/net/cxgb3/sge.c index 14f9fb3e8795..6c641a889471 100644 --- a/trunk/drivers/net/cxgb3/sge.c +++ b/trunk/drivers/net/cxgb3/sge.c @@ -1932,7 +1932,7 @@ static void rx_eth(struct adapter *adap, struct sge_rspq *rq, skb_pull(skb, sizeof(*p) + pad); skb->protocol = eth_type_trans(skb, adap->port[p->iff]); pi = netdev_priv(skb->dev); - if ((pi->rx_offload & T3_RX_CSUM) && p->csum_valid && p->csum == htons(0xffff) && + if (pi->rx_csum_offload && p->csum_valid && p->csum == htons(0xffff) && !p->fragment) { qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; skb->ip_summed = CHECKSUM_UNNECESSARY; diff --git a/trunk/drivers/net/e1000e/ich8lan.c b/trunk/drivers/net/e1000e/ich8lan.c index e415e81ecd3e..f2a5963b5a95 100644 --- a/trunk/drivers/net/e1000e/ich8lan.c +++ b/trunk/drivers/net/e1000e/ich8lan.c @@ -390,8 +390,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) } static DEFINE_MUTEX(nvm_mutex); -static pid_t nvm_owner_pid = -1; -static char nvm_owner_name[TASK_COMM_LEN] = ""; +static pid_t nvm_owner = -1; /** * e1000_acquire_swflag_ich8lan - Acquire software control flag @@ -409,15 +408,11 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) might_sleep(); if (!mutex_trylock(&nvm_mutex)) { - WARN(1, KERN_ERR "e1000e mutex contention. Owned by process " - "%s (pid %d), required by process %s (pid %d)\n", - nvm_owner_name, nvm_owner_pid, - current->comm, current->pid); - + WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n", + nvm_owner); mutex_lock(&nvm_mutex); } - nvm_owner_pid = current->pid; - strncpy(nvm_owner_name, current->comm, TASK_COMM_LEN); + nvm_owner = current->pid; while (timeout) { extcnf_ctrl = er32(EXTCNF_CTRL); @@ -435,8 +430,7 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ew32(EXTCNF_CTRL, extcnf_ctrl); - nvm_owner_pid = -1; - strcpy(nvm_owner_name, ""); + nvm_owner = -1; mutex_unlock(&nvm_mutex); return -E1000_ERR_CONFIG; } @@ -460,8 +454,7 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; ew32(EXTCNF_CTRL, extcnf_ctrl); - nvm_owner_pid = -1; - strcpy(nvm_owner_name, ""); + nvm_owner = -1; mutex_unlock(&nvm_mutex); } diff --git a/trunk/drivers/net/e2100.c b/trunk/drivers/net/e2100.c index b07ba1924de0..20eb05cddb83 100644 --- a/trunk/drivers/net/e2100.c +++ b/trunk/drivers/net/e2100.c @@ -169,7 +169,6 @@ static const struct net_device_ops e21_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/enic/enic_main.c b/trunk/drivers/net/enic/enic_main.c index 7d60551d538f..d039e16f2763 100644 --- a/trunk/drivers/net/enic/enic_main.c +++ b/trunk/drivers/net/enic/enic_main.c @@ -1599,7 +1599,6 @@ static const struct net_device_ops enic_netdev_ops = { .ndo_start_xmit = enic_hard_start_xmit, .ndo_get_stats = enic_get_stats, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_set_multicast_list = enic_set_multicast_list, .ndo_change_mtu = enic_change_mtu, .ndo_vlan_rx_register = enic_vlan_rx_register, diff --git a/trunk/drivers/net/forcedeth.c b/trunk/drivers/net/forcedeth.c index 5b910cf63740..5b68dc20168d 100644 --- a/trunk/drivers/net/forcedeth.c +++ b/trunk/drivers/net/forcedeth.c @@ -13,7 +13,7 @@ * Copyright (C) 2004 Andrew de Quincey (wol support) * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane * IRQ rate fixes, bigendian fixes, cleanups, verification) - * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation + * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,7 +39,7 @@ * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few * superfluous timer interrupts from the nic. */ -#define FORCEDETH_VERSION "0.62" +#define FORCEDETH_VERSION "0.61" #define DRV_NAME "forcedeth" #include @@ -2096,15 +2096,14 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); } - spin_lock_irqsave(&np->lock, flags); empty_slots = nv_get_empty_tx_slots(np); if (unlikely(empty_slots <= entries)) { + spin_lock_irqsave(&np->lock, flags); netif_stop_queue(dev); np->tx_stop = 1; spin_unlock_irqrestore(&np->lock, flags); return NETDEV_TX_BUSY; } - spin_unlock_irqrestore(&np->lock, flags); start_tx = put_tx = np->put_tx.orig; @@ -2215,15 +2214,14 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); } - spin_lock_irqsave(&np->lock, flags); empty_slots = nv_get_empty_tx_slots(np); if (unlikely(empty_slots <= entries)) { + spin_lock_irqsave(&np->lock, flags); netif_stop_queue(dev); np->tx_stop = 1; spin_unlock_irqrestore(&np->lock, flags); return NETDEV_TX_BUSY; } - spin_unlock_irqrestore(&np->lock, flags); start_tx = put_tx = np->put_tx.ex; start_tx_ctx = np->put_tx_ctx; @@ -3405,10 +3403,10 @@ static irqreturn_t nv_nic_irq(int foo, void *data) #ifdef CONFIG_FORCEDETH_NAPI if (events & NVREG_IRQ_RX_ALL) { - spin_lock(&np->lock); netif_rx_schedule(&np->napi); /* Disable furthur receive irq's */ + spin_lock(&np->lock); np->irqmask &= ~NVREG_IRQ_RX_ALL; if (np->msi_flags & NV_MSI_X_ENABLED) @@ -3522,10 +3520,10 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data) #ifdef CONFIG_FORCEDETH_NAPI if (events & NVREG_IRQ_RX_ALL) { - spin_lock(&np->lock); netif_rx_schedule(&np->napi); /* Disable furthur receive irq's */ + spin_lock(&np->lock); np->irqmask &= ~NVREG_IRQ_RX_ALL; if (np->msi_flags & NV_MSI_X_ENABLED) @@ -6169,19 +6167,19 @@ static struct pci_device_id pci_tbl[] = { }, { /* MCP79 Ethernet Controller */ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), - .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, + .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, }, { /* MCP79 Ethernet Controller */ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), - .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, + .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, }, { /* MCP79 Ethernet Controller */ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), - .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, + .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, }, { /* MCP79 Ethernet Controller */ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), - .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, + .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, }, {0,}, }; diff --git a/trunk/drivers/net/gianfar.c b/trunk/drivers/net/gianfar.c index efcbeb6c8673..1b8deca8b9f8 100644 --- a/trunk/drivers/net/gianfar.c +++ b/trunk/drivers/net/gianfar.c @@ -296,20 +296,6 @@ static int gfar_of_init(struct net_device *dev) return err; } -/* Ioctl MII Interface */ -static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct gfar_private *priv = netdev_priv(dev); - - if (!netif_running(dev)) - return -EINVAL; - - if (!priv->phydev) - return -ENODEV; - - return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); -} - /* Set up the ethernet device structure, private data, * and anything else we need before we start */ static int gfar_probe(struct of_device *ofdev, @@ -380,7 +366,6 @@ static int gfar_probe(struct of_device *ofdev, dev->set_multicast_list = gfar_set_multi; dev->ethtool_ops = &gfar_ethtool_ops; - dev->do_ioctl = gfar_ioctl; if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { priv->rx_csum_enable = 1; diff --git a/trunk/drivers/net/hamachi.c b/trunk/drivers/net/hamachi.c index 7e8b3c59a7d6..32200227c923 100644 --- a/trunk/drivers/net/hamachi.c +++ b/trunk/drivers/net/hamachi.c @@ -576,7 +576,6 @@ static const struct net_device_ops hamachi_netdev_ops = { .ndo_set_multicast_list = set_rx_mode, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_tx_timeout = hamachi_tx_timeout, .ndo_do_ioctl = netdev_ioctl, }; diff --git a/trunk/drivers/net/hamradio/6pack.c b/trunk/drivers/net/hamradio/6pack.c index 2d4089894ec7..50f1e172ee8f 100644 --- a/trunk/drivers/net/hamradio/6pack.c +++ b/trunk/drivers/net/hamradio/6pack.c @@ -717,12 +717,11 @@ static int sixpack_ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg) { struct sixpack *sp = sp_get(tty); - struct net_device *dev; + struct net_device *dev = sp->dev; unsigned int tmp, err; if (!sp) return -ENXIO; - dev = sp->dev; switch(cmd) { case SIOCGIFNAME: diff --git a/trunk/drivers/net/hp-plus.c b/trunk/drivers/net/hp-plus.c index 5e070f446635..b507dbc16e62 100644 --- a/trunk/drivers/net/hp-plus.c +++ b/trunk/drivers/net/hp-plus.c @@ -166,7 +166,6 @@ static const struct net_device_ops hpp_netdev_ops = { .ndo_get_stats = eip_get_stats, .ndo_set_multicast_list = eip_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = eip_poll, diff --git a/trunk/drivers/net/hydra.c b/trunk/drivers/net/hydra.c index 8ac0930c183c..9cb38a8d4387 100644 --- a/trunk/drivers/net/hydra.c +++ b/trunk/drivers/net/hydra.c @@ -103,7 +103,6 @@ static const struct net_device_ops hydra_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/irda/au1k_ir.c b/trunk/drivers/net/irda/au1k_ir.c index 941164076a2b..75a1d0a86dee 100644 --- a/trunk/drivers/net/irda/au1k_ir.c +++ b/trunk/drivers/net/irda/au1k_ir.c @@ -594,7 +594,7 @@ static int au1k_irda_rx(struct net_device *dev) update_rx_stats(dev, flags, count); skb=alloc_skb(count+1,GFP_ATOMIC); if (skb == NULL) { - aup->netdev->stats.rx_dropped++; + aup->stats.rx_dropped++; continue; } skb_reserve(skb, 1); diff --git a/trunk/drivers/net/irda/donauboe.c b/trunk/drivers/net/irda/donauboe.c index 6f3e7f71658d..687c2d53d4d2 100644 --- a/trunk/drivers/net/irda/donauboe.c +++ b/trunk/drivers/net/irda/donauboe.c @@ -1194,13 +1194,13 @@ toshoboe_interrupt (int irq, void *dev_id) txp = txpc; txpc++; txpc %= TX_SLOTS; - self->netdev->stats.tx_packets++; + self->stats.tx_packets++; if (self->ring->tx[txpc].control & OBOE_CTL_TX_HW_OWNS) self->ring->tx[txp].control &= ~OBOE_CTL_TX_RTCENTX; } - self->netdev->stats.tx_packets--; + self->stats.tx_packets--; #else - self->netdev->stats.tx_packets++; + self->stats.tx_packets++; #endif toshoboe_start_DMA(self, OBOE_CONFIG0H_ENTX); } @@ -1280,7 +1280,7 @@ dumpbufs(self->rx_bufs[self->rxs],len,'<'); skb_put (skb, len); skb_copy_to_linear_data(skb, self->rx_bufs[self->rxs], len); - self->netdev->stats.rx_packets++; + self->stats.rx_packets++; skb->dev = self->netdev; skb_reset_mac_header(skb); skb->protocol = htons (ETH_P_IRDA); diff --git a/trunk/drivers/net/mac8390.c b/trunk/drivers/net/mac8390.c index 8e884869a05b..57716e22660c 100644 --- a/trunk/drivers/net/mac8390.c +++ b/trunk/drivers/net/mac8390.c @@ -486,7 +486,6 @@ static const struct net_device_ops mac8390_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/mlx4/en_netdev.c b/trunk/drivers/net/mlx4/en_netdev.c index 9f6644a44030..15bb38d99304 100644 --- a/trunk/drivers/net/mlx4/en_netdev.c +++ b/trunk/drivers/net/mlx4/en_netdev.c @@ -952,7 +952,6 @@ static const struct net_device_ops mlx4_netdev_ops = { .ndo_get_stats = mlx4_en_get_stats, .ndo_set_multicast_list = mlx4_en_set_multicast, .ndo_set_mac_address = mlx4_en_set_mac, - .ndo_validate_addr = eth_validate_addr, .ndo_change_mtu = mlx4_en_change_mtu, .ndo_tx_timeout = mlx4_en_tx_timeout, .ndo_vlan_rx_register = mlx4_en_vlan_rx_register, diff --git a/trunk/drivers/net/mlx4/main.c b/trunk/drivers/net/mlx4/main.c index 6ef2490d5c3e..710c79e7a2db 100644 --- a/trunk/drivers/net/mlx4/main.c +++ b/trunk/drivers/net/mlx4/main.c @@ -912,8 +912,8 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev) int i; if (msi_x) { - nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, - num_possible_cpus() + 1); + nreq = min(dev->caps.num_eqs - dev->caps.reserved_eqs, + num_possible_cpus() + 1); entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); if (!entries) goto no_msi; diff --git a/trunk/drivers/net/ne-h8300.c b/trunk/drivers/net/ne-h8300.c index 7bd6662d5b04..b57239171046 100644 --- a/trunk/drivers/net/ne-h8300.c +++ b/trunk/drivers/net/ne-h8300.c @@ -202,7 +202,6 @@ static const struct net_device_ops ne_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/ne2k-pci.c b/trunk/drivers/net/ne2k-pci.c index f090d3b9ec94..62f20ba211cb 100644 --- a/trunk/drivers/net/ne2k-pci.c +++ b/trunk/drivers/net/ne2k-pci.c @@ -208,7 +208,6 @@ static const struct net_device_ops ne2k_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/ns83820.c b/trunk/drivers/net/ns83820.c index e80294d8cc19..42021aca1ddd 100644 --- a/trunk/drivers/net/ns83820.c +++ b/trunk/drivers/net/ns83820.c @@ -1956,7 +1956,6 @@ static const struct net_device_ops netdev_ops = { .ndo_change_mtu = ns83820_change_mtu, .ndo_set_multicast_list = ns83820_set_multicast, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_tx_timeout = ns83820_tx_timeout, #ifdef NS83820_VLAN_ACCEL_SUPPORT .ndo_vlan_rx_register = ns83820_vlan_rx_register, diff --git a/trunk/drivers/net/qlge/qlge.h b/trunk/drivers/net/qlge/qlge.h index c1dadadfab18..459663a4023d 100644 --- a/trunk/drivers/net/qlge/qlge.h +++ b/trunk/drivers/net/qlge/qlge.h @@ -28,11 +28,11 @@ } while (0) #define QLGE_VENDOR_ID 0x1077 -#define QLGE_DEVICE_ID 0x8012 +#define QLGE_DEVICE_ID1 0x8012 +#define QLGE_DEVICE_ID 0x8000 -#define MAX_CPUS 8 -#define MAX_TX_RINGS MAX_CPUS -#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1) +#define MAX_RX_RINGS 128 +#define MAX_TX_RINGS 128 #define NUM_TX_RING_ENTRIES 256 #define NUM_RX_RING_ENTRIES 256 @@ -45,7 +45,6 @@ #define MAX_SPLIT_SIZE 1023 #define QLGE_SB_PAD 32 -#define MAX_CQ 128 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */ #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) @@ -962,7 +961,8 @@ struct ib_mac_iocb_rsp { #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */ #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */ __le32 data_len; /* */ - __le64 data_addr; /* */ + __le32 data_addr_lo; /* */ + __le32 data_addr_hi; /* */ __le32 rss; /* */ __le16 vlan_id; /* 12 bits */ #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */ @@ -976,7 +976,8 @@ struct ib_mac_iocb_rsp { #define IB_MAC_IOCB_RSP_HS 0x40 #define IB_MAC_IOCB_RSP_HL 0x80 __le32 hdr_len; /* */ - __le64 hdr_addr; /* */ + __le32 hdr_addr_lo; /* */ + __le32 hdr_addr_hi; /* */ } __attribute((packed)); struct ib_ae_iocb_rsp { @@ -1041,8 +1042,10 @@ struct wqicb { __le16 cq_id_rss; #define Q_CQ_ID_RSS_RV 0x8000 __le16 rid; - __le64 addr; - __le64 cnsmr_idx_addr; + __le32 addr_lo; + __le32 addr_hi; + __le32 cnsmr_idx_addr_lo; + __le32 cnsmr_idx_addr_hi; } __attribute((packed)); /* @@ -1067,14 +1070,18 @@ struct cqicb { #define LEN_CPP_64 0x0002 #define LEN_CPP_128 0x0003 __le16 rid; - __le64 addr; - __le64 prod_idx_addr; + __le32 addr_lo; + __le32 addr_hi; + __le32 prod_idx_addr_lo; + __le32 prod_idx_addr_hi; __le16 pkt_delay; __le16 irq_delay; - __le64 lbq_addr; + __le32 lbq_addr_lo; + __le32 lbq_addr_hi; __le16 lbq_buf_size; __le16 lbq_len; /* entry count */ - __le64 sbq_addr; + __le32 sbq_addr_lo; + __le32 sbq_addr_hi; __le16 sbq_buf_size; __le16 sbq_len; /* entry count */ } __attribute((packed)); @@ -1138,7 +1145,7 @@ struct tx_ring { struct wqicb wqicb; /* structure used to inform chip of new queue */ void *wq_base; /* pci_alloc:virtual addr for tx */ dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */ - __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ + u32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */ dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */ u32 wq_size; /* size in bytes of queue area */ u32 wq_len; /* number of entries in queue */ @@ -1174,7 +1181,7 @@ struct rx_ring { u32 cq_size; u32 cq_len; u16 cq_id; - __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ + volatile __le32 *prod_idx_sh_reg; /* Shadowed producer register. */ dma_addr_t prod_idx_sh_reg_dma; void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */ u32 cnsmr_idx; /* current sw idx */ @@ -1395,11 +1402,9 @@ struct ql_adapter { int rx_ring_count; int ring_mem_size; void *ring_mem; - - struct rx_ring rx_ring[MAX_RX_RINGS]; - struct tx_ring tx_ring[MAX_TX_RINGS]; - + struct rx_ring *rx_ring; int rx_csum; + struct tx_ring *tx_ring; u32 default_rx_queue; u16 rx_coalesce_usecs; /* cqicb->int_delay */ @@ -1454,24 +1459,6 @@ static inline void ql_write_db_reg(u32 val, void __iomem *addr) mmiowb(); } -/* - * Shadow Registers: - * Outbound queues have a consumer index that is maintained by the chip. - * Inbound queues have a producer index that is maintained by the chip. - * For lower overhead, these registers are "shadowed" to host memory - * which allows the device driver to track the queue progress without - * PCI reads. When an entry is placed on an inbound queue, the chip will - * update the relevant index register and then copy the value to the - * shadow register in host memory. - */ -static inline u32 ql_read_sh_reg(__le32 *addr) -{ - u32 reg; - reg = le32_to_cpu(*addr); - rmb(); - return reg; -} - extern char qlge_driver_name[]; extern const char qlge_driver_version[]; extern const struct ethtool_ops qlge_ethtool_ops; diff --git a/trunk/drivers/net/qlge/qlge_dbg.c b/trunk/drivers/net/qlge/qlge_dbg.c index 379b895ed6e6..3f5e02d2e4a9 100644 --- a/trunk/drivers/net/qlge/qlge_dbg.c +++ b/trunk/drivers/net/qlge/qlge_dbg.c @@ -435,10 +435,14 @@ void ql_dump_wqicb(struct wqicb *wqicb) printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n", le16_to_cpu(wqicb->cq_id_rss)); printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid)); - printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(wqicb->addr)); - printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr)); + printk(KERN_ERR PFX "wqicb->wq_addr_lo = 0x%.08x.\n", + le32_to_cpu(wqicb->addr_lo)); + printk(KERN_ERR PFX "wqicb->wq_addr_hi = 0x%.08x.\n", + le32_to_cpu(wqicb->addr_hi)); + printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr_lo = 0x%.08x.\n", + le32_to_cpu(wqicb->cnsmr_idx_addr_lo)); + printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr_hi = 0x%.08x.\n", + le32_to_cpu(wqicb->cnsmr_idx_addr_hi)); } void ql_dump_tx_ring(struct tx_ring *tx_ring) @@ -451,11 +455,10 @@ void ql_dump_tx_ring(struct tx_ring *tx_ring) printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base); printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n", (unsigned long long) tx_ring->wq_base_dma); - printk(KERN_ERR PFX - "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n", - tx_ring->cnsmr_idx_sh_reg, - tx_ring->cnsmr_idx_sh_reg - ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0); + printk(KERN_ERR PFX "tx_ring->cnsmr_idx_sh_reg = %p.\n", + tx_ring->cnsmr_idx_sh_reg); + printk(KERN_ERR PFX "tx_ring->cnsmr_idx_sh_reg_dma = 0x%llx.\n", + (unsigned long long) tx_ring->cnsmr_idx_sh_reg_dma); printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size); printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len); printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n", @@ -507,22 +510,30 @@ void ql_dump_cqicb(struct cqicb *cqicb) printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect); printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags); printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len)); - printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(cqicb->addr)); - printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr)); + printk(KERN_ERR PFX "cqicb->addr_lo = %x.\n", + le32_to_cpu(cqicb->addr_lo)); + printk(KERN_ERR PFX "cqicb->addr_hi = %x.\n", + le32_to_cpu(cqicb->addr_hi)); + printk(KERN_ERR PFX "cqicb->prod_idx_addr_lo = %x.\n", + le32_to_cpu(cqicb->prod_idx_addr_lo)); + printk(KERN_ERR PFX "cqicb->prod_idx_addr_hi = %x.\n", + le32_to_cpu(cqicb->prod_idx_addr_hi)); printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n", le16_to_cpu(cqicb->pkt_delay)); printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n", le16_to_cpu(cqicb->irq_delay)); - printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(cqicb->lbq_addr)); + printk(KERN_ERR PFX "cqicb->lbq_addr_lo = %x.\n", + le32_to_cpu(cqicb->lbq_addr_lo)); + printk(KERN_ERR PFX "cqicb->lbq_addr_hi = %x.\n", + le32_to_cpu(cqicb->lbq_addr_hi)); printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n", le16_to_cpu(cqicb->lbq_buf_size)); printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n", le16_to_cpu(cqicb->lbq_len)); - printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(cqicb->sbq_addr)); + printk(KERN_ERR PFX "cqicb->sbq_addr_lo = %x.\n", + le32_to_cpu(cqicb->sbq_addr_lo)); + printk(KERN_ERR PFX "cqicb->sbq_addr_hi = %x.\n", + le32_to_cpu(cqicb->sbq_addr_hi)); printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n", le16_to_cpu(cqicb->sbq_buf_size)); printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n", @@ -547,10 +558,9 @@ void ql_dump_rx_ring(struct rx_ring *rx_ring) printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size); printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len); printk(KERN_ERR PFX - "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n", + "rx_ring->prod_idx_sh_reg, addr = %p, value = %d.\n", rx_ring->prod_idx_sh_reg, - rx_ring->prod_idx_sh_reg - ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0); + rx_ring->prod_idx_sh_reg ? *(rx_ring->prod_idx_sh_reg) : 0); printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n", (unsigned long long) rx_ring->prod_idx_sh_reg_dma); printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n", @@ -799,8 +809,10 @@ void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp) printk(KERN_ERR PFX "data_len = %d\n", le32_to_cpu(ib_mac_rsp->data_len)); - printk(KERN_ERR PFX "data_addr = 0x%llx\n", - (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr)); + printk(KERN_ERR PFX "data_addr_hi = 0x%x\n", + le32_to_cpu(ib_mac_rsp->data_addr_hi)); + printk(KERN_ERR PFX "data_addr_lo = 0x%x\n", + le32_to_cpu(ib_mac_rsp->data_addr_lo)); if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) printk(KERN_ERR PFX "rss = %x\n", le32_to_cpu(ib_mac_rsp->rss)); @@ -816,8 +828,10 @@ void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp) if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { printk(KERN_ERR PFX "hdr length = %d.\n", le32_to_cpu(ib_mac_rsp->hdr_len)); - printk(KERN_ERR PFX "hdr addr = 0x%llx.\n", - (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr)); + printk(KERN_ERR PFX "hdr addr_hi = 0x%x.\n", + le32_to_cpu(ib_mac_rsp->hdr_addr_hi)); + printk(KERN_ERR PFX "hdr addr_lo = 0x%x.\n", + le32_to_cpu(ib_mac_rsp->hdr_addr_lo)); } } #endif diff --git a/trunk/drivers/net/qlge/qlge_main.c b/trunk/drivers/net/qlge/qlge_main.c index 45421c8b6010..f4c016012f18 100644 --- a/trunk/drivers/net/qlge/qlge_main.c +++ b/trunk/drivers/net/qlge/qlge_main.c @@ -76,6 +76,7 @@ MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy."); static struct pci_device_id qlge_pci_tbl[] __devinitdata = { {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)}, + {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)}, /* required last entry */ {0,} }; @@ -126,12 +127,12 @@ static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask) int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask) { - unsigned int wait_count = 30; + unsigned int seconds = 3; do { if (!ql_sem_trylock(qdev, sem_mask)) return 0; - udelay(100); - } while (--wait_count); + ssleep(1); + } while (--seconds); return -ETIMEDOUT; } @@ -1544,7 +1545,7 @@ static void ql_process_chip_ae_intr(struct ql_adapter *qdev, static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) { struct ql_adapter *qdev = rx_ring->qdev; - u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); struct ob_mac_iocb_rsp *net_rsp = NULL; int count = 0; @@ -1570,7 +1571,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) } count++; ql_update_cq(rx_ring); - prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); } ql_write_cq_idx(rx_ring); if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) { @@ -1590,7 +1591,7 @@ static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) { struct ql_adapter *qdev = rx_ring->qdev; - u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + u32 prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); struct ql_net_rsp_iocb *net_rsp; int count = 0; @@ -1623,7 +1624,7 @@ static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) } count++; ql_update_cq(rx_ring); - prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); + prod = le32_to_cpu(*rx_ring->prod_idx_sh_reg); if (count == budget) break; } @@ -1786,7 +1787,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) * Check the default queue and wake handler if active. */ rx_ring = &qdev->rx_ring[0]; - if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) { + if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) { QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n"); ql_disable_completion_interrupt(qdev, intr_context->intr); queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue, @@ -1800,7 +1801,7 @@ static irqreturn_t qlge_isr(int irq, void *dev_id) */ for (i = 1; i < qdev->rx_ring_count; i++) { rx_ring = &qdev->rx_ring[i]; - if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != + if (le32_to_cpu(*rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) { QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[%d].\n", i); @@ -2355,6 +2356,28 @@ static void ql_tx_ring_clean(struct ql_adapter *qdev) } } +static void ql_free_ring_cb(struct ql_adapter *qdev) +{ + kfree(qdev->ring_mem); +} + +static int ql_alloc_ring_cb(struct ql_adapter *qdev) +{ + /* Allocate space for tx/rx ring control blocks. */ + qdev->ring_mem_size = + (qdev->tx_ring_count * sizeof(struct tx_ring)) + + (qdev->rx_ring_count * sizeof(struct rx_ring)); + qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL); + if (qdev->ring_mem == NULL) { + return -ENOMEM; + } else { + qdev->rx_ring = qdev->ring_mem; + qdev->tx_ring = qdev->ring_mem + + (qdev->rx_ring_count * sizeof(struct rx_ring)); + } + return 0; +} + static void ql_free_mem_resources(struct ql_adapter *qdev) { int i; @@ -2444,9 +2467,12 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len; cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT); - cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma); + cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma); + cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32); - cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma); + cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma); + cqicb->prod_idx_addr_hi = + cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32); /* * Set up the control block load flags. @@ -2457,8 +2483,10 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) if (rx_ring->lbq_len) { cqicb->flags |= FLAGS_LL; /* Load lbq values */ *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma; - cqicb->lbq_addr = - cpu_to_le64(rx_ring->lbq_base_indirect_dma); + cqicb->lbq_addr_lo = + cpu_to_le32(rx_ring->lbq_base_indirect_dma); + cqicb->lbq_addr_hi = + cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32); bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 : (u16) rx_ring->lbq_buf_size; cqicb->lbq_buf_size = cpu_to_le16(bq_len); @@ -2473,8 +2501,10 @@ static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) if (rx_ring->sbq_len) { cqicb->flags |= FLAGS_LS; /* Load sbq values */ *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma; - cqicb->sbq_addr = - cpu_to_le64(rx_ring->sbq_base_indirect_dma); + cqicb->sbq_addr_lo = + cpu_to_le32(rx_ring->sbq_base_indirect_dma); + cqicb->sbq_addr_hi = + cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32); cqicb->sbq_buf_size = cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8); bq_len = (rx_ring->sbq_len == 65536) ? 0 : @@ -2581,9 +2611,12 @@ static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO); wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id); wqicb->rid = 0; - wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma); + wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma); + wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32); - wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma); + wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma); + wqicb->cnsmr_idx_addr_hi = + cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32); ql_init_tx_ring(qdev, tx_ring); @@ -2713,14 +2746,14 @@ static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) * Outbound queue is for outbound completions only. */ intr_context->handler = qlge_msix_tx_isr; - sprintf(intr_context->name, "%s-tx-%d", + sprintf(intr_context->name, "%s-txq-%d", qdev->ndev->name, i); } else { /* * Inbound queues handle unicast frames only. */ intr_context->handler = qlge_msix_rx_isr; - sprintf(intr_context->name, "%s-rx-%d", + sprintf(intr_context->name, "%s-rxq-%d", qdev->ndev->name, i); } } @@ -3214,6 +3247,7 @@ static int qlge_close(struct net_device *ndev) msleep(1); ql_adapter_down(qdev); ql_release_adapter_resources(qdev); + ql_free_ring_cb(qdev); return 0; } @@ -3239,8 +3273,8 @@ static int ql_configure_rings(struct ql_adapter *qdev) * This limitation can be removed when requested. */ - if (cpu_cnt > MAX_CPUS) - cpu_cnt = MAX_CPUS; + if (cpu_cnt > 8) + cpu_cnt = 8; /* * rx_ring[0] is always the default queue. @@ -3260,6 +3294,9 @@ static int ql_configure_rings(struct ql_adapter *qdev) */ qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1; + if (ql_alloc_ring_cb(qdev)) + return -ENOMEM; + for (i = 0; i < qdev->tx_ring_count; i++) { tx_ring = &qdev->tx_ring[i]; memset((void *)tx_ring, 0, sizeof(tx_ring)); @@ -3356,6 +3393,7 @@ static int qlge_open(struct net_device *ndev) error_up: ql_release_adapter_resources(qdev); + ql_free_ring_cb(qdev); return err; } diff --git a/trunk/drivers/net/r6040.c b/trunk/drivers/net/r6040.c index 72fd9e97c190..cf3a082bc89d 100644 --- a/trunk/drivers/net/r6040.c +++ b/trunk/drivers/net/r6040.c @@ -49,8 +49,8 @@ #include #define DRV_NAME "r6040" -#define DRV_VERSION "0.21" -#define DRV_RELDATE "09Jan2009" +#define DRV_VERSION "0.20" +#define DRV_RELDATE "07Jan2009" /* PHY CHIP Address */ #define PHY1_ADDR 1 /* For MAC1 */ @@ -457,12 +457,22 @@ static void r6040_down(struct net_device *dev) iowrite16(adrp[0], ioaddr + MID_0L); iowrite16(adrp[1], ioaddr + MID_0M); iowrite16(adrp[2], ioaddr + MID_0H); + free_irq(dev->irq, dev); + + /* Free RX buffer */ + r6040_free_rxbufs(dev); + + /* Free TX buffer */ + r6040_free_txbufs(dev); + + /* Free Descriptor memory */ + pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); + pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); } static int r6040_close(struct net_device *dev) { struct r6040_private *lp = netdev_priv(dev); - struct pci_dev *pdev = lp->pdev; /* deleted timer */ del_timer_sync(&lp->timer); @@ -471,28 +481,8 @@ static int r6040_close(struct net_device *dev) napi_disable(&lp->napi); netif_stop_queue(dev); r6040_down(dev); - - free_irq(dev->irq, dev); - - /* Free RX buffer */ - r6040_free_rxbufs(dev); - - /* Free TX buffer */ - r6040_free_txbufs(dev); - spin_unlock_irq(&lp->lock); - /* Free Descriptor memory */ - if (lp->rx_ring) { - pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); - lp->rx_ring = 0; - } - - if (lp->tx_ring) { - pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); - lp->tx_ring = 0; - } - return 0; } @@ -1059,7 +1049,6 @@ static const struct net_device_ops r6040_netdev_ops = { .ndo_set_multicast_list = r6040_multicast_list, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_do_ioctl = r6040_ioctl, .ndo_tx_timeout = r6040_tx_timeout, #ifdef CONFIG_NET_POLL_CONTROLLER @@ -1154,10 +1143,8 @@ static int __devinit r6040_init_one(struct pci_dev *pdev, /* Some bootloader/BIOSes do not initialize * MAC address, warn about that */ - if (!(adrp[0] || adrp[1] || adrp[2])) { - printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n"); - random_ether_addr(dev->dev_addr); - } + if (!(adrp[0] || adrp[1] || adrp[2])) + printk(KERN_WARNING DRV_NAME ": MAC address not initialized\n"); /* Link new device into r6040_root_dev */ lp->pdev = pdev; diff --git a/trunk/drivers/net/sc92031.c b/trunk/drivers/net/sc92031.c index 8b75bef4a841..42fd31276602 100644 --- a/trunk/drivers/net/sc92031.c +++ b/trunk/drivers/net/sc92031.c @@ -1408,7 +1408,6 @@ static const struct net_device_ops sc92031_netdev_ops = { .ndo_set_multicast_list = sc92031_set_multicast_list, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_tx_timeout = sc92031_tx_timeout, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = sc92031_poll_controller, diff --git a/trunk/drivers/net/sfc/tenxpress.c b/trunk/drivers/net/sfc/tenxpress.c index 9ecb77da9545..b9768760fae7 100644 --- a/trunk/drivers/net/sfc/tenxpress.c +++ b/trunk/drivers/net/sfc/tenxpress.c @@ -636,11 +636,10 @@ static void tenxpress_phy_fini(struct efx_nic *efx) { int reg; - if (efx->phy_type == PHY_TYPE_SFT9001B) + if (efx->phy_type == PHY_TYPE_SFT9001B) { device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_short_reach); - - if (efx->phy_type == PHY_TYPE_SFX7101) { + } else { /* Power down the LNPGA */ reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, diff --git a/trunk/drivers/net/sis900.c b/trunk/drivers/net/sis900.c index 6cbefcae9ac2..4acd41a093ad 100644 --- a/trunk/drivers/net/sis900.c +++ b/trunk/drivers/net/sis900.c @@ -389,7 +389,6 @@ static const struct net_device_ops sis900_netdev_ops = { .ndo_set_multicast_list = set_rx_mode, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_do_ioctl = mii_ioctl, .ndo_tx_timeout = sis900_tx_timeout, #ifdef CONFIG_NET_POLL_CONTROLLER diff --git a/trunk/drivers/net/smc-mca.c b/trunk/drivers/net/smc-mca.c index 8d36d40649ef..404b80e5ba11 100644 --- a/trunk/drivers/net/smc-mca.c +++ b/trunk/drivers/net/smc-mca.c @@ -192,7 +192,6 @@ static const struct net_device_ops ultramca_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/smc-ultra.c b/trunk/drivers/net/smc-ultra.c index 2033fee3143a..b3866089a206 100644 --- a/trunk/drivers/net/smc-ultra.c +++ b/trunk/drivers/net/smc-ultra.c @@ -196,7 +196,6 @@ static const struct net_device_ops ultra_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/smsc911x.c b/trunk/drivers/net/smsc911x.c index f513bdf1c887..dc3f1108884d 100644 --- a/trunk/drivers/net/smsc911x.c +++ b/trunk/drivers/net/smsc911x.c @@ -144,7 +144,6 @@ static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) } BUG(); - return 0; } static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, @@ -1741,7 +1740,6 @@ static const struct net_device_ops smsc911x_netdev_ops = { .ndo_set_multicast_list = smsc911x_set_multicast_list, .ndo_do_ioctl = smsc911x_do_ioctl, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = smsc911x_poll_controller, #endif @@ -1969,7 +1967,7 @@ static int __devinit smsc911x_drv_probe(struct platform_device *pdev) smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED, - dev->name, dev); + SMSC_CHIPNAME, dev); if (retval) { SMSC_WARNING(PROBE, "Unable to claim requested irq: %d", dev->irq); diff --git a/trunk/drivers/net/smsc9420.c b/trunk/drivers/net/smsc9420.c index c14a4c6452c7..27e017d96966 100644 --- a/trunk/drivers/net/smsc9420.c +++ b/trunk/drivers/net/smsc9420.c @@ -1551,7 +1551,6 @@ static const struct net_device_ops smsc9420_netdev_ops = { .ndo_set_multicast_list = smsc9420_set_multicast_list, .ndo_do_ioctl = smsc9420_do_ioctl, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = smsc9420_poll_controller, #endif /* CONFIG_NET_POLL_CONTROLLER */ diff --git a/trunk/drivers/net/ucc_geth.c b/trunk/drivers/net/ucc_geth.c index 11441225bf41..7d5a1303e30d 100644 --- a/trunk/drivers/net/ucc_geth.c +++ b/trunk/drivers/net/ucc_geth.c @@ -442,30 +442,40 @@ static void magic_packet_detection_enable(struct ucc_geth_private *ugeth) { struct ucc_fast_private *uccf; struct ucc_geth __iomem *ug_regs; + u32 maccfg2, uccm; uccf = ugeth->uccf; ug_regs = ugeth->ug_regs; /* Enable interrupts for magic packet detection */ - setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); + uccm = in_be32(uccf->p_uccm); + uccm |= UCCE_MPD; + out_be32(uccf->p_uccm, uccm); /* Enable magic packet detection */ - setbits32(&ug_regs->maccfg2, MACCFG2_MPE); + maccfg2 = in_be32(&ug_regs->maccfg2); + maccfg2 |= MACCFG2_MPE; + out_be32(&ug_regs->maccfg2, maccfg2); } static void magic_packet_detection_disable(struct ucc_geth_private *ugeth) { struct ucc_fast_private *uccf; struct ucc_geth __iomem *ug_regs; + u32 maccfg2, uccm; uccf = ugeth->uccf; ug_regs = ugeth->ug_regs; /* Disable interrupts for magic packet detection */ - clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD); + uccm = in_be32(uccf->p_uccm); + uccm &= ~UCCE_MPD; + out_be32(uccf->p_uccm, uccm); /* Disable magic packet detection */ - clrbits32(&ug_regs->maccfg2, MACCFG2_MPE); + maccfg2 = in_be32(&ug_regs->maccfg2); + maccfg2 &= ~MACCFG2_MPE; + out_be32(&ug_regs->maccfg2, maccfg2); } #endif /* MAGIC_PACKET */ @@ -575,8 +585,7 @@ static void get_statistics(struct ucc_geth_private *ugeth, /* Hardware only if user handed pointer and driver actually gathers hardware statistics */ - if (hardware_statistics && - (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { + if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) { hardware_statistics->tx64 = in_be32(&ug_regs->tx64); hardware_statistics->tx127 = in_be32(&ug_regs->tx127); hardware_statistics->tx255 = in_be32(&ug_regs->tx255); @@ -1172,7 +1181,9 @@ int init_flow_control_params(u32 automatic_flow_control_mode, out_be32(uempr_register, value); /* Set UPSMR register */ - setbits32(upsmr_register, automatic_flow_control_mode); + value = in_be32(upsmr_register); + value |= automatic_flow_control_mode; + out_be32(upsmr_register, value); value = in_be32(maccfg1_register); if (rx_flow_control_enable) @@ -1189,11 +1200,14 @@ static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, u32 __iomem *upsmr_register, u16 __iomem *uescr_register) { + u32 upsmr_value = 0; u16 uescr_value = 0; - /* Enable hardware statistics gathering if requested */ - if (enable_hardware_statistics) - setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); + if (enable_hardware_statistics) { + upsmr_value = in_be32(upsmr_register); + upsmr_value |= UPSMR_HSE; + out_be32(upsmr_register, upsmr_value); + } /* Clear hardware statistics counters */ uescr_value = in_be16(uescr_register); @@ -1219,17 +1233,23 @@ static int init_firmware_statistics_gathering_mode(int { /* Note: this function does not check if */ /* the parameters it receives are NULL */ + u16 temoder_value; + u32 remoder_value; if (enable_tx_firmware_statistics) { out_be32(tx_rmon_base_ptr, tx_firmware_statistics_structure_address); - setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); + temoder_value = in_be16(temoder_register); + temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE; + out_be16(temoder_register, temoder_value); } if (enable_rx_firmware_statistics) { out_be32(rx_rmon_base_ptr, rx_firmware_statistics_structure_address); - setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); + remoder_value = in_be32(remoder_register); + remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE; + out_be32(remoder_register, remoder_value); } return 0; @@ -1296,12 +1316,15 @@ static int init_check_frame_length_mode(int length_check, static int init_preamble_length(u8 preamble_length, u32 __iomem *maccfg2_register) { + u32 value = 0; + if ((preamble_length < 3) || (preamble_length > 7)) return -EINVAL; - clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, - preamble_length << MACCFG2_PREL_SHIFT); - + value = in_be32(maccfg2_register); + value &= ~MACCFG2_PREL_MASK; + value |= (preamble_length << MACCFG2_PREL_SHIFT); + out_be32(maccfg2_register, value); return 0; } @@ -1314,19 +1337,19 @@ static int init_rx_parameters(int reject_broadcast, value = in_be32(upsmr_register); if (reject_broadcast) - value |= UCC_GETH_UPSMR_BRO; + value |= UPSMR_BRO; else - value &= ~UCC_GETH_UPSMR_BRO; + value &= ~UPSMR_BRO; if (receive_short_frames) - value |= UCC_GETH_UPSMR_RSH; + value |= UPSMR_RSH; else - value &= ~UCC_GETH_UPSMR_RSH; + value &= ~UPSMR_RSH; if (promiscuous) - value |= UCC_GETH_UPSMR_PRO; + value |= UPSMR_PRO; else - value &= ~UCC_GETH_UPSMR_PRO; + value &= ~UPSMR_PRO; out_be32(upsmr_register, value); @@ -1387,27 +1410,26 @@ static int adjust_enet_interface(struct ucc_geth_private *ugeth) /* Set UPSMR */ upsmr = in_be32(&uf_regs->upsmr); - upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | - UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); + upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM); if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { - upsmr |= UCC_GETH_UPSMR_RPM; + upsmr |= UPSMR_RPM; switch (ugeth->max_speed) { case SPEED_10: - upsmr |= UCC_GETH_UPSMR_R10M; + upsmr |= UPSMR_R10M; /* FALLTHROUGH */ case SPEED_100: if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) - upsmr |= UCC_GETH_UPSMR_RMM; + upsmr |= UPSMR_RMM; } } if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { - upsmr |= UCC_GETH_UPSMR_TBIM; + upsmr |= UPSMR_TBIM; } out_be32(&uf_regs->upsmr, upsmr); @@ -1495,9 +1517,9 @@ static void adjust_link(struct net_device *dev) (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { if (phydev->speed == SPEED_10) - upsmr |= UCC_GETH_UPSMR_R10M; + upsmr |= UPSMR_R10M; else - upsmr &= ~UCC_GETH_UPSMR_R10M; + upsmr &= ~(UPSMR_R10M); } break; default: @@ -1580,8 +1602,10 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) uccf = ugeth->uccf; /* Mask GRACEFUL STOP TX interrupt bit and clear it */ - clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); - out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ + temp = in_be32(uccf->p_uccm); + temp &= ~UCCE_GRA; + out_be32(uccf->p_uccm, temp); + out_be32(uccf->p_ucce, UCCE_GRA); /* clear by writing 1 */ /* Issue host command */ cecr_subblock = @@ -1593,7 +1617,7 @@ static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) do { msleep(10); temp = in_be32(uccf->p_ucce); - } while (!(temp & UCC_GETH_UCCE_GRA) && --i); + } while (!(temp & UCCE_GRA) && --i); uccf->stopped_tx = 1; @@ -1951,9 +1975,12 @@ static void ucc_geth_set_multi(struct net_device *dev) uf_regs = ugeth->uccf->uf_regs; if (dev->flags & IFF_PROMISC) { - setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); + + out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr) | UPSMR_PRO); + } else { - clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); + + out_be32(&uf_regs->upsmr, in_be32(&uf_regs->upsmr)&~UPSMR_PRO); p_82xx_addr_filt = (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> @@ -1993,6 +2020,7 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth) { struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; struct phy_device *phydev = ugeth->phydev; + u32 tempval; ugeth_vdbg("%s: IN", __func__); @@ -2009,7 +2037,9 @@ static void ucc_geth_stop(struct ucc_geth_private *ugeth) out_be32(ugeth->uccf->p_ucce, 0xffffffff); /* Disable Rx and Tx */ - clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); + tempval = in_be32(&ug_regs->maccfg1); + tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); + out_be32(&ug_regs->maccfg1, tempval); ucc_geth_memclean(ugeth); } @@ -2123,10 +2153,10 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) /* Generate uccm_mask for receive */ uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ for (i = 0; i < ug_info->numQueuesRx; i++) - uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); + uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i); for (i = 0; i < ug_info->numQueuesTx; i++) - uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); + uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i); /* Initialize the general fast UCC block. */ if (ucc_fast_init(uf_info, &ugeth->uccf)) { if (netif_msg_probe(ugeth)) @@ -2155,7 +2185,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth) struct ucc_geth __iomem *ug_regs; int ret_val = -EINVAL; u32 remoder = UCC_GETH_REMODER_INIT; - u32 init_enet_pram_offset, cecr_subblock, command; + u32 init_enet_pram_offset, cecr_subblock, command, maccfg1; u32 ifstat, i, j, size, l2qt, l3qt, length; u16 temoder = UCC_GETH_TEMODER_INIT; u16 test; @@ -2251,7 +2281,10 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth) &uf_regs->upsmr, &ug_regs->uempr, &ug_regs->maccfg1); - setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); + maccfg1 = in_be32(&ug_regs->maccfg1); + maccfg1 |= MACCFG1_ENABLE_RX; + maccfg1 |= MACCFG1_ENABLE_TX; + out_be32(&ug_regs->maccfg1, maccfg1); /* Set IPGIFG */ /* For more details see the hardware spec. */ @@ -3241,6 +3274,7 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ) static int ucc_geth_poll(struct napi_struct *napi, int budget) { struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); + struct net_device *dev = ugeth->dev; struct ucc_geth_info *ug_info; int howmany, i; @@ -3251,8 +3285,14 @@ static int ucc_geth_poll(struct napi_struct *napi, int budget) howmany += ucc_geth_rx(ugeth, i, budget - howmany); if (howmany < budget) { + struct ucc_fast_private *uccf; + u32 uccm; + netif_rx_complete(napi); - setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS); + uccf = ugeth->uccf; + uccm = in_be32(uccf->p_uccm); + uccm |= UCCE_RX_EVENTS; + out_be32(uccf->p_uccm, uccm); } return howmany; @@ -3292,7 +3332,7 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info) /* Tx event processing */ if (ucce & UCCE_TX_EVENTS) { spin_lock(&ugeth->lock); - tx_mask = UCC_GETH_UCCE_TXB0; + tx_mask = UCCE_TXBF_SINGLE_MASK; for (i = 0; i < ug_info->numQueuesTx; i++) { if (ucce & tx_mask) ucc_geth_tx(dev, i); @@ -3304,10 +3344,12 @@ static irqreturn_t ucc_geth_irq_handler(int irq, void *info) /* Errors and other events */ if (ucce & UCCE_OTHER) { - if (ucce & UCC_GETH_UCCE_BSY) + if (ucce & UCCE_BSY) { dev->stats.rx_errors++; - if (ucce & UCC_GETH_UCCE_TXE) + } + if (ucce & UCCE_TXE) { dev->stats.tx_errors++; + } } return IRQ_HANDLED; diff --git a/trunk/drivers/net/ucc_geth.h b/trunk/drivers/net/ucc_geth.h index 8f699cb773ee..d74d2f7cb739 100644 --- a/trunk/drivers/net/ucc_geth.h +++ b/trunk/drivers/net/ucc_geth.h @@ -162,27 +162,92 @@ struct ucc_geth { boundary */ /* UCC GETH Event Register */ -#define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \ - UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \ - UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \ - UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0) - -#define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \ - UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \ - UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \ - UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0) - -#define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \ - UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \ - UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \ - UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0) - -#define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \ - UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \ - UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE) - -#define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY) -#define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE) +#define UCCE_MPD 0x80000000 /* Magic packet + detection */ +#define UCCE_SCAR 0x40000000 +#define UCCE_GRA 0x20000000 /* Tx graceful + stop + complete */ +#define UCCE_CBPR 0x10000000 +#define UCCE_BSY 0x08000000 +#define UCCE_RXC 0x04000000 +#define UCCE_TXC 0x02000000 +#define UCCE_TXE 0x01000000 +#define UCCE_TXB7 0x00800000 +#define UCCE_TXB6 0x00400000 +#define UCCE_TXB5 0x00200000 +#define UCCE_TXB4 0x00100000 +#define UCCE_TXB3 0x00080000 +#define UCCE_TXB2 0x00040000 +#define UCCE_TXB1 0x00020000 +#define UCCE_TXB0 0x00010000 +#define UCCE_RXB7 0x00008000 +#define UCCE_RXB6 0x00004000 +#define UCCE_RXB5 0x00002000 +#define UCCE_RXB4 0x00001000 +#define UCCE_RXB3 0x00000800 +#define UCCE_RXB2 0x00000400 +#define UCCE_RXB1 0x00000200 +#define UCCE_RXB0 0x00000100 +#define UCCE_RXF7 0x00000080 +#define UCCE_RXF6 0x00000040 +#define UCCE_RXF5 0x00000020 +#define UCCE_RXF4 0x00000010 +#define UCCE_RXF3 0x00000008 +#define UCCE_RXF2 0x00000004 +#define UCCE_RXF1 0x00000002 +#define UCCE_RXF0 0x00000001 + +#define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) +#define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) + +#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ + UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) +#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ + UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) +#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ + UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) +#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ + UCCE_RXC | UCCE_TXC | UCCE_TXE) + +#define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) +#define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) + +/* UCC GETH UPSMR (Protocol Specific Mode Register) */ +#define UPSMR_ECM 0x04000000 /* Enable CAM + Miss or + Enable + Filtering + Miss */ +#define UPSMR_HSE 0x02000000 /* Hardware + Statistics + Enable */ +#define UPSMR_PRO 0x00400000 /* Promiscuous*/ +#define UPSMR_CAP 0x00200000 /* CAM polarity + */ +#define UPSMR_RSH 0x00100000 /* Receive + Short Frames + */ +#define UPSMR_RPM 0x00080000 /* Reduced Pin + Mode + interfaces */ +#define UPSMR_R10M 0x00040000 /* RGMII/RMII + 10 Mode */ +#define UPSMR_RLPB 0x00020000 /* RMII + Loopback + Mode */ +#define UPSMR_TBIM 0x00010000 /* Ten-bit + Interface + Mode */ +#define UPSMR_RMM 0x00001000 /* RMII/RGMII + Mode */ +#define UPSMR_CAM 0x00000400 /* CAM Address + Matching */ +#define UPSMR_BRO 0x00000200 /* Broadcast + Address */ +#define UPSMR_RES1 0x00002000 /* Reserved + feild - must + be 1 */ /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control @@ -880,10 +945,9 @@ struct ucc_geth_hardware_statistics { #define UCC_GETH_REMODER_INIT 0 /* bits that must be set */ #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ - -/* Initial value for UPSMR */ -#define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1 - +#define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value + for this + register */ #define UCC_GETH_MACCFG1_INIT 0 #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) diff --git a/trunk/drivers/net/via-rhine.c b/trunk/drivers/net/via-rhine.c index 3b8e63254277..ac07cc6e3cb2 100644 --- a/trunk/drivers/net/via-rhine.c +++ b/trunk/drivers/net/via-rhine.c @@ -622,7 +622,6 @@ static const struct net_device_ops rhine_netdev_ops = { .ndo_get_stats = rhine_get_stats, .ndo_set_multicast_list = rhine_set_rx_mode, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_do_ioctl = netdev_ioctl, .ndo_tx_timeout = rhine_tx_timeout, #ifdef CONFIG_NET_POLL_CONTROLLER diff --git a/trunk/drivers/net/via-velocity.c b/trunk/drivers/net/via-velocity.c index a75f91dc3153..58e25d090ae0 100644 --- a/trunk/drivers/net/via-velocity.c +++ b/trunk/drivers/net/via-velocity.c @@ -855,7 +855,6 @@ static const struct net_device_ops velocity_netdev_ops = { .ndo_start_xmit = velocity_xmit, .ndo_get_stats = velocity_get_stats, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_set_multicast_list = velocity_set_multi, .ndo_change_mtu = velocity_change_mtu, .ndo_do_ioctl = velocity_ioctl, diff --git a/trunk/drivers/net/wd.c b/trunk/drivers/net/wd.c index d8322d2d1e29..3c1edda08d3d 100644 --- a/trunk/drivers/net/wd.c +++ b/trunk/drivers/net/wd.c @@ -155,7 +155,6 @@ static const struct net_device_ops wd_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/net/wireless/libertas/main.c b/trunk/drivers/net/wireless/libertas/main.c index 4e0007d20030..3dba83679444 100644 --- a/trunk/drivers/net/wireless/libertas/main.c +++ b/trunk/drivers/net/wireless/libertas/main.c @@ -1369,7 +1369,7 @@ EXPORT_SYMBOL_GPL(lbs_start_card); void lbs_stop_card(struct lbs_private *priv) { - struct net_device *dev; + struct net_device *dev = priv->dev; struct cmd_ctrl_node *cmdnode; unsigned long flags; @@ -1377,10 +1377,9 @@ void lbs_stop_card(struct lbs_private *priv) if (!priv) goto out; - dev = priv->dev; - netif_stop_queue(dev); - netif_carrier_off(dev); + netif_stop_queue(priv->dev); + netif_carrier_off(priv->dev); lbs_debugfs_remove_one(priv); if (priv->mesh_tlv) { diff --git a/trunk/drivers/net/yellowfin.c b/trunk/drivers/net/yellowfin.c index 2f1645dcb8c8..cf9712922778 100644 --- a/trunk/drivers/net/yellowfin.c +++ b/trunk/drivers/net/yellowfin.c @@ -362,7 +362,6 @@ static const struct net_device_ops netdev_ops = { .ndo_set_multicast_list = set_rx_mode, .ndo_change_mtu = eth_change_mtu, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_do_ioctl = netdev_ioctl, .ndo_tx_timeout = yellowfin_tx_timeout, }; diff --git a/trunk/drivers/net/zorro8390.c b/trunk/drivers/net/zorro8390.c index 37c84e3b8be0..affd904deafc 100644 --- a/trunk/drivers/net/zorro8390.c +++ b/trunk/drivers/net/zorro8390.c @@ -147,7 +147,6 @@ static const struct net_device_ops zorro8390_netdev_ops = { .ndo_get_stats = ei_get_stats, .ndo_set_multicast_list = ei_set_multicast_list, .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, .ndo_change_mtu = eth_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, diff --git a/trunk/drivers/parisc/superio.c b/trunk/drivers/parisc/superio.c index 4fa3bb2ddfe4..1e93c837514f 100644 --- a/trunk/drivers/parisc/superio.c +++ b/trunk/drivers/parisc/superio.c @@ -405,6 +405,7 @@ static void __init superio_serial_init(void) serial_port.type = PORT_16550A; serial_port.uartclk = 115200*16; serial_port.fifosize = 16; + spin_lock_init(&serial_port.lock); /* serial port #1 */ serial_port.iobase = sio_dev.sp1_base; diff --git a/trunk/drivers/pci/intel-iommu.c b/trunk/drivers/pci/intel-iommu.c index 3dfecb20d5e7..235fb7a5a8a5 100644 --- a/trunk/drivers/pci/intel-iommu.c +++ b/trunk/drivers/pci/intel-iommu.c @@ -438,8 +438,7 @@ static struct intel_iommu *device_to_iommu(u8 bus, u8 devfn) continue; for (i = 0; i < drhd->devices_cnt; i++) - if (drhd->devices[i] && - drhd->devices[i]->bus->number == bus && + if (drhd->devices[i]->bus->number == bus && drhd->devices[i]->devfn == devfn) return drhd->iommu; diff --git a/trunk/drivers/power/Kconfig b/trunk/drivers/power/Kconfig index 33da1127992a..668472405a57 100644 --- a/trunk/drivers/power/Kconfig +++ b/trunk/drivers/power/Kconfig @@ -82,10 +82,4 @@ config BATTERY_DA9030 Say Y here to enable support for batteries charger integrated into DA9030 PMIC. -config CHARGER_PCF50633 - tristate "NXP PCF50633 MBC" - depends on MFD_PCF50633 - help - Say Y to include support for NXP PCF50633 Main Battery Charger. - endif # POWER_SUPPLY diff --git a/trunk/drivers/power/Makefile b/trunk/drivers/power/Makefile index 2fcf41d13e5c..eebb15505a40 100644 --- a/trunk/drivers/power/Makefile +++ b/trunk/drivers/power/Makefile @@ -25,4 +25,3 @@ obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o -obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o \ No newline at end of file diff --git a/trunk/drivers/power/pcf50633-charger.c b/trunk/drivers/power/pcf50633-charger.c deleted file mode 100644 index e988ec130fcd..000000000000 --- a/trunk/drivers/power/pcf50633-charger.c +++ /dev/null @@ -1,358 +0,0 @@ -/* NXP PCF50633 Main Battery Charger Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte, Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -struct pcf50633_mbc { - struct pcf50633 *pcf; - - int adapter_active; - int adapter_online; - int usb_active; - int usb_online; - - struct power_supply usb; - struct power_supply adapter; -}; - -int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma) -{ - struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); - int ret = 0; - u8 bits; - - if (ma >= 1000) - bits = PCF50633_MBCC7_USB_1000mA; - else if (ma >= 500) - bits = PCF50633_MBCC7_USB_500mA; - else if (ma >= 100) - bits = PCF50633_MBCC7_USB_100mA; - else - bits = PCF50633_MBCC7_USB_SUSPEND; - - ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7, - PCF50633_MBCC7_USB_MASK, bits); - if (ret) - dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma); - else - dev_info(pcf->dev, "usb curlim to %d mA\n", ma); - - power_supply_changed(&mbc->usb); - - return ret; -} -EXPORT_SYMBOL_GPL(pcf50633_mbc_usb_curlim_set); - -int pcf50633_mbc_get_status(struct pcf50633 *pcf) -{ - struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); - int status = 0; - - if (mbc->usb_online) - status |= PCF50633_MBC_USB_ONLINE; - if (mbc->usb_active) - status |= PCF50633_MBC_USB_ACTIVE; - if (mbc->adapter_online) - status |= PCF50633_MBC_ADAPTER_ONLINE; - if (mbc->adapter_active) - status |= PCF50633_MBC_ADAPTER_ACTIVE; - - return status; -} -EXPORT_SYMBOL_GPL(pcf50633_mbc_get_status); - -void pcf50633_mbc_set_status(struct pcf50633 *pcf, int what, int status) -{ - struct pcf50633_mbc *mbc = platform_get_drvdata(pcf->mbc_pdev); - - if (what & PCF50633_MBC_USB_ONLINE) - mbc->usb_online = !!status; - if (what & PCF50633_MBC_USB_ACTIVE) - mbc->usb_active = !!status; - if (what & PCF50633_MBC_ADAPTER_ONLINE) - mbc->adapter_online = !!status; - if (what & PCF50633_MBC_ADAPTER_ACTIVE) - mbc->adapter_active = !!status; -} -EXPORT_SYMBOL_GPL(pcf50633_mbc_set_status); - -static ssize_t -show_chgmode(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct pcf50633_mbc *mbc = dev_get_drvdata(dev); - - u8 mbcs2 = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCS2); - u8 chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK); - - return sprintf(buf, "%d\n", chgmod); -} -static DEVICE_ATTR(chgmode, S_IRUGO, show_chgmode, NULL); - -static ssize_t -show_usblim(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct pcf50633_mbc *mbc = dev_get_drvdata(dev); - u8 usblim = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCC7) & - PCF50633_MBCC7_USB_MASK; - unsigned int ma; - - if (usblim == PCF50633_MBCC7_USB_1000mA) - ma = 1000; - else if (usblim == PCF50633_MBCC7_USB_500mA) - ma = 500; - else if (usblim == PCF50633_MBCC7_USB_100mA) - ma = 100; - else - ma = 0; - - return sprintf(buf, "%u\n", ma); -} - -static ssize_t set_usblim(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct pcf50633_mbc *mbc = dev_get_drvdata(dev); - unsigned long ma; - int ret; - - ret = strict_strtoul(buf, 10, &ma); - if (ret) - return -EINVAL; - - pcf50633_mbc_usb_curlim_set(mbc->pcf, ma); - - return count; -} - -static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, set_usblim); - -static struct attribute *pcf50633_mbc_sysfs_entries[] = { - &dev_attr_chgmode.attr, - &dev_attr_usb_curlim.attr, - NULL, -}; - -static struct attribute_group mbc_attr_group = { - .name = NULL, /* put in device directory */ - .attrs = pcf50633_mbc_sysfs_entries, -}; - -static void -pcf50633_mbc_irq_handler(int irq, void *data) -{ - struct pcf50633_mbc *mbc = data; - - /* USB */ - if (irq == PCF50633_IRQ_USBINS) { - mbc->usb_online = 1; - } else if (irq == PCF50633_IRQ_USBREM) { - mbc->usb_online = 0; - mbc->usb_active = 0; - pcf50633_mbc_usb_curlim_set(mbc->pcf, 0); - } - - /* Adapter */ - if (irq == PCF50633_IRQ_ADPINS) { - mbc->adapter_online = 1; - mbc->adapter_active = 1; - } else if (irq == PCF50633_IRQ_ADPREM) { - mbc->adapter_online = 0; - mbc->adapter_active = 0; - } - - if (irq == PCF50633_IRQ_BATFULL) { - mbc->usb_active = 0; - mbc->adapter_active = 0; - } - - power_supply_changed(&mbc->usb); - power_supply_changed(&mbc->adapter); - - if (mbc->pcf->pdata->mbc_event_callback) - mbc->pcf->pdata->mbc_event_callback(mbc->pcf, irq); -} - -static int adapter_get_property(struct power_supply *psy, - enum power_supply_property psp, - union power_supply_propval *val) -{ - struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb); - int ret = 0; - - switch (psp) { - case POWER_SUPPLY_PROP_ONLINE: - val->intval = mbc->adapter_online; - break; - default: - ret = -EINVAL; - break; - } - return ret; -} - -static int usb_get_property(struct power_supply *psy, - enum power_supply_property psp, - union power_supply_propval *val) -{ - struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb); - int ret = 0; - - switch (psp) { - case POWER_SUPPLY_PROP_ONLINE: - val->intval = mbc->usb_online; - break; - default: - ret = -EINVAL; - break; - } - return ret; -} - -static enum power_supply_property power_props[] = { - POWER_SUPPLY_PROP_ONLINE, -}; - -static const u8 mbc_irq_handlers[] = { - PCF50633_IRQ_ADPINS, - PCF50633_IRQ_ADPREM, - PCF50633_IRQ_USBINS, - PCF50633_IRQ_USBREM, - PCF50633_IRQ_BATFULL, - PCF50633_IRQ_CHGHALT, - PCF50633_IRQ_THLIMON, - PCF50633_IRQ_THLIMOFF, - PCF50633_IRQ_USBLIMON, - PCF50633_IRQ_USBLIMOFF, - PCF50633_IRQ_LOWSYS, - PCF50633_IRQ_LOWBAT, -}; - -static int __devinit pcf50633_mbc_probe(struct platform_device *pdev) -{ - struct pcf50633_mbc *mbc; - struct pcf50633_subdev_pdata *pdata = pdev->dev.platform_data; - int ret; - int i; - u8 mbcs1; - - mbc = kzalloc(sizeof(*mbc), GFP_KERNEL); - if (!mbc) - return -ENOMEM; - - platform_set_drvdata(pdev, mbc); - mbc->pcf = pdata->pcf; - - /* Set up IRQ handlers */ - for (i = 0; i < ARRAY_SIZE(mbc_irq_handlers); i++) - pcf50633_register_irq(mbc->pcf, mbc_irq_handlers[i], - pcf50633_mbc_irq_handler, mbc); - - /* Create power supplies */ - mbc->adapter.name = "adapter"; - mbc->adapter.type = POWER_SUPPLY_TYPE_MAINS; - mbc->adapter.properties = power_props; - mbc->adapter.num_properties = ARRAY_SIZE(power_props); - mbc->adapter.get_property = &adapter_get_property; - mbc->adapter.supplied_to = mbc->pcf->pdata->batteries; - mbc->adapter.num_supplicants = mbc->pcf->pdata->num_batteries; - - mbc->usb.name = "usb"; - mbc->usb.type = POWER_SUPPLY_TYPE_USB; - mbc->usb.properties = power_props; - mbc->usb.num_properties = ARRAY_SIZE(power_props); - mbc->usb.get_property = usb_get_property; - mbc->usb.supplied_to = mbc->pcf->pdata->batteries; - mbc->usb.num_supplicants = mbc->pcf->pdata->num_batteries; - - ret = power_supply_register(&pdev->dev, &mbc->adapter); - if (ret) { - dev_err(mbc->pcf->dev, "failed to register adapter\n"); - kfree(mbc); - return ret; - } - - ret = power_supply_register(&pdev->dev, &mbc->usb); - if (ret) { - dev_err(mbc->pcf->dev, "failed to register usb\n"); - power_supply_unregister(&mbc->adapter); - kfree(mbc); - return ret; - } - - ret = sysfs_create_group(&pdev->dev.kobj, &mbc_attr_group); - if (ret) - dev_err(mbc->pcf->dev, "failed to create sysfs entries\n"); - - mbcs1 = pcf50633_reg_read(mbc->pcf, PCF50633_REG_MBCS1); - if (mbcs1 & PCF50633_MBCS1_USBPRES) - pcf50633_mbc_irq_handler(PCF50633_IRQ_USBINS, mbc); - if (mbcs1 & PCF50633_MBCS1_ADAPTPRES) - pcf50633_mbc_irq_handler(PCF50633_IRQ_ADPINS, mbc); - - return 0; -} - -static int __devexit pcf50633_mbc_remove(struct platform_device *pdev) -{ - struct pcf50633_mbc *mbc = platform_get_drvdata(pdev); - int i; - - /* Remove IRQ handlers */ - for (i = 0; i < ARRAY_SIZE(mbc_irq_handlers); i++) - pcf50633_free_irq(mbc->pcf, mbc_irq_handlers[i]); - - power_supply_unregister(&mbc->usb); - power_supply_unregister(&mbc->adapter); - - kfree(mbc); - - return 0; -} - -static struct platform_driver pcf50633_mbc_driver = { - .driver = { - .name = "pcf50633-mbc", - }, - .probe = pcf50633_mbc_probe, - .remove = __devexit_p(pcf50633_mbc_remove), -}; - -static int __init pcf50633_mbc_init(void) -{ - return platform_driver_register(&pcf50633_mbc_driver); -} -module_init(pcf50633_mbc_init); - -static void __exit pcf50633_mbc_exit(void) -{ - platform_driver_unregister(&pcf50633_mbc_driver); -} -module_exit(pcf50633_mbc_exit); - -MODULE_AUTHOR("Balaji Rao "); -MODULE_DESCRIPTION("PCF50633 mbc driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pcf50633-mbc"); diff --git a/trunk/drivers/regulator/Kconfig b/trunk/drivers/regulator/Kconfig index e7e0cf102d6d..39360e2a4540 100644 --- a/trunk/drivers/regulator/Kconfig +++ b/trunk/drivers/regulator/Kconfig @@ -73,11 +73,4 @@ config REGULATOR_DA903X Say y here to support the BUCKs and LDOs regulators found on Dialog Semiconductor DA9030/DA9034 PMIC. -config REGULATOR_PCF50633 - tristate "PCF50633 regulator driver" - depends on MFD_PCF50633 - help - Say Y here to support the voltage regulators and convertors - on PCF50633 - endif diff --git a/trunk/drivers/regulator/Makefile b/trunk/drivers/regulator/Makefile index 61b30c6ddecc..254d40c02ee8 100644 --- a/trunk/drivers/regulator/Makefile +++ b/trunk/drivers/regulator/Makefile @@ -11,6 +11,5 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o obj-$(CONFIG_REGULATOR_DA903X) += da903x.o -obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG diff --git a/trunk/drivers/regulator/pcf50633-regulator.c b/trunk/drivers/regulator/pcf50633-regulator.c deleted file mode 100644 index 4cc85ec6e120..000000000000 --- a/trunk/drivers/regulator/pcf50633-regulator.c +++ /dev/null @@ -1,329 +0,0 @@ -/* NXP PCF50633 PMIC Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte and Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#define PCF50633_REGULATOR(_name, _id) \ - { \ - .name = _name, \ - .id = _id, \ - .ops = &pcf50633_regulator_ops, \ - .type = REGULATOR_VOLTAGE, \ - .owner = THIS_MODULE, \ - } - -static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = { - [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT, - [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT, - [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT, - [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT, - [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT, - [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT, - [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT, - [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT, - [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT, - [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT, - [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT, -}; - -/* Bits from voltage value */ -static u8 auto_voltage_bits(unsigned int millivolts) -{ - if (millivolts < 1800) - return 0; - if (millivolts > 3800) - return 0xff; - - millivolts -= 625; - - return millivolts / 25; -} - -static u8 down_voltage_bits(unsigned int millivolts) -{ - if (millivolts < 625) - return 0; - else if (millivolts > 3000) - return 0xff; - - millivolts -= 625; - - return millivolts / 25; -} - -static u8 ldo_voltage_bits(unsigned int millivolts) -{ - if (millivolts < 900) - return 0; - else if (millivolts > 3600) - return 0x1f; - - millivolts -= 900; - return millivolts / 100; -} - -/* Obtain voltage value from bits */ -static unsigned int auto_voltage_value(u8 bits) -{ - if (bits < 0x2f) - return 0; - - return 625 + (bits * 25); -} - - -static unsigned int down_voltage_value(u8 bits) -{ - return 625 + (bits * 25); -} - - -static unsigned int ldo_voltage_value(u8 bits) -{ - bits &= 0x1f; - - return 900 + (bits * 100); -} - -static int pcf50633_regulator_set_voltage(struct regulator_dev *rdev, - int min_uV, int max_uV) -{ - struct pcf50633 *pcf; - int regulator_id, millivolts; - u8 volt_bits, regnr; - - pcf = rdev_get_drvdata(rdev); - - regulator_id = rdev_get_id(rdev); - if (regulator_id >= PCF50633_NUM_REGULATORS) - return -EINVAL; - - millivolts = min_uV / 1000; - - regnr = pcf50633_regulator_registers[regulator_id]; - - switch (regulator_id) { - case PCF50633_REGULATOR_AUTO: - volt_bits = auto_voltage_bits(millivolts); - break; - case PCF50633_REGULATOR_DOWN1: - volt_bits = down_voltage_bits(millivolts); - break; - case PCF50633_REGULATOR_DOWN2: - volt_bits = down_voltage_bits(millivolts); - break; - case PCF50633_REGULATOR_LDO1: - case PCF50633_REGULATOR_LDO2: - case PCF50633_REGULATOR_LDO3: - case PCF50633_REGULATOR_LDO4: - case PCF50633_REGULATOR_LDO5: - case PCF50633_REGULATOR_LDO6: - case PCF50633_REGULATOR_HCLDO: - volt_bits = ldo_voltage_bits(millivolts); - break; - default: - return -EINVAL; - } - - return pcf50633_reg_write(pcf, regnr, volt_bits); -} - -static int pcf50633_regulator_get_voltage(struct regulator_dev *rdev) -{ - struct pcf50633 *pcf; - int regulator_id, millivolts, volt_bits; - u8 regnr; - - pcf = rdev_get_drvdata(rdev);; - - regulator_id = rdev_get_id(rdev); - if (regulator_id >= PCF50633_NUM_REGULATORS) - return -EINVAL; - - regnr = pcf50633_regulator_registers[regulator_id]; - - volt_bits = pcf50633_reg_read(pcf, regnr); - if (volt_bits < 0) - return -1; - - switch (regulator_id) { - case PCF50633_REGULATOR_AUTO: - millivolts = auto_voltage_value(volt_bits); - break; - case PCF50633_REGULATOR_DOWN1: - millivolts = down_voltage_value(volt_bits); - break; - case PCF50633_REGULATOR_DOWN2: - millivolts = down_voltage_value(volt_bits); - break; - case PCF50633_REGULATOR_LDO1: - case PCF50633_REGULATOR_LDO2: - case PCF50633_REGULATOR_LDO3: - case PCF50633_REGULATOR_LDO4: - case PCF50633_REGULATOR_LDO5: - case PCF50633_REGULATOR_LDO6: - case PCF50633_REGULATOR_HCLDO: - millivolts = ldo_voltage_value(volt_bits); - break; - default: - return -EINVAL; - } - - return millivolts * 1000; -} - -static int pcf50633_regulator_enable(struct regulator_dev *rdev) -{ - struct pcf50633 *pcf = rdev_get_drvdata(rdev); - int regulator_id; - u8 regnr; - - regulator_id = rdev_get_id(rdev); - if (regulator_id >= PCF50633_NUM_REGULATORS) - return -EINVAL; - - /* The *ENA register is always one after the *OUT register */ - regnr = pcf50633_regulator_registers[regulator_id] + 1; - - return pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON, - PCF50633_REGULATOR_ON); -} - -static int pcf50633_regulator_disable(struct regulator_dev *rdev) -{ - struct pcf50633 *pcf = rdev_get_drvdata(rdev); - int regulator_id; - u8 regnr; - - regulator_id = rdev_get_id(rdev); - if (regulator_id >= PCF50633_NUM_REGULATORS) - return -EINVAL; - - /* the *ENA register is always one after the *OUT register */ - regnr = pcf50633_regulator_registers[regulator_id] + 1; - - return pcf50633_reg_set_bit_mask(pcf, regnr, - PCF50633_REGULATOR_ON, 0); -} - -static int pcf50633_regulator_is_enabled(struct regulator_dev *rdev) -{ - struct pcf50633 *pcf = rdev_get_drvdata(rdev); - int regulator_id = rdev_get_id(rdev); - u8 regnr; - - regulator_id = rdev_get_id(rdev); - if (regulator_id >= PCF50633_NUM_REGULATORS) - return -EINVAL; - - /* the *ENA register is always one after the *OUT register */ - regnr = pcf50633_regulator_registers[regulator_id] + 1; - - return pcf50633_reg_read(pcf, regnr) & PCF50633_REGULATOR_ON; -} - -static struct regulator_ops pcf50633_regulator_ops = { - .set_voltage = pcf50633_regulator_set_voltage, - .get_voltage = pcf50633_regulator_get_voltage, - .enable = pcf50633_regulator_enable, - .disable = pcf50633_regulator_disable, - .is_enabled = pcf50633_regulator_is_enabled, -}; - -static struct regulator_desc regulators[] = { - [PCF50633_REGULATOR_AUTO] = - PCF50633_REGULATOR("auto", PCF50633_REGULATOR_AUTO), - [PCF50633_REGULATOR_DOWN1] = - PCF50633_REGULATOR("down1", PCF50633_REGULATOR_DOWN1), - [PCF50633_REGULATOR_DOWN2] = - PCF50633_REGULATOR("down2", PCF50633_REGULATOR_DOWN2), - [PCF50633_REGULATOR_LDO1] = - PCF50633_REGULATOR("ldo1", PCF50633_REGULATOR_LDO1), - [PCF50633_REGULATOR_LDO2] = - PCF50633_REGULATOR("ldo2", PCF50633_REGULATOR_LDO2), - [PCF50633_REGULATOR_LDO3] = - PCF50633_REGULATOR("ldo3", PCF50633_REGULATOR_LDO3), - [PCF50633_REGULATOR_LDO4] = - PCF50633_REGULATOR("ldo4", PCF50633_REGULATOR_LDO4), - [PCF50633_REGULATOR_LDO5] = - PCF50633_REGULATOR("ldo5", PCF50633_REGULATOR_LDO5), - [PCF50633_REGULATOR_LDO6] = - PCF50633_REGULATOR("ldo6", PCF50633_REGULATOR_LDO6), - [PCF50633_REGULATOR_HCLDO] = - PCF50633_REGULATOR("hcldo", PCF50633_REGULATOR_HCLDO), - [PCF50633_REGULATOR_MEMLDO] = - PCF50633_REGULATOR("memldo", PCF50633_REGULATOR_MEMLDO), -}; - -static int __devinit pcf50633_regulator_probe(struct platform_device *pdev) -{ - struct regulator_dev *rdev; - struct pcf50633 *pcf; - - /* Already set by core driver */ - pcf = platform_get_drvdata(pdev); - - rdev = regulator_register(®ulators[pdev->id], &pdev->dev, pcf); - if (IS_ERR(rdev)) - return PTR_ERR(rdev); - - if (pcf->pdata->regulator_registered) - pcf->pdata->regulator_registered(pcf, pdev->id); - - return 0; -} - -static int __devexit pcf50633_regulator_remove(struct platform_device *pdev) -{ - struct regulator_dev *rdev = platform_get_drvdata(pdev); - - regulator_unregister(rdev); - - return 0; -} - -static struct platform_driver pcf50633_regulator_driver = { - .driver = { - .name = "pcf50633-regltr", - }, - .probe = pcf50633_regulator_probe, - .remove = __devexit_p(pcf50633_regulator_remove), -}; - -static int __init pcf50633_regulator_init(void) -{ - return platform_driver_register(&pcf50633_regulator_driver); -} -module_init(pcf50633_regulator_init); - -static void __exit pcf50633_regulator_exit(void) -{ - platform_driver_unregister(&pcf50633_regulator_driver); -} -module_exit(pcf50633_regulator_exit); - -MODULE_AUTHOR("Balaji Rao "); -MODULE_DESCRIPTION("PCF50633 regulator driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pcf50633-regulator"); diff --git a/trunk/drivers/rtc/Kconfig b/trunk/drivers/rtc/Kconfig index cced4d108319..4ad831de41ad 100644 --- a/trunk/drivers/rtc/Kconfig +++ b/trunk/drivers/rtc/Kconfig @@ -502,13 +502,6 @@ config RTC_DRV_WM8350 This driver can also be built as a module. If so, the module will be called "rtc-wm8350". -config RTC_DRV_PCF50633 - depends on MFD_PCF50633 - tristate "NXP PCF50633 RTC" - help - If you say yes here you get support for the RTC subsystem of the - NXP PCF50633 used in embedded systems. - comment "on-CPU RTC drivers" config RTC_DRV_OMAP diff --git a/trunk/drivers/rtc/Makefile b/trunk/drivers/rtc/Makefile index 6e28021abb9d..9a4340d48f26 100644 --- a/trunk/drivers/rtc/Makefile +++ b/trunk/drivers/rtc/Makefile @@ -74,4 +74,3 @@ obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o -obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o diff --git a/trunk/drivers/rtc/rtc-pcf50633.c b/trunk/drivers/rtc/rtc-pcf50633.c deleted file mode 100644 index f4dd87e29075..000000000000 --- a/trunk/drivers/rtc/rtc-pcf50633.c +++ /dev/null @@ -1,344 +0,0 @@ -/* NXP PCF50633 RTC Driver - * - * (C) 2006-2008 by Openmoko, Inc. - * Author: Balaji Rao - * All rights reserved. - * - * Broken down from monstrous PCF50633 driver mainly by - * Harald Welte, Andy Green and Werner Almesberger - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define PCF50633_REG_RTCSC 0x59 /* Second */ -#define PCF50633_REG_RTCMN 0x5a /* Minute */ -#define PCF50633_REG_RTCHR 0x5b /* Hour */ -#define PCF50633_REG_RTCWD 0x5c /* Weekday */ -#define PCF50633_REG_RTCDT 0x5d /* Day */ -#define PCF50633_REG_RTCMT 0x5e /* Month */ -#define PCF50633_REG_RTCYR 0x5f /* Year */ -#define PCF50633_REG_RTCSCA 0x60 /* Alarm Second */ -#define PCF50633_REG_RTCMNA 0x61 /* Alarm Minute */ -#define PCF50633_REG_RTCHRA 0x62 /* Alarm Hour */ -#define PCF50633_REG_RTCWDA 0x63 /* Alarm Weekday */ -#define PCF50633_REG_RTCDTA 0x64 /* Alarm Day */ -#define PCF50633_REG_RTCMTA 0x65 /* Alarm Month */ -#define PCF50633_REG_RTCYRA 0x66 /* Alarm Year */ - -enum pcf50633_time_indexes { - PCF50633_TI_SEC, - PCF50633_TI_MIN, - PCF50633_TI_HOUR, - PCF50633_TI_WKDAY, - PCF50633_TI_DAY, - PCF50633_TI_MONTH, - PCF50633_TI_YEAR, - PCF50633_TI_EXTENT /* always last */ -}; - -struct pcf50633_time { - u_int8_t time[PCF50633_TI_EXTENT]; -}; - -struct pcf50633_rtc { - int alarm_enabled; - int second_enabled; - - struct pcf50633 *pcf; - struct rtc_device *rtc_dev; -}; - -static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf) -{ - rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]); - rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]); - rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]); - rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]); - rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]); - rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]); - rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100; -} - -static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc) -{ - pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec); - pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min); - pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour); - pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday); - pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday); - pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon); - pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year % 100); -} - -static int -pcf50633_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) -{ - struct pcf50633_rtc *rtc = dev_get_drvdata(dev); - int err; - - if (enabled) - err = pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); - else - err = pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); - - if (err < 0) - return err; - - rtc->alarm_enabled = enabled; - - return 0; -} - -static int -pcf50633_rtc_update_irq_enable(struct device *dev, unsigned int enabled) -{ - struct pcf50633_rtc *rtc = dev_get_drvdata(dev); - int err; - - if (enabled) - err = pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_SECOND); - else - err = pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_SECOND); - - if (err < 0) - return err; - - rtc->second_enabled = enabled; - - return 0; -} - -static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm) -{ - struct pcf50633_rtc *rtc; - struct pcf50633_time pcf_tm; - int ret; - - rtc = dev_get_drvdata(dev); - - ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSC, - PCF50633_TI_EXTENT, - &pcf_tm.time[0]); - if (ret != PCF50633_TI_EXTENT) { - dev_err(dev, "Failed to read time\n"); - return -EIO; - } - - dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n", - pcf_tm.time[PCF50633_TI_DAY], - pcf_tm.time[PCF50633_TI_MONTH], - pcf_tm.time[PCF50633_TI_YEAR], - pcf_tm.time[PCF50633_TI_HOUR], - pcf_tm.time[PCF50633_TI_MIN], - pcf_tm.time[PCF50633_TI_SEC]); - - pcf2rtc_time(tm, &pcf_tm); - - dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n", - tm->tm_mday, tm->tm_mon, tm->tm_year, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - return rtc_valid_tm(tm); -} - -static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm) -{ - struct pcf50633_rtc *rtc; - struct pcf50633_time pcf_tm; - int second_masked, alarm_masked, ret = 0; - - rtc = dev_get_drvdata(dev); - - dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n", - tm->tm_mday, tm->tm_mon, tm->tm_year, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - rtc2pcf_time(&pcf_tm, tm); - - dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n", - pcf_tm.time[PCF50633_TI_DAY], - pcf_tm.time[PCF50633_TI_MONTH], - pcf_tm.time[PCF50633_TI_YEAR], - pcf_tm.time[PCF50633_TI_HOUR], - pcf_tm.time[PCF50633_TI_MIN], - pcf_tm.time[PCF50633_TI_SEC]); - - - second_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_SECOND); - alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM); - - if (!second_masked) - pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_SECOND); - if (!alarm_masked) - pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); - - /* Returns 0 on success */ - ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSC, - PCF50633_TI_EXTENT, - &pcf_tm.time[0]); - - if (!second_masked) - pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_SECOND); - if (!alarm_masked) - pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); - - return ret; -} - -static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) -{ - struct pcf50633_rtc *rtc; - struct pcf50633_time pcf_tm; - int ret = 0; - - rtc = dev_get_drvdata(dev); - - alrm->enabled = rtc->alarm_enabled; - - ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSCA, - PCF50633_TI_EXTENT, &pcf_tm.time[0]); - if (ret != PCF50633_TI_EXTENT) { - dev_err(dev, "Failed to read time\n"); - return -EIO; - } - - pcf2rtc_time(&alrm->time, &pcf_tm); - - return rtc_valid_tm(&alrm->time); -} - -static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) -{ - struct pcf50633_rtc *rtc; - struct pcf50633_time pcf_tm; - int alarm_masked, ret = 0; - - rtc = dev_get_drvdata(dev); - - rtc2pcf_time(&pcf_tm, &alrm->time); - - /* do like mktime does and ignore tm_wday */ - pcf_tm.time[PCF50633_TI_WKDAY] = 7; - - alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM); - - /* disable alarm interrupt */ - if (!alarm_masked) - pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM); - - /* Returns 0 on success */ - ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSCA, - PCF50633_TI_EXTENT, &pcf_tm.time[0]); - - if (!alarm_masked) - pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM); - - return ret; -} - -static struct rtc_class_ops pcf50633_rtc_ops = { - .read_time = pcf50633_rtc_read_time, - .set_time = pcf50633_rtc_set_time, - .read_alarm = pcf50633_rtc_read_alarm, - .set_alarm = pcf50633_rtc_set_alarm, - .alarm_irq_enable = pcf50633_rtc_alarm_irq_enable, - .update_irq_enable = pcf50633_rtc_update_irq_enable, -}; - -static void pcf50633_rtc_irq(int irq, void *data) -{ - struct pcf50633_rtc *rtc = data; - - switch (irq) { - case PCF50633_IRQ_ALARM: - rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); - break; - case PCF50633_IRQ_SECOND: - rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); - break; - } -} - -static int __devinit pcf50633_rtc_probe(struct platform_device *pdev) -{ - struct pcf50633_subdev_pdata *pdata; - struct pcf50633_rtc *rtc; - - - rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); - if (!rtc) - return -ENOMEM; - - pdata = pdev->dev.platform_data; - rtc->pcf = pdata->pcf; - platform_set_drvdata(pdev, rtc); - rtc->rtc_dev = rtc_device_register("pcf50633-rtc", &pdev->dev, - &pcf50633_rtc_ops, THIS_MODULE); - - if (IS_ERR(rtc->rtc_dev)) { - kfree(rtc); - return PTR_ERR(rtc->rtc_dev); - } - - pcf50633_register_irq(rtc->pcf, PCF50633_IRQ_ALARM, - pcf50633_rtc_irq, rtc); - pcf50633_register_irq(rtc->pcf, PCF50633_IRQ_SECOND, - pcf50633_rtc_irq, rtc); - - return 0; -} - -static int __devexit pcf50633_rtc_remove(struct platform_device *pdev) -{ - struct pcf50633_rtc *rtc; - - rtc = platform_get_drvdata(pdev); - - pcf50633_free_irq(rtc->pcf, PCF50633_IRQ_ALARM); - pcf50633_free_irq(rtc->pcf, PCF50633_IRQ_SECOND); - - rtc_device_unregister(rtc->rtc_dev); - kfree(rtc); - - return 0; -} - -static struct platform_driver pcf50633_rtc_driver = { - .driver = { - .name = "pcf50633-rtc", - }, - .probe = pcf50633_rtc_probe, - .remove = __devexit_p(pcf50633_rtc_remove), -}; - -static int __init pcf50633_rtc_init(void) -{ - return platform_driver_register(&pcf50633_rtc_driver); -} -module_init(pcf50633_rtc_init); - -static void __exit pcf50633_rtc_exit(void) -{ - platform_driver_unregister(&pcf50633_rtc_driver); -} -module_exit(pcf50633_rtc_exit); - -MODULE_DESCRIPTION("PCF50633 RTC driver"); -MODULE_AUTHOR("Balaji Rao "); -MODULE_LICENSE("GPL"); - diff --git a/trunk/drivers/s390/net/qeth_l2_main.c b/trunk/drivers/s390/net/qeth_l2_main.c index 07ab8a5c1c46..c4f1b046c3b1 100644 --- a/trunk/drivers/s390/net/qeth_l2_main.c +++ b/trunk/drivers/s390/net/qeth_l2_main.c @@ -916,7 +916,7 @@ static struct ethtool_ops qeth_l2_osn_ops = { .get_drvinfo = qeth_core_get_drvinfo, }; -static const struct net_device_ops qeth_l2_netdev_ops = { +static struct net_device_ops qeth_l2_netdev_ops = { .ndo_open = qeth_l2_open, .ndo_stop = qeth_l2_stop, .ndo_get_stats = qeth_get_stats, diff --git a/trunk/drivers/s390/net/qeth_l3_main.c b/trunk/drivers/s390/net/qeth_l3_main.c index 3d04920b9bb9..68d623ab7e6e 100644 --- a/trunk/drivers/s390/net/qeth_l3_main.c +++ b/trunk/drivers/s390/net/qeth_l3_main.c @@ -2894,7 +2894,7 @@ qeth_l3_neigh_setup(struct net_device *dev, struct neigh_parms *np) return 0; } -static const struct net_device_ops qeth_l3_netdev_ops = { +static struct net_device_ops qeth_l3_netdev_ops = { .ndo_open = qeth_l3_open, .ndo_stop = qeth_l3_stop, .ndo_get_stats = qeth_get_stats, @@ -2909,22 +2909,6 @@ static const struct net_device_ops qeth_l3_netdev_ops = { .ndo_tx_timeout = qeth_tx_timeout, }; -static const struct net_device_ops qeth_l3_osa_netdev_ops = { - .ndo_open = qeth_l3_open, - .ndo_stop = qeth_l3_stop, - .ndo_get_stats = qeth_get_stats, - .ndo_start_xmit = qeth_l3_hard_start_xmit, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_multicast_list = qeth_l3_set_multicast_list, - .ndo_do_ioctl = qeth_l3_do_ioctl, - .ndo_change_mtu = qeth_change_mtu, - .ndo_vlan_rx_register = qeth_l3_vlan_rx_register, - .ndo_vlan_rx_add_vid = qeth_l3_vlan_rx_add_vid, - .ndo_vlan_rx_kill_vid = qeth_l3_vlan_rx_kill_vid, - .ndo_tx_timeout = qeth_tx_timeout, - .ndo_neigh_setup = qeth_l3_neigh_setup, -}; - static int qeth_l3_setup_netdev(struct qeth_card *card) { if (card->info.type == QETH_CARD_TYPE_OSAE) { @@ -2935,12 +2919,12 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) #endif if (!card->dev) return -ENODEV; - card->dev->netdev_ops = &qeth_l3_netdev_ops; } else { card->dev = alloc_etherdev(0); if (!card->dev) return -ENODEV; - card->dev->netdev_ops = &qeth_l3_osa_netdev_ops; + qeth_l3_netdev_ops.ndo_neigh_setup = + qeth_l3_neigh_setup; /*IPv6 address autoconfiguration stuff*/ qeth_l3_get_unique_id(card); @@ -2953,7 +2937,6 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) if (!card->dev) return -ENODEV; card->dev->flags |= IFF_NOARP; - card->dev->netdev_ops = &qeth_l3_netdev_ops; qeth_l3_iqd_read_initial_mac(card); } else return -ENODEV; @@ -2961,6 +2944,7 @@ static int qeth_l3_setup_netdev(struct qeth_card *card) card->dev->ml_priv = card; card->dev->watchdog_timeo = QETH_TX_TIMEOUT; card->dev->mtu = card->info.initial_mtu; + card->dev->netdev_ops = &qeth_l3_netdev_ops; SET_ETHTOOL_OPS(card->dev, &qeth_l3_ethtool_ops); card->dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | diff --git a/trunk/drivers/serial/8250.c b/trunk/drivers/serial/8250.c index 0d934bfbdd9b..1889a63ebc22 100644 --- a/trunk/drivers/serial/8250.c +++ b/trunk/drivers/serial/8250.c @@ -2839,8 +2839,6 @@ int __init early_serial_setup(struct uart_port *port) p->flags = port->flags; p->mapbase = port->mapbase; p->private_data = port->private_data; - p->type = port->type; - p->line = port->line; set_io_from_upio(p); if (port->serial_in) diff --git a/trunk/drivers/serial/jsm/jsm_neo.c b/trunk/drivers/serial/jsm/jsm_neo.c index e6390d023634..b7584ca55ade 100644 --- a/trunk/drivers/serial/jsm/jsm_neo.c +++ b/trunk/drivers/serial/jsm/jsm_neo.c @@ -577,6 +577,9 @@ static void neo_parse_modem(struct jsm_channel *ch, u8 signals) jsm_printk(MSIGS, INFO, &ch->ch_bd->pci_dev, "neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals); + if (!ch) + return; + /* Scrub off lower bits. They signify delta's, which I don't care about */ /* Keep DDCD and DDSR though */ msignals &= 0xf8; diff --git a/trunk/drivers/usb/serial/ti_usb_3410_5052.c b/trunk/drivers/usb/serial/ti_usb_3410_5052.c index 3cf41df302d7..01d0c70d60e9 100644 --- a/trunk/drivers/usb/serial/ti_usb_3410_5052.c +++ b/trunk/drivers/usb/serial/ti_usb_3410_5052.c @@ -145,7 +145,7 @@ static int ti_command_in_sync(struct ti_device *tdev, __u8 command, static int ti_write_byte(struct ti_device *tdev, unsigned long addr, __u8 mask, __u8 byte); -static int ti_download_firmware(struct ti_device *tdev); +static int ti_download_firmware(struct ti_device *tdev, int type); /* circular buffer */ static struct circ_buf *ti_buf_alloc(void); @@ -176,14 +176,9 @@ static unsigned int product_5052_count; /* the array dimension is the number of default entries plus */ /* TI_EXTRA_VID_PID_COUNT user defined entries plus 1 terminating */ /* null entry */ -static struct usb_device_id ti_id_table_3410[7+TI_EXTRA_VID_PID_COUNT+1] = { +static struct usb_device_id ti_id_table_3410[1+TI_EXTRA_VID_PID_COUNT+1] = { { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_NO_FW_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_NO_FW_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_EDGE_PRODUCT_ID) }, }; static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { @@ -193,14 +188,9 @@ static struct usb_device_id ti_id_table_5052[4+TI_EXTRA_VID_PID_COUNT+1] = { { USB_DEVICE(TI_VENDOR_ID, TI_5052_FIRMWARE_PRODUCT_ID) }, }; -static struct usb_device_id ti_id_table_combined[6+2*TI_EXTRA_VID_PID_COUNT+1] = { +static struct usb_device_id ti_id_table_combined[] = { { USB_DEVICE(TI_VENDOR_ID, TI_3410_PRODUCT_ID) }, { USB_DEVICE(TI_VENDOR_ID, TI_3410_EZ430_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_NO_FW_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_NO_FW_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_CDMA_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_GSM_PRODUCT_ID) }, - { USB_DEVICE(MTS_VENDOR_ID, MTS_EDGE_PRODUCT_ID) }, { USB_DEVICE(TI_VENDOR_ID, TI_5052_BOOT_PRODUCT_ID) }, { USB_DEVICE(TI_VENDOR_ID, TI_5152_BOOT_PRODUCT_ID) }, { USB_DEVICE(TI_VENDOR_ID, TI_5052_EEPROM_PRODUCT_ID) }, @@ -282,9 +272,6 @@ MODULE_LICENSE("GPL"); MODULE_FIRMWARE("ti_3410.fw"); MODULE_FIRMWARE("ti_5052.fw"); -MODULE_FIRMWARE("mts_cdma.fw"); -MODULE_FIRMWARE("mts_gsm.fw"); -MODULE_FIRMWARE("mts_edge.fw"); module_param(debug, bool, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Enable debugging, 0=no, 1=yes"); @@ -317,28 +304,21 @@ MODULE_DEVICE_TABLE(usb, ti_id_table_combined); static int __init ti_init(void) { - int i, j, c; + int i, j; int ret; /* insert extra vendor and product ids */ - c = ARRAY_SIZE(ti_id_table_combined) - 2 * TI_EXTRA_VID_PID_COUNT - 1; j = ARRAY_SIZE(ti_id_table_3410) - TI_EXTRA_VID_PID_COUNT - 1; - for (i = 0; i < min(vendor_3410_count, product_3410_count); i++, j++, c++) { + for (i = 0; i < min(vendor_3410_count, product_3410_count); i++, j++) { ti_id_table_3410[j].idVendor = vendor_3410[i]; ti_id_table_3410[j].idProduct = product_3410[i]; ti_id_table_3410[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; - ti_id_table_combined[c].idVendor = vendor_3410[i]; - ti_id_table_combined[c].idProduct = product_3410[i]; - ti_id_table_combined[c].match_flags = USB_DEVICE_ID_MATCH_DEVICE; } j = ARRAY_SIZE(ti_id_table_5052) - TI_EXTRA_VID_PID_COUNT - 1; - for (i = 0; i < min(vendor_5052_count, product_5052_count); i++, j++, c++) { + for (i = 0; i < min(vendor_5052_count, product_5052_count); i++, j++) { ti_id_table_5052[j].idVendor = vendor_5052[i]; ti_id_table_5052[j].idProduct = product_5052[i]; ti_id_table_5052[j].match_flags = USB_DEVICE_ID_MATCH_DEVICE; - ti_id_table_combined[c].idVendor = vendor_5052[i]; - ti_id_table_combined[c].idProduct = product_5052[i]; - ti_id_table_combined[c].match_flags = USB_DEVICE_ID_MATCH_DEVICE; } ret = usb_serial_register(&ti_1port_device); @@ -410,7 +390,11 @@ static int ti_startup(struct usb_serial *serial) /* if we have only 1 configuration, download firmware */ if (dev->descriptor.bNumConfigurations == 1) { - if ((status = ti_download_firmware(tdev)) != 0) + if (tdev->td_is_3410) + status = ti_download_firmware(tdev, 3410); + else + status = ti_download_firmware(tdev, 5052); + if (status) goto free_tdev; /* 3410 must be reset, 5052 resets itself */ @@ -1687,9 +1671,9 @@ static int ti_do_download(struct usb_device *dev, int pipe, return status; } -static int ti_download_firmware(struct ti_device *tdev) +static int ti_download_firmware(struct ti_device *tdev, int type) { - int status; + int status = -ENOMEM; int buffer_size; __u8 *buffer; struct usb_device *dev = tdev->td_serial->dev; @@ -1697,34 +1681,9 @@ static int ti_download_firmware(struct ti_device *tdev) tdev->td_serial->port[0]->bulk_out_endpointAddress); const struct firmware *fw_p; char buf[32]; + sprintf(buf, "ti_usb-%d.bin", type); - /* try ID specific firmware first, then try generic firmware */ - sprintf(buf, "ti_usb-v%04x-p%04x.fw", dev->descriptor.idVendor, - dev->descriptor.idProduct); - if ((status = request_firmware(&fw_p, buf, &dev->dev)) != 0) { - buf[0] = '\0'; - if (dev->descriptor.idVendor == MTS_VENDOR_ID) { - switch (dev->descriptor.idProduct) { - case MTS_CDMA_PRODUCT_ID: - strcpy(buf, "mts_cdma.fw"); - break; - case MTS_GSM_PRODUCT_ID: - strcpy(buf, "mts_gsm.fw"); - break; - case MTS_EDGE_PRODUCT_ID: - strcpy(buf, "mts_edge.fw"); - break; - } - } - if (buf[0] == '\0') { - if (tdev->td_is_3410) - strcpy(buf, "ti_3410.fw"); - else - strcpy(buf, "ti_5052.fw"); - } - status = request_firmware(&fw_p, buf, &dev->dev); - } - if (status) { + if (request_firmware(&fw_p, buf, &dev->dev)) { dev_err(&dev->dev, "%s - firmware not found\n", __func__); return -ENOENT; } @@ -1740,8 +1699,6 @@ static int ti_download_firmware(struct ti_device *tdev) memset(buffer + fw_p->size, 0xff, buffer_size - fw_p->size); status = ti_do_download(dev, pipe, buffer, fw_p->size); kfree(buffer); - } else { - status = -ENOMEM; } release_firmware(fw_p); if (status) { diff --git a/trunk/drivers/usb/serial/ti_usb_3410_5052.h b/trunk/drivers/usb/serial/ti_usb_3410_5052.h index 7e4752fbf232..b5541bf991ba 100644 --- a/trunk/drivers/usb/serial/ti_usb_3410_5052.h +++ b/trunk/drivers/usb/serial/ti_usb_3410_5052.h @@ -34,14 +34,6 @@ #define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ #define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ -/* Multi-Tech vendor and product ids */ -#define MTS_VENDOR_ID 0x06E0 -#define MTS_GSM_NO_FW_PRODUCT_ID 0xF108 -#define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109 -#define MTS_CDMA_PRODUCT_ID 0xF110 -#define MTS_GSM_PRODUCT_ID 0xF111 -#define MTS_EDGE_PRODUCT_ID 0xF112 - /* Commands */ #define TI_GET_VERSION 0x01 #define TI_GET_PORT_STATUS 0x02 diff --git a/trunk/drivers/usb/serial/usb-serial.c b/trunk/drivers/usb/serial/usb-serial.c index cfcfd5ab06ce..080ade223d53 100644 --- a/trunk/drivers/usb/serial/usb-serial.c +++ b/trunk/drivers/usb/serial/usb-serial.c @@ -511,6 +511,9 @@ static void usb_serial_port_work(struct work_struct *work) dbg("%s - port %d", __func__, port->number); + if (!port) + return; + tty = tty_port_tty_get(&port->port); if (!tty) return; diff --git a/trunk/drivers/video/Makefile b/trunk/drivers/video/Makefile index be2b657546ef..e39e33e797da 100644 --- a/trunk/drivers/video/Makefile +++ b/trunk/drivers/video/Makefile @@ -28,7 +28,7 @@ obj-$(CONFIG_FB_DDC) += fb_ddc.o obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o # Hardware specific drivers go first -obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o +obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o obj-$(CONFIG_FB_ARC) += arcfb.o obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o @@ -72,7 +72,7 @@ obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o obj-$(CONFIG_FB_SGIVW) += sgivwfb.o obj-$(CONFIG_FB_ACORN) += acornfb.o -obj-$(CONFIG_FB_ATARI) += atafb.o c2p_iplan2.o atafb_mfb.o \ +obj-$(CONFIG_FB_ATARI) += atafb.o c2p.o atafb_mfb.o \ atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o obj-$(CONFIG_FB_MAC) += macfb.o obj-$(CONFIG_FB_HECUBA) += hecubafb.o diff --git a/trunk/drivers/video/amifb.c b/trunk/drivers/video/amifb.c index 100f23661465..b8e9a8682f2d 100644 --- a/trunk/drivers/video/amifb.c +++ b/trunk/drivers/video/amifb.c @@ -2159,9 +2159,9 @@ static void amifb_imageblit(struct fb_info *info, const struct fb_image *image) src += pitch; } } else { - c2p_planar(info->screen_base, image->data, dx, dy, width, - height, par->next_line, par->next_plane, - image->width, info->var.bits_per_pixel); + c2p(info->screen_base, image->data, dx, dy, width, height, + par->next_line, par->next_plane, image->width, + info->var.bits_per_pixel); } } diff --git a/trunk/drivers/video/atafb.c b/trunk/drivers/video/atafb.c index 8058572a7428..77eb8b34fbfa 100644 --- a/trunk/drivers/video/atafb.c +++ b/trunk/drivers/video/atafb.c @@ -122,6 +122,7 @@ static struct atafb_par { void *screen_base; int yres_virtual; u_long next_line; + u_long next_plane; #if defined ATAFB_TT || defined ATAFB_STE union { struct { @@ -148,7 +149,6 @@ static struct atafb_par { short mono; short ste_mode; short bpp; - u32 pseudo_palette[16]; } falcon; #endif /* Nothing needed for external mode */ @@ -614,7 +614,7 @@ static int tt_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) fix->xpanstep = 0; fix->ypanstep = 1; fix->ywrapstep = 0; - fix->line_length = par->next_line; + fix->line_length = 0; fix->accel = FB_ACCEL_ATARIBLITT; return 0; } @@ -691,7 +691,6 @@ static int tt_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par) return -EINVAL; par->yres_virtual = yres_virtual; par->screen_base = screen_base + var->yoffset * linelen; - par->next_line = linelen; return 0; } @@ -885,6 +884,10 @@ static int vdl_prescale[4][3] = { /* Default hsync timing [mon_type] in picoseconds */ static long h_syncs[4] = { 3000000, 4875000, 4000000, 4875000 }; +#ifdef FBCON_HAS_CFB16 +static u16 fbcon_cfb16_cmap[16]; +#endif + static inline int hxx_prescale(struct falcon_hw *hw) { return hw->ste_mode ? 16 @@ -915,7 +918,7 @@ static int falcon_encode_fix(struct fb_fix_screeninfo *fix, fix->visual = FB_VISUAL_TRUECOLOR; fix->xpanstep = 2; } - fix->line_length = par->next_line; + fix->line_length = 0; fix->accel = FB_ACCEL_ATARIBLITT; return 0; } @@ -1391,7 +1394,14 @@ static int falcon_decode_var(struct fb_var_screeninfo *var, par->screen_base = screen_base + var->yoffset * linelen; par->hw.falcon.xoffset = 0; + // FIXME!!! sort of works, no crash + //par->next_line = linelen; + //par->next_plane = yres_virtual * linelen; par->next_line = linelen; + par->next_plane = 2; + // crashes + //par->next_plane = linelen; + //par->next_line = yres_virtual * linelen; return 0; } @@ -1725,10 +1735,10 @@ static int falcon_setcolreg(unsigned int regno, unsigned int red, (((red & 0xe000) >> 13) | ((red & 0x1000) >> 12) << 8) | (((green & 0xe000) >> 13) | ((green & 0x1000) >> 12) << 4) | ((blue & 0xe000) >> 13) | ((blue & 0x1000) >> 12); -#ifdef ATAFB_FALCON - ((u32 *)info->pseudo_palette)[regno] = ((red & 0xf800) | - ((green & 0xfc00) >> 5) | - ((blue & 0xf800) >> 11)); +#ifdef FBCON_HAS_CFB16 + fbcon_cfb16_cmap[regno] = ((red & 0xf800) | + ((green & 0xfc00) >> 5) | + ((blue & 0xf800) >> 11)); #endif } return 0; @@ -1842,7 +1852,7 @@ static int stste_encode_fix(struct fb_fix_screeninfo *fix, fix->ypanstep = 0; } fix->ywrapstep = 0; - fix->line_length = par->next_line; + fix->line_length = 0; fix->accel = FB_ACCEL_ATARIBLITT; return 0; } @@ -1900,7 +1910,6 @@ static int stste_decode_var(struct fb_var_screeninfo *var, return -EINVAL; par->yres_virtual = yres_virtual; par->screen_base = screen_base + var->yoffset * linelen; - par->next_line = linelen; return 0; } @@ -2160,7 +2169,7 @@ static int ext_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par) fix->xpanstep = 0; fix->ypanstep = 0; fix->ywrapstep = 0; - fix->line_length = par->next_line; + fix->line_length = 0; return 0; } @@ -2175,8 +2184,6 @@ static int ext_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par) var->xoffset > 0 || var->yoffset > 0) return -EINVAL; - - par->next_line = external_xres_virtual * external_depth / 8; return 0; } @@ -2436,6 +2443,42 @@ static void atafb_set_disp(struct fb_info *info) atafb_get_fix(&info->fix, info); info->screen_base = (void *)info->fix.smem_start; + + switch (info->fix.type) { + case FB_TYPE_INTERLEAVED_PLANES: + switch (info->var.bits_per_pixel) { + case 2: + // display->dispsw = &fbcon_iplan2p2; + break; + case 4: + // display->dispsw = &fbcon_iplan2p4; + break; + case 8: + // display->dispsw = &fbcon_iplan2p8; + break; + } + break; + case FB_TYPE_PACKED_PIXELS: + switch (info->var.bits_per_pixel) { +#ifdef FBCON_HAS_MFB + case 1: + // display->dispsw = &fbcon_mfb; + break; +#endif +#ifdef FBCON_HAS_CFB8 + case 8: + // display->dispsw = &fbcon_cfb8; + break; +#endif +#ifdef FBCON_HAS_CFB16 + case 16: + // display->dispsw = &fbcon_cfb16; + // display->dispsw_data = fbcon_cfb16_cmap; + break; +#endif + } + break; + } } static int atafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, @@ -2506,13 +2549,6 @@ static void atafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) if (!rect->width || !rect->height) return; -#ifdef ATAFB_FALCON - if (info->var.bits_per_pixel == 16) { - cfb_fillrect(info, rect); - return; - } -#endif - /* * We could use hardware clipping but on many cards you get around * hardware clipping by writing to framebuffer directly. @@ -2547,13 +2583,6 @@ static void atafb_copyarea(struct fb_info *info, const struct fb_copyarea *area) u32 dx, dy, sx, sy, width, height; int rev_copy = 0; -#ifdef ATAFB_FALCON - if (info->var.bits_per_pixel == 16) { - cfb_copyarea(info, area); - return; - } -#endif - /* clip the destination */ x2 = area->dx + area->width; y2 = area->dy + area->height; @@ -2603,13 +2632,6 @@ static void atafb_imageblit(struct fb_info *info, const struct fb_image *image) const char *src; u32 dx, dy, width, height, pitch; -#ifdef ATAFB_FALCON - if (info->var.bits_per_pixel == 16) { - cfb_imageblit(info, image); - return; - } -#endif - /* * We could use hardware clipping but on many cards you get around * hardware clipping by writing to framebuffer directly like we are @@ -2654,9 +2676,10 @@ static void atafb_imageblit(struct fb_info *info, const struct fb_image *image) src += pitch; } } else { - c2p_iplan2(info->screen_base, image->data, dx, dy, width, - height, par->next_line, image->width, - info->var.bits_per_pixel); + // only used for logo; broken + c2p(info->screen_base, image->data, dx, dy, width, height, + par->next_line, par->next_plane, image->width, + info->var.bits_per_pixel); } } @@ -3075,7 +3098,8 @@ int __init atafb_setup(char *options) int __init atafb_init(void) { - int pad, detected_mode, error; + int pad; + int detected_mode; unsigned int defmode = 0; unsigned long mem_req; @@ -3115,12 +3139,8 @@ int __init atafb_init(void) printk("atafb_init: initializing Falcon hw\n"); fbhw = &falcon_switch; atafb_ops.fb_setcolreg = &falcon_setcolreg; - error = request_irq(IRQ_AUTO_4, falcon_vbl_switcher, - IRQ_TYPE_PRIO, - "framebuffer/modeswitch", - falcon_vbl_switcher); - if (error) - return error; + request_irq(IRQ_AUTO_4, falcon_vbl_switcher, IRQ_TYPE_PRIO, + "framebuffer/modeswitch", falcon_vbl_switcher); defmode = DEFMODE_F30; break; } @@ -3205,10 +3225,6 @@ int __init atafb_init(void) // tries to read from HW which may not be initialized yet // so set sane var first, then call atafb_set_par atafb_get_var(&fb_info.var, &fb_info); - -#ifdef ATAFB_FALCON - fb_info.pseudo_palette = current_par.hw.falcon.pseudo_palette; -#endif fb_info.flags = FBINFO_FLAG_DEFAULT; if (!fb_find_mode(&fb_info.var, &fb_info, mode_option, atafb_modedb, diff --git a/trunk/drivers/video/c2p.c b/trunk/drivers/video/c2p.c new file mode 100644 index 000000000000..376bc07ff952 --- /dev/null +++ b/trunk/drivers/video/c2p.c @@ -0,0 +1,232 @@ +/* + * Fast C2P (Chunky-to-Planar) Conversion + * + * Copyright (C) 2003 Geert Uytterhoeven + * + * NOTES: + * - This code was inspired by Scout's C2P tutorial + * - It assumes to run on a big endian system + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include "c2p.h" + + + /* + * Basic transpose step + */ + +#define _transp(d, i1, i2, shift, mask) \ + do { \ + u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; \ + d[i1] ^= t; \ + d[i2] ^= t << shift; \ + } while (0) + +static inline u32 get_mask(int n) +{ + switch (n) { + case 1: + return 0x55555555; + break; + + case 2: + return 0x33333333; + break; + + case 4: + return 0x0f0f0f0f; + break; + + case 8: + return 0x00ff00ff; + break; + + case 16: + return 0x0000ffff; + break; + } + return 0; +} + +#define transp_nx1(d, n) \ + do { \ + u32 mask = get_mask(n); \ + /* First block */ \ + _transp(d, 0, 1, n, mask); \ + /* Second block */ \ + _transp(d, 2, 3, n, mask); \ + /* Third block */ \ + _transp(d, 4, 5, n, mask); \ + /* Fourth block */ \ + _transp(d, 6, 7, n, mask); \ + } while (0) + +#define transp_nx2(d, n) \ + do { \ + u32 mask = get_mask(n); \ + /* First block */ \ + _transp(d, 0, 2, n, mask); \ + _transp(d, 1, 3, n, mask); \ + /* Second block */ \ + _transp(d, 4, 6, n, mask); \ + _transp(d, 5, 7, n, mask); \ + } while (0) + +#define transp_nx4(d, n) \ + do { \ + u32 mask = get_mask(n); \ + _transp(d, 0, 4, n, mask); \ + _transp(d, 1, 5, n, mask); \ + _transp(d, 2, 6, n, mask); \ + _transp(d, 3, 7, n, mask); \ + } while (0) + +#define transp(d, n, m) transp_nx ## m(d, n) + + + /* + * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words + * containing + * - 32 8-bit chunky pixels on input + * - permuted planar data on output + */ + +static void c2p_8bpp(u32 d[8]) +{ + transp(d, 16, 4); + transp(d, 8, 2); + transp(d, 4, 1); + transp(d, 2, 4); + transp(d, 1, 2); +} + + + /* + * Array containing the permution indices of the planar data after c2p + */ + +static const int perm_c2p_8bpp[8] = { 7, 5, 3, 1, 6, 4, 2, 0 }; + + + /* + * Compose two values, using a bitmask as decision value + * This is equivalent to (a & mask) | (b & ~mask) + */ + +static inline unsigned long comp(unsigned long a, unsigned long b, + unsigned long mask) +{ + return ((a ^ b) & mask) ^ b; +} + + + /* + * Store a full block of planar data after c2p conversion + */ + +static inline void store_planar(char *dst, u32 dst_inc, u32 bpp, u32 d[8]) +{ + int i; + + for (i = 0; i < bpp; i++, dst += dst_inc) + *(u32 *)dst = d[perm_c2p_8bpp[i]]; +} + + + /* + * Store a partial block of planar data after c2p conversion + */ + +static inline void store_planar_masked(char *dst, u32 dst_inc, u32 bpp, + u32 d[8], u32 mask) +{ + int i; + + for (i = 0; i < bpp; i++, dst += dst_inc) + *(u32 *)dst = comp(d[perm_c2p_8bpp[i]], *(u32 *)dst, mask); +} + + + /* + * c2p - Copy 8-bit chunky image data to a planar frame buffer + * @dst: Starting address of the planar frame buffer + * @dx: Horizontal destination offset (in pixels) + * @dy: Vertical destination offset (in pixels) + * @width: Image width (in pixels) + * @height: Image height (in pixels) + * @dst_nextline: Frame buffer offset to the next line (in bytes) + * @dst_nextplane: Frame buffer offset to the next plane (in bytes) + * @src_nextline: Image offset to the next line (in bytes) + * @bpp: Bits per pixel of the planar frame buffer (1-8) + */ + +void c2p(u8 *dst, const u8 *src, u32 dx, u32 dy, u32 width, u32 height, + u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, u32 bpp) +{ + int dst_idx; + u32 d[8], first, last, w; + const u8 *c; + u8 *p; + + dst += dy*dst_nextline+(dx & ~31); + dst_idx = dx % 32; + first = ~0UL >> dst_idx; + last = ~(~0UL >> ((dst_idx+width) % 32)); + while (height--) { + c = src; + p = dst; + w = width; + if (dst_idx+width <= 32) { + /* Single destination word */ + first &= last; + memset(d, 0, sizeof(d)); + memcpy((u8 *)d+dst_idx, c, width); + c += width; + c2p_8bpp(d); + store_planar_masked(p, dst_nextplane, bpp, d, first); + p += 4; + } else { + /* Multiple destination words */ + w = width; + /* Leading bits */ + if (dst_idx) { + w = 32 - dst_idx; + memset(d, 0, dst_idx); + memcpy((u8 *)d+dst_idx, c, w); + c += w; + c2p_8bpp(d); + store_planar_masked(p, dst_nextplane, bpp, d, first); + p += 4; + w = width-w; + } + /* Main chunk */ + while (w >= 32) { + memcpy(d, c, 32); + c += 32; + c2p_8bpp(d); + store_planar(p, dst_nextplane, bpp, d); + p += 4; + w -= 32; + } + /* Trailing bits */ + w %= 32; + if (w > 0) { + memcpy(d, c, w); + memset((u8 *)d+w, 0, 32-w); + c2p_8bpp(d); + store_planar_masked(p, dst_nextplane, bpp, d, last); + } + } + src += src_nextline; + dst += dst_nextline; + } +} +EXPORT_SYMBOL_GPL(c2p); + +MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/video/c2p.h b/trunk/drivers/video/c2p.h index 6c38d40427d8..c77cbf17e043 100644 --- a/trunk/drivers/video/c2p.h +++ b/trunk/drivers/video/c2p.h @@ -1,7 +1,7 @@ /* * Fast C2P (Chunky-to-Planar) Conversion * - * Copyright (C) 2003-2008 Geert Uytterhoeven + * Copyright (C) 2003 Geert Uytterhoeven * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive @@ -10,10 +10,7 @@ #include -extern void c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, - u32 height, u32 dst_nextline, u32 dst_nextplane, - u32 src_nextline, u32 bpp); +extern void c2p(u8 *dst, const u8 *src, u32 dx, u32 dy, u32 width, u32 height, + u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, + u32 bpp); -extern void c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, - u32 height, u32 dst_nextline, u32 src_nextline, - u32 bpp); diff --git a/trunk/drivers/video/c2p_core.h b/trunk/drivers/video/c2p_core.h deleted file mode 100644 index e1035a865fb9..000000000000 --- a/trunk/drivers/video/c2p_core.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Fast C2P (Chunky-to-Planar) Conversion - * - * Copyright (C) 2003-2008 Geert Uytterhoeven - * - * NOTES: - * - This code was inspired by Scout's C2P tutorial - * - It assumes to run on a big endian system - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - - - /* - * Basic transpose step - */ - -static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, - unsigned int shift, u32 mask) -{ - u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; - - d[i1] ^= t; - d[i2] ^= t << shift; -} - - -extern void c2p_unsupported(void); - -static inline u32 get_mask(unsigned int n) -{ - switch (n) { - case 1: - return 0x55555555; - - case 2: - return 0x33333333; - - case 4: - return 0x0f0f0f0f; - - case 8: - return 0x00ff00ff; - - case 16: - return 0x0000ffff; - } - - c2p_unsupported(); - return 0; -} - - - /* - * Transpose operations on 8 32-bit words - */ - -static inline void transp8(u32 d[], unsigned int n, unsigned int m) -{ - u32 mask = get_mask(n); - - switch (m) { - case 1: - /* First n x 1 block */ - _transp(d, 0, 1, n, mask); - /* Second n x 1 block */ - _transp(d, 2, 3, n, mask); - /* Third n x 1 block */ - _transp(d, 4, 5, n, mask); - /* Fourth n x 1 block */ - _transp(d, 6, 7, n, mask); - return; - - case 2: - /* First n x 2 block */ - _transp(d, 0, 2, n, mask); - _transp(d, 1, 3, n, mask); - /* Second n x 2 block */ - _transp(d, 4, 6, n, mask); - _transp(d, 5, 7, n, mask); - return; - - case 4: - /* Single n x 4 block */ - _transp(d, 0, 4, n, mask); - _transp(d, 1, 5, n, mask); - _transp(d, 2, 6, n, mask); - _transp(d, 3, 7, n, mask); - return; - } - - c2p_unsupported(); -} - - - /* - * Transpose operations on 4 32-bit words - */ - -static inline void transp4(u32 d[], unsigned int n, unsigned int m) -{ - u32 mask = get_mask(n); - - switch (m) { - case 1: - /* First n x 1 block */ - _transp(d, 0, 1, n, mask); - /* Second n x 1 block */ - _transp(d, 2, 3, n, mask); - return; - - case 2: - /* Single n x 2 block */ - _transp(d, 0, 2, n, mask); - _transp(d, 1, 3, n, mask); - return; - } - - c2p_unsupported(); -} - - - /* - * Transpose operations on 4 32-bit words (reverse order) - */ - -static inline void transp4x(u32 d[], unsigned int n, unsigned int m) -{ - u32 mask = get_mask(n); - - switch (m) { - case 2: - /* Single n x 2 block */ - _transp(d, 2, 0, n, mask); - _transp(d, 3, 1, n, mask); - return; - } - - c2p_unsupported(); -} - - - /* - * Compose two values, using a bitmask as decision value - * This is equivalent to (a & mask) | (b & ~mask) - */ - -static inline u32 comp(u32 a, u32 b, u32 mask) -{ - return ((a ^ b) & mask) ^ b; -} diff --git a/trunk/drivers/video/c2p_iplan2.c b/trunk/drivers/video/c2p_iplan2.c deleted file mode 100644 index 19156dc6158c..000000000000 --- a/trunk/drivers/video/c2p_iplan2.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Fast C2P (Chunky-to-Planar) Conversion - * - * Copyright (C) 2003-2008 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include - -#include - -#include "c2p.h" -#include "c2p_core.h" - - - /* - * Perform a full C2P step on 16 8-bit pixels, stored in 4 32-bit words - * containing - * - 16 8-bit chunky pixels on input - * - permutated planar data (2 planes per 32-bit word) on output - */ - -static void c2p_16x8(u32 d[4]) -{ - transp4(d, 8, 2); - transp4(d, 1, 2); - transp4x(d, 16, 2); - transp4x(d, 2, 2); - transp4(d, 4, 1); -} - - - /* - * Array containing the permutation indices of the planar data after c2p - */ - -static const int perm_c2p_16x8[4] = { 1, 3, 0, 2 }; - - - /* - * Store a full block of iplan2 data after c2p conversion - */ - -static inline void store_iplan2(void *dst, u32 bpp, u32 d[4]) -{ - int i; - - for (i = 0; i < bpp/2; i++, dst += 4) - put_unaligned_be32(d[perm_c2p_16x8[i]], dst); -} - - - /* - * Store a partial block of iplan2 data after c2p conversion - */ - -static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask) -{ - int i; - - for (i = 0; i < bpp/2; i++, dst += 4) - put_unaligned_be32(comp(d[perm_c2p_16x8[i]], - get_unaligned_be32(dst), mask), - dst); -} - - - /* - * c2p_iplan2 - Copy 8-bit chunky image data to an interleaved planar - * frame buffer with 2 bytes of interleave - * @dst: Starting address of the planar frame buffer - * @dx: Horizontal destination offset (in pixels) - * @dy: Vertical destination offset (in pixels) - * @width: Image width (in pixels) - * @height: Image height (in pixels) - * @dst_nextline: Frame buffer offset to the next line (in bytes) - * @src_nextline: Image offset to the next line (in bytes) - * @bpp: Bits per pixel of the planar frame buffer (2, 4, or 8) - */ - -void c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, - u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp) -{ - union { - u8 pixels[16]; - u32 words[4]; - } d; - u32 dst_idx, first, last, w; - const u8 *c; - void *p; - - dst += dy*dst_nextline+(dx & ~15)*bpp; - dst_idx = dx % 16; - first = 0xffffU >> dst_idx; - first |= first << 16; - last = 0xffffU ^ (0xffffU >> ((dst_idx+width) % 16)); - last |= last << 16; - while (height--) { - c = src; - p = dst; - w = width; - if (dst_idx+width <= 16) { - /* Single destination word */ - first &= last; - memset(d.pixels, 0, sizeof(d)); - memcpy(d.pixels+dst_idx, c, width); - c += width; - c2p_16x8(d.words); - store_iplan2_masked(p, bpp, d.words, first); - p += bpp*2; - } else { - /* Multiple destination words */ - w = width; - /* Leading bits */ - if (dst_idx) { - w = 16 - dst_idx; - memset(d.pixels, 0, dst_idx); - memcpy(d.pixels+dst_idx, c, w); - c += w; - c2p_16x8(d.words); - store_iplan2_masked(p, bpp, d.words, first); - p += bpp*2; - w = width-w; - } - /* Main chunk */ - while (w >= 16) { - memcpy(d.pixels, c, 16); - c += 16; - c2p_16x8(d.words); - store_iplan2(p, bpp, d.words); - p += bpp*2; - w -= 16; - } - /* Trailing bits */ - w %= 16; - if (w > 0) { - memcpy(d.pixels, c, w); - memset(d.pixels+w, 0, 16-w); - c2p_16x8(d.words); - store_iplan2_masked(p, bpp, d.words, last); - } - } - src += src_nextline; - dst += dst_nextline; - } -} -EXPORT_SYMBOL_GPL(c2p_iplan2); - -MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/video/c2p_planar.c b/trunk/drivers/video/c2p_planar.c deleted file mode 100644 index ec7ac8526f06..000000000000 --- a/trunk/drivers/video/c2p_planar.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Fast C2P (Chunky-to-Planar) Conversion - * - * Copyright (C) 2003-2008 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include - -#include - -#include "c2p.h" -#include "c2p_core.h" - - - /* - * Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words - * containing - * - 32 8-bit chunky pixels on input - * - permutated planar data (1 plane per 32-bit word) on output - */ - -static void c2p_32x8(u32 d[8]) -{ - transp8(d, 16, 4); - transp8(d, 8, 2); - transp8(d, 4, 1); - transp8(d, 2, 4); - transp8(d, 1, 2); -} - - - /* - * Array containing the permutation indices of the planar data after c2p - */ - -static const int perm_c2p_32x8[8] = { 7, 5, 3, 1, 6, 4, 2, 0 }; - - - /* - * Store a full block of planar data after c2p conversion - */ - -static inline void store_planar(void *dst, u32 dst_inc, u32 bpp, u32 d[8]) -{ - int i; - - for (i = 0; i < bpp; i++, dst += dst_inc) - put_unaligned_be32(d[perm_c2p_32x8[i]], dst); -} - - - /* - * Store a partial block of planar data after c2p conversion - */ - -static inline void store_planar_masked(void *dst, u32 dst_inc, u32 bpp, - u32 d[8], u32 mask) -{ - int i; - - for (i = 0; i < bpp; i++, dst += dst_inc) - put_unaligned_be32(comp(d[perm_c2p_32x8[i]], - get_unaligned_be32(dst), mask), - dst); -} - - - /* - * c2p_planar - Copy 8-bit chunky image data to a planar frame buffer - * @dst: Starting address of the planar frame buffer - * @dx: Horizontal destination offset (in pixels) - * @dy: Vertical destination offset (in pixels) - * @width: Image width (in pixels) - * @height: Image height (in pixels) - * @dst_nextline: Frame buffer offset to the next line (in bytes) - * @dst_nextplane: Frame buffer offset to the next plane (in bytes) - * @src_nextline: Image offset to the next line (in bytes) - * @bpp: Bits per pixel of the planar frame buffer (1-8) - */ - -void c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, - u32 height, u32 dst_nextline, u32 dst_nextplane, - u32 src_nextline, u32 bpp) -{ - union { - u8 pixels[32]; - u32 words[8]; - } d; - u32 dst_idx, first, last, w; - const u8 *c; - void *p; - - dst += dy*dst_nextline+(dx & ~31); - dst_idx = dx % 32; - first = 0xffffffffU >> dst_idx; - last = ~(0xffffffffU >> ((dst_idx+width) % 32)); - while (height--) { - c = src; - p = dst; - w = width; - if (dst_idx+width <= 32) { - /* Single destination word */ - first &= last; - memset(d.pixels, 0, sizeof(d)); - memcpy(d.pixels+dst_idx, c, width); - c += width; - c2p_32x8(d.words); - store_planar_masked(p, dst_nextplane, bpp, d.words, - first); - p += 4; - } else { - /* Multiple destination words */ - w = width; - /* Leading bits */ - if (dst_idx) { - w = 32 - dst_idx; - memset(d.pixels, 0, dst_idx); - memcpy(d.pixels+dst_idx, c, w); - c += w; - c2p_32x8(d.words); - store_planar_masked(p, dst_nextplane, bpp, - d.words, first); - p += 4; - w = width-w; - } - /* Main chunk */ - while (w >= 32) { - memcpy(d.pixels, c, 32); - c += 32; - c2p_32x8(d.words); - store_planar(p, dst_nextplane, bpp, d.words); - p += 4; - w -= 32; - } - /* Trailing bits */ - w %= 32; - if (w > 0) { - memcpy(d.pixels, c, w); - memset(d.pixels+w, 0, 32-w); - c2p_32x8(d.words); - store_planar_masked(p, dst_nextplane, bpp, - d.words, last); - } - } - src += src_nextline; - dst += dst_nextline; - } -} -EXPORT_SYMBOL_GPL(c2p_planar); - -MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/video/console/fbcon.c b/trunk/drivers/video/console/fbcon.c index 1657b9608b04..4bcff81b50e0 100644 --- a/trunk/drivers/video/console/fbcon.c +++ b/trunk/drivers/video/console/fbcon.c @@ -78,6 +78,13 @@ #include #include #include +#ifdef CONFIG_ATARI +#include +#endif +#if defined(__mc68000__) +#include +#include +#endif #include "fbcon.h" @@ -148,6 +155,9 @@ static int fbcon_set_origin(struct vc_data *); #define CURSOR_DRAW_DELAY (1) +/* # VBL ints between cursor state changes */ +#define ATARI_CURSOR_BLINK_RATE (42) + static int vbl_cursor_cnt; static int fbcon_cursor_noblink; @@ -393,6 +403,20 @@ static void fb_flashcursor(struct work_struct *work) release_console_sem(); } +#ifdef CONFIG_ATARI +static int cursor_blink_rate; +static irqreturn_t fb_vbl_handler(int irq, void *dev_id) +{ + struct fb_info *info = dev_id; + + if (vbl_cursor_cnt && --vbl_cursor_cnt == 0) { + schedule_work(&info->queue); + vbl_cursor_cnt = cursor_blink_rate; + } + return IRQ_HANDLED; +} +#endif + static void cursor_timer_handler(unsigned long dev_addr) { struct fb_info *info = (struct fb_info *) dev_addr; @@ -993,6 +1017,15 @@ static const char *fbcon_startup(void) info->var.yres, info->var.bits_per_pixel); +#ifdef CONFIG_ATARI + if (MACH_IS_ATARI) { + cursor_blink_rate = ATARI_CURSOR_BLINK_RATE; + (void)request_irq(IRQ_AUTO_4, fb_vbl_handler, + IRQ_TYPE_PRIO, "framebuffer vbl", + info); + } +#endif /* CONFIG_ATARI */ + fbcon_add_cursor_timer(info); fbcon_has_exited = 0; return display_desc; @@ -3421,6 +3454,11 @@ static void fbcon_exit(void) if (fbcon_has_exited) return; +#ifdef CONFIG_ATARI + if (MACH_IS_ATARI) + free_irq(IRQ_AUTO_4, fb_vbl_handler); +#endif + kfree((void *)softback_buf); softback_buf = 0UL; diff --git a/trunk/drivers/watchdog/Kconfig b/trunk/drivers/watchdog/Kconfig index 3efa12f9ee50..ec68c741b564 100644 --- a/trunk/drivers/watchdog/Kconfig +++ b/trunk/drivers/watchdog/Kconfig @@ -770,12 +770,6 @@ config TXX9_WDT # POWERPC Architecture -config GEF_WDT - tristate "GE Fanuc Watchdog Timer" - depends on GEF_SBC610 - ---help--- - Watchdog timer found in a number of GE Fanuc single board computers. - config MPC5200_WDT tristate "MPC5200 Watchdog Timer" depends on PPC_MPC52xx @@ -796,14 +790,6 @@ config MV64X60_WDT tristate "MV64X60 (Marvell Discovery) Watchdog Timer" depends on MV64X60 -config PIKA_WDT - tristate "PIKA FPGA Watchdog" - depends on WARP - default y - help - This enables the watchdog in the PIKA FPGA. Currently used on - the Warp platform. - config BOOKE_WDT bool "PowerPC Book-E Watchdog Timer" depends on BOOKE || 4xx diff --git a/trunk/drivers/watchdog/Makefile b/trunk/drivers/watchdog/Makefile index 806b3eb08536..c19b866f5ed1 100644 --- a/trunk/drivers/watchdog/Makefile +++ b/trunk/drivers/watchdog/Makefile @@ -111,11 +111,9 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o # PARISC Architecture # POWERPC Architecture -obj-$(CONFIG_GEF_WDT) += gef_wdt.o obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o -obj-$(CONFIG_PIKA_WDT) += pika_wdt.o obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o # PPC64 Architecture diff --git a/trunk/drivers/watchdog/gef_wdt.c b/trunk/drivers/watchdog/gef_wdt.c deleted file mode 100644 index f0c2b7a1a175..000000000000 --- a/trunk/drivers/watchdog/gef_wdt.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * GE Fanuc watchdog userspace interface - * - * Author: Martyn Welch - * - * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Based on: mv64x60_wdt.c (MV64X60 watchdog userspace interface) - * Author: James Chapman - */ - -/* TODO: - * This driver does not provide support for the hardwares capability of sending - * an interrupt at a programmable threshold. - * - * This driver currently can only support 1 watchdog - there are 2 in the - * hardware that this driver supports. Thus one could be configured as a - * process-based watchdog (via /dev/watchdog), the second (using the interrupt - * capabilities) a kernel-based watchdog. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * The watchdog configuration register contains a pair of 2-bit fields, - * 1. a reload field, bits 27-26, which triggers a reload of - * the countdown register, and - * 2. an enable field, bits 25-24, which toggles between - * enabling and disabling the watchdog timer. - * Bit 31 is a read-only field which indicates whether the - * watchdog timer is currently enabled. - * - * The low 24 bits contain the timer reload value. - */ -#define GEF_WDC_ENABLE_SHIFT 24 -#define GEF_WDC_SERVICE_SHIFT 26 -#define GEF_WDC_ENABLED_SHIFT 31 - -#define GEF_WDC_ENABLED_TRUE 1 -#define GEF_WDC_ENABLED_FALSE 0 - -/* Flags bits */ -#define GEF_WDOG_FLAG_OPENED 0 - -static unsigned long wdt_flags; -static int wdt_status; -static void __iomem *gef_wdt_regs; -static int gef_wdt_timeout; -static int gef_wdt_count; -static unsigned int bus_clk; -static char expect_close; -static DEFINE_SPINLOCK(gef_wdt_spinlock); - -static int nowayout = WATCHDOG_NOWAYOUT; -module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" - __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - - -static int gef_wdt_toggle_wdc(int enabled_predicate, int field_shift) -{ - u32 data; - u32 enabled; - int ret = 0; - - spin_lock(&gef_wdt_spinlock); - data = ioread32be(gef_wdt_regs); - enabled = (data >> GEF_WDC_ENABLED_SHIFT) & 1; - - /* only toggle the requested field if enabled state matches predicate */ - if ((enabled ^ enabled_predicate) == 0) { - /* We write a 1, then a 2 -- to the appropriate field */ - data = (1 << field_shift) | gef_wdt_count; - iowrite32be(data, gef_wdt_regs); - - data = (2 << field_shift) | gef_wdt_count; - iowrite32be(data, gef_wdt_regs); - ret = 1; - } - spin_unlock(&gef_wdt_spinlock); - - return ret; -} - -static void gef_wdt_service(void) -{ - gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE, - GEF_WDC_SERVICE_SHIFT); -} - -static void gef_wdt_handler_enable(void) -{ - if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_FALSE, - GEF_WDC_ENABLE_SHIFT)) { - gef_wdt_service(); - printk(KERN_NOTICE "gef_wdt: watchdog activated\n"); - } -} - -static void gef_wdt_handler_disable(void) -{ - if (gef_wdt_toggle_wdc(GEF_WDC_ENABLED_TRUE, - GEF_WDC_ENABLE_SHIFT)) - printk(KERN_NOTICE "gef_wdt: watchdog deactivated\n"); -} - -static void gef_wdt_set_timeout(unsigned int timeout) -{ - /* maximum bus cycle count is 0xFFFFFFFF */ - if (timeout > 0xFFFFFFFF / bus_clk) - timeout = 0xFFFFFFFF / bus_clk; - - /* Register only holds upper 24 bits, bit shifted into lower 24 */ - gef_wdt_count = (timeout * bus_clk) >> 8; - gef_wdt_timeout = timeout; -} - - -static ssize_t gef_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - if (len) { - if (!nowayout) { - size_t i; - - expect_close = 0; - - for (i = 0; i != len; i++) { - char c; - if (get_user(c, data + i)) - return -EFAULT; - if (c == 'V') - expect_close = 42; - } - } - gef_wdt_service(); - } - - return len; -} - -static long gef_wdt_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - int timeout; - int options; - void __user *argp = (void __user *)arg; - static struct watchdog_info info = { - .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | - WDIOF_KEEPALIVEPING, - .firmware_version = 0, - .identity = "GE Fanuc watchdog", - }; - - switch (cmd) { - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &info, sizeof(info))) - return -EFAULT; - break; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - if (put_user(wdt_status, (int __user *)argp)) - return -EFAULT; - wdt_status &= ~WDIOF_KEEPALIVEPING; - break; - - case WDIOC_SETOPTIONS: - if (get_user(options, (int __user *)argp)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) - gef_wdt_handler_disable(); - - if (options & WDIOS_ENABLECARD) - gef_wdt_handler_enable(); - break; - - case WDIOC_KEEPALIVE: - gef_wdt_service(); - wdt_status |= WDIOF_KEEPALIVEPING; - break; - - case WDIOC_SETTIMEOUT: - if (get_user(timeout, (int __user *)argp)) - return -EFAULT; - gef_wdt_set_timeout(timeout); - /* Fall through */ - - case WDIOC_GETTIMEOUT: - if (put_user(gef_wdt_timeout, (int __user *)argp)) - return -EFAULT; - break; - - default: - return -ENOTTY; - } - - return 0; -} - -static int gef_wdt_open(struct inode *inode, struct file *file) -{ - if (test_and_set_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags)) - return -EBUSY; - - if (nowayout) - __module_get(THIS_MODULE); - - gef_wdt_handler_enable(); - - return nonseekable_open(inode, file); -} - -static int gef_wdt_release(struct inode *inode, struct file *file) -{ - if (expect_close == 42) - gef_wdt_handler_disable(); - else { - printk(KERN_CRIT - "gef_wdt: unexpected close, not stopping timer!\n"); - gef_wdt_service(); - } - expect_close = 0; - - clear_bit(GEF_WDOG_FLAG_OPENED, &wdt_flags); - - return 0; -} - -static const struct file_operations gef_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = gef_wdt_write, - .unlocked_ioctl = gef_wdt_ioctl, - .open = gef_wdt_open, - .release = gef_wdt_release, -}; - -static struct miscdevice gef_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &gef_wdt_fops, -}; - - -static int __devinit gef_wdt_probe(struct of_device *dev, - const struct of_device_id *match) -{ - int timeout = 10; - u32 freq; - - bus_clk = 133; /* in MHz */ - - freq = fsl_get_sys_freq(); - if (freq > 0) - bus_clk = freq; - - /* Map devices registers into memory */ - gef_wdt_regs = of_iomap(dev->node, 0); - if (gef_wdt_regs == NULL) - return -ENOMEM; - - gef_wdt_set_timeout(timeout); - - gef_wdt_handler_disable(); /* in case timer was already running */ - - return misc_register(&gef_wdt_miscdev); -} - -static int __devexit gef_wdt_remove(struct platform_device *dev) -{ - misc_deregister(&gef_wdt_miscdev); - - gef_wdt_handler_disable(); - - iounmap(gef_wdt_regs); - - return 0; -} - -static const struct of_device_id gef_wdt_ids[] = { - { - .compatible = "gef,fpga-wdt", - }, - {}, -}; - -static struct of_platform_driver gef_wdt_driver = { - .owner = THIS_MODULE, - .name = "gef_wdt", - .match_table = gef_wdt_ids, - .probe = gef_wdt_probe, -}; - -static int __init gef_wdt_init(void) -{ - printk(KERN_INFO "GE Fanuc watchdog driver\n"); - return of_register_platform_driver(&gef_wdt_driver); -} - -static void __exit gef_wdt_exit(void) -{ - of_unregister_platform_driver(&gef_wdt_driver); -} - -module_init(gef_wdt_init); -module_exit(gef_wdt_exit); - -MODULE_AUTHOR("Martyn Welch "); -MODULE_DESCRIPTION("GE Fanuc watchdog driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -MODULE_ALIAS("platform: gef_wdt"); diff --git a/trunk/drivers/watchdog/pika_wdt.c b/trunk/drivers/watchdog/pika_wdt.c deleted file mode 100644 index 2d22e996e996..000000000000 --- a/trunk/drivers/watchdog/pika_wdt.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * PIKA FPGA based Watchdog Timer - * - * Copyright (c) 2008 PIKA Technologies - * Sean MacLennan - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DRV_NAME "PIKA-WDT" -#define PFX DRV_NAME ": " - -/* Hardware timeout in seconds */ -#define WDT_HW_TIMEOUT 2 - -/* Timer heartbeat (500ms) */ -#define WDT_TIMEOUT (HZ/2) - -/* User land timeout */ -#define WDT_HEARTBEAT 15 -static int heartbeat = WDT_HEARTBEAT; -module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. " - "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")"); - -static int nowayout = WATCHDOG_NOWAYOUT; -module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " - "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - -static struct { - void __iomem *fpga; - unsigned long next_heartbeat; /* the next_heartbeat for the timer */ - unsigned long open; - char expect_close; - int bootstatus; - struct timer_list timer; /* The timer that pings the watchdog */ -} pikawdt_private; - -static struct watchdog_info ident = { - .identity = DRV_NAME, - .options = WDIOF_CARDRESET | - WDIOF_SETTIMEOUT | - WDIOF_KEEPALIVEPING | - WDIOF_MAGICCLOSE, -}; - -/* - * Reload the watchdog timer. (ie, pat the watchdog) - */ -static inline void pikawdt_reset(void) -{ - /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- - * Bit 7, WTCHDG_EN: When set to 1, the watchdog timer is enabled. - * Once enabled, it cannot be disabled. The watchdog can be - * kicked by performing any write access to the reset - * control register (this register). - * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in - * seconds. Valid ranges are 1 to 15 seconds. The value can - * be modified dynamically. - */ - unsigned reset = in_be32(pikawdt_private.fpga + 0x14); - /* enable with max timeout - 15 seconds */ - reset |= (1 << 7) + (WDT_HW_TIMEOUT << 8); - out_be32(pikawdt_private.fpga + 0x14, reset); -} - -/* - * Timer tick - */ -static void pikawdt_ping(unsigned long data) -{ - if (time_before(jiffies, pikawdt_private.next_heartbeat) || - (!nowayout && !pikawdt_private.open)) { - pikawdt_reset(); - mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); - } else - printk(KERN_CRIT PFX "I will reset your machine !\n"); -} - - -static void pikawdt_keepalive(void) -{ - pikawdt_private.next_heartbeat = jiffies + heartbeat * HZ; -} - -static void pikawdt_start(void) -{ - pikawdt_keepalive(); - mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); -} - -/* - * Watchdog device is opened, and watchdog starts running. - */ -static int pikawdt_open(struct inode *inode, struct file *file) -{ - /* /dev/watchdog can only be opened once */ - if (test_and_set_bit(0, &pikawdt_private.open)) - return -EBUSY; - - pikawdt_start(); - - return nonseekable_open(inode, file); -} - -/* - * Close the watchdog device. - */ -static int pikawdt_release(struct inode *inode, struct file *file) -{ - /* stop internal ping */ - if (!pikawdt_private.expect_close) - del_timer(&pikawdt_private.timer); - - clear_bit(0, &pikawdt_private.open); - pikawdt_private.expect_close = 0; - return 0; -} - -/* - * Pat the watchdog whenever device is written to. - */ -static ssize_t pikawdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) -{ - if (!len) - return 0; - - /* Scan for magic character */ - if (!nowayout) { - size_t i; - - pikawdt_private.expect_close = 0; - - for (i = 0; i < len; i++) { - char c; - if (get_user(c, data + i)) - return -EFAULT; - if (c == 'V') { - pikawdt_private.expect_close = 42; - break; - } - } - } - - pikawdt_keepalive(); - - return len; -} - -/* - * Handle commands from user-space. - */ -static long pikawdt_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - void __user *argp = (void __user *)arg; - int __user *p = argp; - int new_value; - - switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - return put_user(0, p); - - case WDIOC_GETBOOTSTATUS: - return put_user(pikawdt_private.bootstatus, p); - - case WDIOC_KEEPALIVE: - pikawdt_keepalive(); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - - heartbeat = new_value; - pikawdt_keepalive(); - - return put_user(new_value, p); /* return current value */ - - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, p); - } - return -ENOTTY; -} - - -static const struct file_operations pikawdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .open = pikawdt_open, - .release = pikawdt_release, - .write = pikawdt_write, - .unlocked_ioctl = pikawdt_ioctl, -}; - -static struct miscdevice pikawdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &pikawdt_fops, -}; - -static int __init pikawdt_init(void) -{ - struct device_node *np; - void __iomem *fpga; - static u32 post1; - int ret; - - np = of_find_compatible_node(NULL, NULL, "pika,fpga"); - if (np == NULL) { - printk(KERN_ERR PFX "Unable to find fpga.\n"); - return -ENOENT; - } - - pikawdt_private.fpga = of_iomap(np, 0); - of_node_put(np); - if (pikawdt_private.fpga == NULL) { - printk(KERN_ERR PFX "Unable to map fpga.\n"); - return -ENOMEM; - } - - ident.firmware_version = in_be32(pikawdt_private.fpga + 0x1c) & 0xffff; - - /* POST information is in the sd area. */ - np = of_find_compatible_node(NULL, NULL, "pika,fpga-sd"); - if (np == NULL) { - printk(KERN_ERR PFX "Unable to find fpga-sd.\n"); - ret = -ENOENT; - goto out; - } - - fpga = of_iomap(np, 0); - of_node_put(np); - if (fpga == NULL) { - printk(KERN_ERR PFX "Unable to map fpga-sd.\n"); - ret = -ENOMEM; - goto out; - } - - /* -- FPGA: POST Test Results Register 1 (32bit R/W) (Offset: 0x4040) -- - * Bit 31, WDOG: Set to 1 when the last reset was caused by a watchdog - * timeout. - */ - post1 = in_be32(fpga + 0x40); - if (post1 & 0x80000000) - pikawdt_private.bootstatus = WDIOF_CARDRESET; - - iounmap(fpga); - - setup_timer(&pikawdt_private.timer, pikawdt_ping, 0); - - ret = misc_register(&pikawdt_miscdev); - if (ret) { - printk(KERN_ERR PFX "Unable to register miscdev.\n"); - goto out; - } - - printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", - heartbeat, nowayout); - return 0; - -out: - iounmap(pikawdt_private.fpga); - return ret; -} - -static void __exit pikawdt_exit(void) -{ - misc_deregister(&pikawdt_miscdev); - - iounmap(pikawdt_private.fpga); -} - -module_init(pikawdt_init); -module_exit(pikawdt_exit); - -MODULE_AUTHOR("Sean MacLennan "); -MODULE_DESCRIPTION("PIKA FPGA based Watchdog Timer"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); - diff --git a/trunk/drivers/watchdog/wm8350_wdt.c b/trunk/drivers/watchdog/wm8350_wdt.c index a2d2e8eb2282..2bc0d4d4b415 100644 --- a/trunk/drivers/watchdog/wm8350_wdt.c +++ b/trunk/drivers/watchdog/wm8350_wdt.c @@ -279,7 +279,7 @@ static struct miscdevice wm8350_wdt_miscdev = { .fops = &wm8350_wdt_fops, }; -static int __devinit wm8350_wdt_probe(struct platform_device *pdev) +static int wm8350_wdt_probe(struct platform_device *pdev) { struct wm8350 *wm8350 = platform_get_drvdata(pdev); @@ -296,7 +296,7 @@ static int __devinit wm8350_wdt_probe(struct platform_device *pdev) return misc_register(&wm8350_wdt_miscdev); } -static int __devexit wm8350_wdt_remove(struct platform_device *pdev) +static int __exit wm8350_wdt_remove(struct platform_device *pdev) { misc_deregister(&wm8350_wdt_miscdev); @@ -305,7 +305,7 @@ static int __devexit wm8350_wdt_remove(struct platform_device *pdev) static struct platform_driver wm8350_wdt_driver = { .probe = wm8350_wdt_probe, - .remove = __devexit_p(wm8350_wdt_remove), + .remove = wm8350_wdt_remove, .driver = { .name = "wm8350-wdt", }, diff --git a/trunk/drivers/zorro/.gitignore b/trunk/drivers/zorro/.gitignore deleted file mode 100644 index 34f980bd8ff6..000000000000 --- a/trunk/drivers/zorro/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -devlist.h -gen-devlist diff --git a/trunk/drivers/zorro/zorro-sysfs.c b/trunk/drivers/zorro/zorro-sysfs.c index 1d2a772ea14c..5290552d2ef7 100644 --- a/trunk/drivers/zorro/zorro-sysfs.c +++ b/trunk/drivers/zorro/zorro-sysfs.c @@ -77,21 +77,17 @@ static struct bin_attribute zorro_config_attr = { .read = zorro_read_config, }; -int zorro_create_sysfs_dev_files(struct zorro_dev *z) +void zorro_create_sysfs_dev_files(struct zorro_dev *z) { struct device *dev = &z->dev; - int error; /* current configuration's attributes */ - if ((error = device_create_file(dev, &dev_attr_id)) || - (error = device_create_file(dev, &dev_attr_type)) || - (error = device_create_file(dev, &dev_attr_serial)) || - (error = device_create_file(dev, &dev_attr_slotaddr)) || - (error = device_create_file(dev, &dev_attr_slotsize)) || - (error = device_create_file(dev, &dev_attr_resource)) || - (error = sysfs_create_bin_file(&dev->kobj, &zorro_config_attr))) - return error; - - return 0; + device_create_file(dev, &dev_attr_id); + device_create_file(dev, &dev_attr_type); + device_create_file(dev, &dev_attr_serial); + device_create_file(dev, &dev_attr_slotaddr); + device_create_file(dev, &dev_attr_slotsize); + device_create_file(dev, &dev_attr_resource); + sysfs_create_bin_file(&dev->kobj, &zorro_config_attr); } diff --git a/trunk/drivers/zorro/zorro.c b/trunk/drivers/zorro/zorro.c index a1585d6f6486..dff16d9767d8 100644 --- a/trunk/drivers/zorro/zorro.c +++ b/trunk/drivers/zorro/zorro.c @@ -130,7 +130,6 @@ static int __init zorro_init(void) { struct zorro_dev *z; unsigned int i; - int error; if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO)) return 0; @@ -141,11 +140,7 @@ static int __init zorro_init(void) /* Initialize the Zorro bus */ INIT_LIST_HEAD(&zorro_bus.devices); strcpy(zorro_bus.dev.bus_id, "zorro"); - error = device_register(&zorro_bus.dev); - if (error) { - pr_err("Zorro: Error registering zorro_bus\n"); - return error; - } + device_register(&zorro_bus.dev); /* Request the resources */ zorro_bus.num_resources = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2; @@ -165,19 +160,15 @@ static int __init zorro_init(void) zorro_name_device(z); z->resource.name = z->name; if (request_resource(zorro_find_parent_resource(z), &z->resource)) - pr_err("Zorro: Address space collision on device %s %pR\n", - z->name, &z->resource); + printk(KERN_ERR "Zorro: Address space collision on device %s " + "[%lx:%lx]\n", + z->name, (unsigned long)zorro_resource_start(z), + (unsigned long)zorro_resource_end(z)); sprintf(z->dev.bus_id, "%02x", i); z->dev.parent = &zorro_bus.dev; z->dev.bus = &zorro_bus_type; - error = device_register(&z->dev); - if (error) { - pr_err("Zorro: Error registering device %s\n", z->name); - continue; - } - error = zorro_create_sysfs_dev_files(z); - if (error) - dev_err(&z->dev, "Error creating sysfs files\n"); + device_register(&z->dev); + zorro_create_sysfs_dev_files(z); } /* Mark all available Zorro II memory */ diff --git a/trunk/drivers/zorro/zorro.h b/trunk/drivers/zorro/zorro.h index b682d5ccd63f..5c91adac4df1 100644 --- a/trunk/drivers/zorro/zorro.h +++ b/trunk/drivers/zorro/zorro.h @@ -1,4 +1,4 @@ extern void zorro_name_device(struct zorro_dev *z); -extern int zorro_create_sysfs_dev_files(struct zorro_dev *z); +extern void zorro_create_sysfs_dev_files(struct zorro_dev *z); diff --git a/trunk/firmware/Makefile b/trunk/firmware/Makefile index 466106fa2146..ea1d28f9b44c 100644 --- a/trunk/firmware/Makefile +++ b/trunk/firmware/Makefile @@ -78,8 +78,7 @@ fw-shipped- += keyspan/mpr.fw keyspan/usa18x.fw keyspan/usa19.fw \ keyspan/usa28.fw keyspan/usa28xa.fw keyspan/usa28xb.fw \ keyspan/usa28x.fw keyspan/usa49w.fw keyspan/usa49wlc.fw endif -fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw \ - mts_cdma.fw mts_gsm.fw mts_edge.fw +fw-shipped-$(CONFIG_USB_SERIAL_TI) += ti_3410.fw ti_5052.fw fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT) += edgeport/boot.fw edgeport/boot2.fw \ edgeport/down.fw edgeport/down2.fw fw-shipped-$(CONFIG_USB_SERIAL_EDGEPORT_TI) += edgeport/down3.bin diff --git a/trunk/firmware/WHENCE b/trunk/firmware/WHENCE index 524113f9bea3..8b5651347791 100644 --- a/trunk/firmware/WHENCE +++ b/trunk/firmware/WHENCE @@ -191,7 +191,7 @@ Original licence information: None -------------------------------------------------------------------------- -Driver: ti_usb_3410_5052 -- USB TI 3410/5052 serial device +Driver: tu_usb_3410_5052 -- USB TI 3410/5052 serial device File: ti_3410.fw Info: firmware 9/10/04 FW3410_Special_StartWdogOnStartPort @@ -206,20 +206,6 @@ Found in hex form in kernel source. -------------------------------------------------------------------------- -Driver: ti_usb_3410_5052 -- Multi-Tech USB cell modems - -File: mts_cdma.fw -File: mts_gsm.fw -File: mts_edge.fw - -Licence: "all firmware components are redistributable in binary form" - per support@multitech.com - Copyright (C) 2005 Multi-Tech Systems, Inc. - -Found in hex form in ftp://ftp.multitech.com/wireless/wireless_linux.zip - --------------------------------------------------------------------------- - Driver: whiteheat -- USB ConnectTech WhiteHEAT serial device File: whiteheat.fw diff --git a/trunk/firmware/mts_cdma.fw.ihex b/trunk/firmware/mts_cdma.fw.ihex deleted file mode 100644 index f6ad0cbd30cb..000000000000 --- a/trunk/firmware/mts_cdma.fw.ihex +++ /dev/null @@ -1,867 +0,0 @@ -:1000000014360002001E021AF9FFFFFFFFFF023341 -:100010001DFFFFFFFFFFFFFFFFFFFFFFFFFF02339B -:10002000C87581CE90FDE88583A012353CEC4D600B -:100030007378AB8003760018B89CFA787F800376DB -:100040000018B865FA78208003760018B820FA788E -:10005000208003760018B81FFA90FDDDAE83AF82D2 -:1000600090FBF81200AA6005E4F0A380F690FDE88A -:10007000A88290FDE8A982E8696005E4F20880F7AB -:100080009001081200B390010C1200B390011012FD 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******************************************************************************* ** -** Copyright (C) 2005-2009 Red Hat, Inc. All rights reserved. +** Copyright (C) 2005-2008 Red Hat, Inc. All rights reserved. ** ** This copyrighted material is made available to anyone wishing to use, ** modify, copy, or redistribute it subject to the terms and conditions @@ -25,6 +25,19 @@ static struct mutex debug_buf_lock; static struct dentry *dlm_root; +struct rsb_iter { + int entry; + int format; + int header; + struct dlm_ls *ls; + struct list_head *next; + struct dlm_rsb *rsb; +}; + +/* + * dump all rsb's in the lockspace hash table + */ + static char *print_lockmode(int mode) { switch (mode) { @@ -47,13 +60,13 @@ static char *print_lockmode(int mode) } } -static int print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, - struct dlm_rsb *res) +static void print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, + struct dlm_rsb *res) { seq_printf(s, "%08x %s", lkb->lkb_id, print_lockmode(lkb->lkb_grmode)); - if (lkb->lkb_status == DLM_LKSTS_CONVERT || - lkb->lkb_status == DLM_LKSTS_WAITING) + if (lkb->lkb_status == DLM_LKSTS_CONVERT + || lkb->lkb_status == DLM_LKSTS_WAITING) seq_printf(s, " (%s)", print_lockmode(lkb->lkb_rqmode)); if (lkb->lkb_nodeid) { @@ -67,42 +80,33 @@ static int print_format1_lock(struct seq_file *s, struct dlm_lkb *lkb, if (lkb->lkb_wait_type) seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); - return seq_printf(s, "\n"); + seq_printf(s, "\n"); } static int print_format1(struct dlm_rsb *res, struct seq_file *s) { struct dlm_lkb *lkb; int i, lvblen = res->res_ls->ls_lvblen, recover_list, root_list; - int rv; lock_rsb(res); - rv = seq_printf(s, "\nResource %p Name (len=%d) \"", - res, res->res_length); - if (rv) - goto out; - + seq_printf(s, "\nResource %p Name (len=%d) \"", res, res->res_length); for (i = 0; i < res->res_length; i++) { if (isprint(res->res_name[i])) seq_printf(s, "%c", res->res_name[i]); else seq_printf(s, "%c", '.'); } - if (res->res_nodeid > 0) - rv = seq_printf(s, "\" \nLocal Copy, Master is node %d\n", - res->res_nodeid); + seq_printf(s, "\" \nLocal Copy, Master is node %d\n", + res->res_nodeid); else if (res->res_nodeid == 0) - rv = seq_printf(s, "\" \nMaster Copy\n"); + seq_printf(s, "\" \nMaster Copy\n"); else if (res->res_nodeid == -1) - rv = seq_printf(s, "\" \nLooking up master (lkid %x)\n", - res->res_first_lkid); + seq_printf(s, "\" \nLooking up master (lkid %x)\n", + res->res_first_lkid); else - rv = seq_printf(s, "\" \nInvalid master %d\n", - res->res_nodeid); - if (rv) - goto out; + seq_printf(s, "\" \nInvalid master %d\n", res->res_nodeid); /* Print the LVB: */ if (res->res_lvbptr) { @@ -115,66 +119,52 @@ static int print_format1(struct dlm_rsb *res, struct seq_file *s) } if (rsb_flag(res, RSB_VALNOTVALID)) seq_printf(s, " (INVALID)"); - rv = seq_printf(s, "\n"); - if (rv) - goto out; + seq_printf(s, "\n"); } root_list = !list_empty(&res->res_root_list); recover_list = !list_empty(&res->res_recover_list); if (root_list || recover_list) { - rv = seq_printf(s, "Recovery: root %d recover %d flags %lx " - "count %d\n", root_list, recover_list, - res->res_flags, res->res_recover_locks_count); - if (rv) - goto out; + seq_printf(s, "Recovery: root %d recover %d flags %lx " + "count %d\n", root_list, recover_list, + res->res_flags, res->res_recover_locks_count); } /* Print the locks attached to this resource */ seq_printf(s, "Granted Queue\n"); - list_for_each_entry(lkb, &res->res_grantqueue, lkb_statequeue) { - rv = print_format1_lock(s, lkb, res); - if (rv) - goto out; - } + list_for_each_entry(lkb, &res->res_grantqueue, lkb_statequeue) + print_format1_lock(s, lkb, res); seq_printf(s, "Conversion Queue\n"); - list_for_each_entry(lkb, &res->res_convertqueue, lkb_statequeue) { - rv = print_format1_lock(s, lkb, res); - if (rv) - goto out; - } + list_for_each_entry(lkb, &res->res_convertqueue, lkb_statequeue) + print_format1_lock(s, lkb, res); seq_printf(s, "Waiting Queue\n"); - list_for_each_entry(lkb, &res->res_waitqueue, lkb_statequeue) { - rv = print_format1_lock(s, lkb, res); - if (rv) - goto out; - } + list_for_each_entry(lkb, &res->res_waitqueue, lkb_statequeue) + print_format1_lock(s, lkb, res); if (list_empty(&res->res_lookup)) goto out; seq_printf(s, "Lookup Queue\n"); list_for_each_entry(lkb, &res->res_lookup, lkb_rsb_lookup) { - rv = seq_printf(s, "%08x %s", lkb->lkb_id, - print_lockmode(lkb->lkb_rqmode)); + seq_printf(s, "%08x %s", lkb->lkb_id, + print_lockmode(lkb->lkb_rqmode)); if (lkb->lkb_wait_type) seq_printf(s, " wait_type: %d", lkb->lkb_wait_type); - rv = seq_printf(s, "\n"); + seq_printf(s, "\n"); } out: unlock_rsb(res); - return rv; + return 0; } -static int print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, - struct dlm_rsb *r) +static void print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, + struct dlm_rsb *r) { u64 xid = 0; u64 us; - int rv; if (lkb->lkb_flags & DLM_IFL_USER) { if (lkb->lkb_ua) @@ -187,82 +177,69 @@ static int print_format2_lock(struct seq_file *s, struct dlm_lkb *lkb, /* id nodeid remid pid xid exflags flags sts grmode rqmode time_us r_nodeid r_len r_name */ - rv = seq_printf(s, "%x %d %x %u %llu %x %x %d %d %d %llu %u %d \"%s\"\n", - lkb->lkb_id, - lkb->lkb_nodeid, - lkb->lkb_remid, - lkb->lkb_ownpid, - (unsigned long long)xid, - lkb->lkb_exflags, - lkb->lkb_flags, - lkb->lkb_status, - lkb->lkb_grmode, - lkb->lkb_rqmode, - (unsigned long long)us, - r->res_nodeid, - r->res_length, - r->res_name); - return rv; + seq_printf(s, "%x %d %x %u %llu %x %x %d %d %d %llu %u %d \"%s\"\n", + lkb->lkb_id, + lkb->lkb_nodeid, + lkb->lkb_remid, + lkb->lkb_ownpid, + (unsigned long long)xid, + lkb->lkb_exflags, + lkb->lkb_flags, + lkb->lkb_status, + lkb->lkb_grmode, + lkb->lkb_rqmode, + (unsigned long long)us, + r->res_nodeid, + r->res_length, + r->res_name); } static int print_format2(struct dlm_rsb *r, struct seq_file *s) { struct dlm_lkb *lkb; - int rv = 0; lock_rsb(r); - list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { - rv = print_format2_lock(s, lkb, r); - if (rv) - goto out; - } + list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) + print_format2_lock(s, lkb, r); - list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { - rv = print_format2_lock(s, lkb, r); - if (rv) - goto out; - } + list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) + print_format2_lock(s, lkb, r); + + list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) + print_format2_lock(s, lkb, r); - list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) { - rv = print_format2_lock(s, lkb, r); - if (rv) - goto out; - } - out: unlock_rsb(r); - return rv; + return 0; } -static int print_format3_lock(struct seq_file *s, struct dlm_lkb *lkb, - int rsb_lookup) +static void print_format3_lock(struct seq_file *s, struct dlm_lkb *lkb, + int rsb_lookup) { u64 xid = 0; - int rv; if (lkb->lkb_flags & DLM_IFL_USER) { if (lkb->lkb_ua) xid = lkb->lkb_ua->xid; } - rv = seq_printf(s, "lkb %x %d %x %u %llu %x %x %d %d %d %d %d %d %u %llu %llu\n", - lkb->lkb_id, - lkb->lkb_nodeid, - lkb->lkb_remid, - lkb->lkb_ownpid, - (unsigned long long)xid, - lkb->lkb_exflags, - lkb->lkb_flags, - lkb->lkb_status, - lkb->lkb_grmode, - lkb->lkb_rqmode, - lkb->lkb_highbast, - rsb_lookup, - lkb->lkb_wait_type, - lkb->lkb_lvbseq, - (unsigned long long)ktime_to_ns(lkb->lkb_timestamp), - (unsigned long long)ktime_to_ns(lkb->lkb_time_bast)); - return rv; + seq_printf(s, "lkb %x %d %x %u %llu %x %x %d %d %d %d %d %d %u %llu %llu\n", + lkb->lkb_id, + lkb->lkb_nodeid, + lkb->lkb_remid, + lkb->lkb_ownpid, + (unsigned long long)xid, + lkb->lkb_exflags, + lkb->lkb_flags, + lkb->lkb_status, + lkb->lkb_grmode, + lkb->lkb_rqmode, + lkb->lkb_highbast, + rsb_lookup, + lkb->lkb_wait_type, + lkb->lkb_lvbseq, + (unsigned long long)ktime_to_ns(lkb->lkb_timestamp), + (unsigned long long)ktime_to_ns(lkb->lkb_time_bast)); } static int print_format3(struct dlm_rsb *r, struct seq_file *s) @@ -270,21 +247,18 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) struct dlm_lkb *lkb; int i, lvblen = r->res_ls->ls_lvblen; int print_name = 1; - int rv; lock_rsb(r); - rv = seq_printf(s, "rsb %p %d %x %lx %d %d %u %d ", - r, - r->res_nodeid, - r->res_first_lkid, - r->res_flags, - !list_empty(&r->res_root_list), - !list_empty(&r->res_recover_list), - r->res_recover_locks_count, - r->res_length); - if (rv) - goto out; + seq_printf(s, "rsb %p %d %x %lx %d %d %u %d ", + r, + r->res_nodeid, + r->res_first_lkid, + r->res_flags, + !list_empty(&r->res_root_list), + !list_empty(&r->res_recover_list), + r->res_recover_locks_count, + r->res_length); for (i = 0; i < r->res_length; i++) { if (!isascii(r->res_name[i]) || !isprint(r->res_name[i])) @@ -299,9 +273,7 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) else seq_printf(s, " %02x", (unsigned char)r->res_name[i]); } - rv = seq_printf(s, "\n"); - if (rv) - goto out; + seq_printf(s, "\n"); if (!r->res_lvbptr) goto do_locks; @@ -310,294 +282,344 @@ static int print_format3(struct dlm_rsb *r, struct seq_file *s) for (i = 0; i < lvblen; i++) seq_printf(s, " %02x", (unsigned char)r->res_lvbptr[i]); - rv = seq_printf(s, "\n"); - if (rv) - goto out; + seq_printf(s, "\n"); do_locks: - list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { - rv = print_format3_lock(s, lkb, 0); - if (rv) - goto out; - } + list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) + print_format3_lock(s, lkb, 0); + + list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) + print_format3_lock(s, lkb, 0); + + list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) + print_format3_lock(s, lkb, 0); + + list_for_each_entry(lkb, &r->res_lookup, lkb_rsb_lookup) + print_format3_lock(s, lkb, 1); - list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { - rv = print_format3_lock(s, lkb, 0); - if (rv) - goto out; + unlock_rsb(r); + return 0; +} + +static int rsb_iter_next(struct rsb_iter *ri) +{ + struct dlm_ls *ls = ri->ls; + int i; + + if (!ri->next) { + top: + /* Find the next non-empty hash bucket */ + for (i = ri->entry; i < ls->ls_rsbtbl_size; i++) { + read_lock(&ls->ls_rsbtbl[i].lock); + if (!list_empty(&ls->ls_rsbtbl[i].list)) { + ri->next = ls->ls_rsbtbl[i].list.next; + ri->rsb = list_entry(ri->next, struct dlm_rsb, + res_hashchain); + dlm_hold_rsb(ri->rsb); + read_unlock(&ls->ls_rsbtbl[i].lock); + break; + } + read_unlock(&ls->ls_rsbtbl[i].lock); + } + ri->entry = i; + + if (ri->entry >= ls->ls_rsbtbl_size) + return 1; + } else { + struct dlm_rsb *old = ri->rsb; + i = ri->entry; + read_lock(&ls->ls_rsbtbl[i].lock); + ri->next = ri->next->next; + if (ri->next->next == ls->ls_rsbtbl[i].list.next) { + /* End of list - move to next bucket */ + ri->next = NULL; + ri->entry++; + read_unlock(&ls->ls_rsbtbl[i].lock); + dlm_put_rsb(old); + goto top; + } + ri->rsb = list_entry(ri->next, struct dlm_rsb, res_hashchain); + dlm_hold_rsb(ri->rsb); + read_unlock(&ls->ls_rsbtbl[i].lock); + dlm_put_rsb(old); } - list_for_each_entry(lkb, &r->res_waitqueue, lkb_statequeue) { - rv = print_format3_lock(s, lkb, 0); - if (rv) - goto out; + return 0; +} + +static void rsb_iter_free(struct rsb_iter *ri) +{ + kfree(ri); +} + +static struct rsb_iter *rsb_iter_init(struct dlm_ls *ls) +{ + struct rsb_iter *ri; + + ri = kzalloc(sizeof *ri, GFP_KERNEL); + if (!ri) + return NULL; + + ri->ls = ls; + ri->entry = 0; + ri->next = NULL; + ri->format = 1; + + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; } - list_for_each_entry(lkb, &r->res_lookup, lkb_rsb_lookup) { - rv = print_format3_lock(s, lkb, 1); - if (rv) - goto out; + return ri; +} + +static void *rsb_seq_start(struct seq_file *file, loff_t *pos) +{ + struct rsb_iter *ri; + loff_t n = *pos; + + ri = rsb_iter_init(file->private); + if (!ri) + return NULL; + + while (n--) { + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; + } } - out: - unlock_rsb(r); - return rv; + + return ri; } -struct rsbtbl_iter { - struct dlm_rsb *rsb; - unsigned bucket; - int format; - int header; -}; +static void *rsb_seq_next(struct seq_file *file, void *iter_ptr, loff_t *pos) +{ + struct rsb_iter *ri = iter_ptr; + + (*pos)++; + + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; + } -/* seq_printf returns -1 if the buffer is full, and 0 otherwise. - If the buffer is full, seq_printf can be called again, but it - does nothing and just returns -1. So, the these printing routines - periodically check the return value to avoid wasting too much time - trying to print to a full buffer. */ + return ri; +} + +static void rsb_seq_stop(struct seq_file *file, void *iter_ptr) +{ + /* nothing for now */ +} -static int table_seq_show(struct seq_file *seq, void *iter_ptr) +static int rsb_seq_show(struct seq_file *file, void *iter_ptr) { - struct rsbtbl_iter *ri = iter_ptr; - int rv = 0; + struct rsb_iter *ri = iter_ptr; switch (ri->format) { case 1: - rv = print_format1(ri->rsb, seq); + print_format1(ri->rsb, file); break; case 2: if (ri->header) { - seq_printf(seq, "id nodeid remid pid xid exflags " - "flags sts grmode rqmode time_ms " - "r_nodeid r_len r_name\n"); + seq_printf(file, "id nodeid remid pid xid exflags " + "flags sts grmode rqmode time_ms " + "r_nodeid r_len r_name\n"); ri->header = 0; } - rv = print_format2(ri->rsb, seq); + print_format2(ri->rsb, file); break; case 3: if (ri->header) { - seq_printf(seq, "version rsb 1.1 lvb 1.1 lkb 1.1\n"); + seq_printf(file, "version rsb 1.1 lvb 1.1 lkb 1.1\n"); ri->header = 0; } - rv = print_format3(ri->rsb, seq); + print_format3(ri->rsb, file); break; } - return rv; + return 0; } -static struct seq_operations format1_seq_ops; -static struct seq_operations format2_seq_ops; -static struct seq_operations format3_seq_ops; +static struct seq_operations rsb_seq_ops = { + .start = rsb_seq_start, + .next = rsb_seq_next, + .stop = rsb_seq_stop, + .show = rsb_seq_show, +}; -static void *table_seq_start(struct seq_file *seq, loff_t *pos) +static int rsb_open(struct inode *inode, struct file *file) { - struct dlm_ls *ls = seq->private; - struct rsbtbl_iter *ri; - struct dlm_rsb *r; - loff_t n = *pos; - unsigned bucket, entry; + struct seq_file *seq; + int ret; - bucket = n >> 32; - entry = n & ((1LL << 32) - 1); + ret = seq_open(file, &rsb_seq_ops); + if (ret) + return ret; - if (bucket >= ls->ls_rsbtbl_size) - return NULL; + seq = file->private_data; + seq->private = inode->i_private; + + return 0; +} + +static const struct file_operations rsb_fops = { + .owner = THIS_MODULE, + .open = rsb_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release +}; - ri = kzalloc(sizeof(struct rsbtbl_iter), GFP_KERNEL); +/* + * Dump state in compact per-lock listing + */ + +static struct rsb_iter *locks_iter_init(struct dlm_ls *ls, loff_t *pos) +{ + struct rsb_iter *ri; + + ri = kzalloc(sizeof *ri, GFP_KERNEL); if (!ri) return NULL; - if (n == 0) + + ri->ls = ls; + ri->entry = 0; + ri->next = NULL; + ri->format = 2; + + if (*pos == 0) ri->header = 1; - if (seq->op == &format1_seq_ops) - ri->format = 1; - if (seq->op == &format2_seq_ops) - ri->format = 2; - if (seq->op == &format3_seq_ops) - ri->format = 3; - - spin_lock(&ls->ls_rsbtbl[bucket].lock); - if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { - list_for_each_entry(r, &ls->ls_rsbtbl[bucket].list, - res_hashchain) { - if (!entry--) { - dlm_hold_rsb(r); - ri->rsb = r; - ri->bucket = bucket; - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - return ri; - } - } + + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; } - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - /* - * move to the first rsb in the next non-empty bucket - */ + return ri; +} - /* zero the entry */ - n &= ~((1LL << 32) - 1); +static void *locks_seq_start(struct seq_file *file, loff_t *pos) +{ + struct rsb_iter *ri; + loff_t n = *pos; - while (1) { - bucket++; - n += 1LL << 32; + ri = locks_iter_init(file->private, pos); + if (!ri) + return NULL; - if (bucket >= ls->ls_rsbtbl_size) { - kfree(ri); + while (n--) { + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); return NULL; } - - spin_lock(&ls->ls_rsbtbl[bucket].lock); - if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { - r = list_first_entry(&ls->ls_rsbtbl[bucket].list, - struct dlm_rsb, res_hashchain); - dlm_hold_rsb(r); - ri->rsb = r; - ri->bucket = bucket; - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - *pos = n; - return ri; - } - spin_unlock(&ls->ls_rsbtbl[bucket].lock); } + + return ri; } -static void *table_seq_next(struct seq_file *seq, void *iter_ptr, loff_t *pos) +static struct seq_operations locks_seq_ops = { + .start = locks_seq_start, + .next = rsb_seq_next, + .stop = rsb_seq_stop, + .show = rsb_seq_show, +}; + +static int locks_open(struct inode *inode, struct file *file) { - struct dlm_ls *ls = seq->private; - struct rsbtbl_iter *ri = iter_ptr; - struct list_head *next; - struct dlm_rsb *r, *rp; - loff_t n = *pos; - unsigned bucket; - - bucket = n >> 32; - - /* - * move to the next rsb in the same bucket - */ - - spin_lock(&ls->ls_rsbtbl[bucket].lock); - rp = ri->rsb; - next = rp->res_hashchain.next; - - if (next != &ls->ls_rsbtbl[bucket].list) { - r = list_entry(next, struct dlm_rsb, res_hashchain); - dlm_hold_rsb(r); - ri->rsb = r; - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - dlm_put_rsb(rp); - ++*pos; - return ri; - } - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - dlm_put_rsb(rp); + struct seq_file *seq; + int ret; - /* - * move to the first rsb in the next non-empty bucket - */ + ret = seq_open(file, &locks_seq_ops); + if (ret) + return ret; - /* zero the entry */ - n &= ~((1LL << 32) - 1); + seq = file->private_data; + seq->private = inode->i_private; - while (1) { - bucket++; - n += 1LL << 32; + return 0; +} - if (bucket >= ls->ls_rsbtbl_size) { - kfree(ri); - return NULL; - } +static const struct file_operations locks_fops = { + .owner = THIS_MODULE, + .open = locks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release +}; - spin_lock(&ls->ls_rsbtbl[bucket].lock); - if (!list_empty(&ls->ls_rsbtbl[bucket].list)) { - r = list_first_entry(&ls->ls_rsbtbl[bucket].list, - struct dlm_rsb, res_hashchain); - dlm_hold_rsb(r); - ri->rsb = r; - ri->bucket = bucket; - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - *pos = n; - return ri; - } - spin_unlock(&ls->ls_rsbtbl[bucket].lock); - } -} +/* + * Dump all rsb/lvb/lkb state in compact listing, more complete than _locks + * This can replace both formats 1 and 2 eventually. + */ -static void table_seq_stop(struct seq_file *seq, void *iter_ptr) +static struct rsb_iter *all_iter_init(struct dlm_ls *ls, loff_t *pos) { - struct rsbtbl_iter *ri = iter_ptr; + struct rsb_iter *ri; + + ri = kzalloc(sizeof *ri, GFP_KERNEL); + if (!ri) + return NULL; + + ri->ls = ls; + ri->entry = 0; + ri->next = NULL; + ri->format = 3; + + if (*pos == 0) + ri->header = 1; - if (ri) { - dlm_put_rsb(ri->rsb); - kfree(ri); + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; } + + return ri; } -static struct seq_operations format1_seq_ops = { - .start = table_seq_start, - .next = table_seq_next, - .stop = table_seq_stop, - .show = table_seq_show, -}; +static void *all_seq_start(struct seq_file *file, loff_t *pos) +{ + struct rsb_iter *ri; + loff_t n = *pos; -static struct seq_operations format2_seq_ops = { - .start = table_seq_start, - .next = table_seq_next, - .stop = table_seq_stop, - .show = table_seq_show, -}; + ri = all_iter_init(file->private, pos); + if (!ri) + return NULL; -static struct seq_operations format3_seq_ops = { - .start = table_seq_start, - .next = table_seq_next, - .stop = table_seq_stop, - .show = table_seq_show, -}; + while (n--) { + if (rsb_iter_next(ri)) { + rsb_iter_free(ri); + return NULL; + } + } -static const struct file_operations format1_fops; -static const struct file_operations format2_fops; -static const struct file_operations format3_fops; + return ri; +} -static int table_open(struct inode *inode, struct file *file) +static struct seq_operations all_seq_ops = { + .start = all_seq_start, + .next = rsb_seq_next, + .stop = rsb_seq_stop, + .show = rsb_seq_show, +}; + +static int all_open(struct inode *inode, struct file *file) { struct seq_file *seq; - int ret = -1; - - if (file->f_op == &format1_fops) - ret = seq_open(file, &format1_seq_ops); - else if (file->f_op == &format2_fops) - ret = seq_open(file, &format2_seq_ops); - else if (file->f_op == &format3_fops) - ret = seq_open(file, &format3_seq_ops); + int ret; + ret = seq_open(file, &all_seq_ops); if (ret) return ret; seq = file->private_data; - seq->private = inode->i_private; /* the dlm_ls */ + seq->private = inode->i_private; + return 0; } -static const struct file_operations format1_fops = { - .owner = THIS_MODULE, - .open = table_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release -}; - -static const struct file_operations format2_fops = { - .owner = THIS_MODULE, - .open = table_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release -}; - -static const struct file_operations format3_fops = { +static const struct file_operations all_fops = { .owner = THIS_MODULE, - .open = table_open, + .open = all_open, .read = seq_read, .llseek = seq_lseek, .release = seq_release @@ -667,7 +689,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) S_IFREG | S_IRUGO, dlm_root, ls, - &format1_fops); + &rsb_fops); if (!ls->ls_debug_rsb_dentry) goto fail; @@ -680,7 +702,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) S_IFREG | S_IRUGO, dlm_root, ls, - &format2_fops); + &locks_fops); if (!ls->ls_debug_locks_dentry) goto fail; @@ -693,7 +715,7 @@ int dlm_create_debug_file(struct dlm_ls *ls) S_IFREG | S_IRUGO, dlm_root, ls, - &format3_fops); + &all_fops); if (!ls->ls_debug_all_dentry) goto fail; diff --git a/trunk/fs/dlm/dlm_internal.h b/trunk/fs/dlm/dlm_internal.h index 076e86f38bc8..ef2f1e353966 100644 --- a/trunk/fs/dlm/dlm_internal.h +++ b/trunk/fs/dlm/dlm_internal.h @@ -105,7 +105,7 @@ struct dlm_dirtable { struct dlm_rsbtable { struct list_head list; struct list_head toss; - spinlock_t lock; + rwlock_t lock; }; struct dlm_lkbtable { diff --git a/trunk/fs/dlm/lock.c b/trunk/fs/dlm/lock.c index 01e7d39c5fba..6cfe65bbf4a2 100644 --- a/trunk/fs/dlm/lock.c +++ b/trunk/fs/dlm/lock.c @@ -412,9 +412,9 @@ static int search_rsb(struct dlm_ls *ls, char *name, int len, int b, unsigned int flags, struct dlm_rsb **r_ret) { int error; - spin_lock(&ls->ls_rsbtbl[b].lock); + write_lock(&ls->ls_rsbtbl[b].lock); error = _search_rsb(ls, name, len, b, flags, r_ret); - spin_unlock(&ls->ls_rsbtbl[b].lock); + write_unlock(&ls->ls_rsbtbl[b].lock); return error; } @@ -478,16 +478,16 @@ static int find_rsb(struct dlm_ls *ls, char *name, int namelen, r->res_nodeid = nodeid; } - spin_lock(&ls->ls_rsbtbl[bucket].lock); + write_lock(&ls->ls_rsbtbl[bucket].lock); error = _search_rsb(ls, name, namelen, bucket, 0, &tmp); if (!error) { - spin_unlock(&ls->ls_rsbtbl[bucket].lock); + write_unlock(&ls->ls_rsbtbl[bucket].lock); dlm_free_rsb(r); r = tmp; goto out; } list_add(&r->res_hashchain, &ls->ls_rsbtbl[bucket].list); - spin_unlock(&ls->ls_rsbtbl[bucket].lock); + write_unlock(&ls->ls_rsbtbl[bucket].lock); error = 0; out: *r_ret = r; @@ -530,9 +530,9 @@ static void put_rsb(struct dlm_rsb *r) struct dlm_ls *ls = r->res_ls; uint32_t bucket = r->res_bucket; - spin_lock(&ls->ls_rsbtbl[bucket].lock); + write_lock(&ls->ls_rsbtbl[bucket].lock); kref_put(&r->res_ref, toss_rsb); - spin_unlock(&ls->ls_rsbtbl[bucket].lock); + write_unlock(&ls->ls_rsbtbl[bucket].lock); } void dlm_put_rsb(struct dlm_rsb *r) @@ -967,7 +967,7 @@ static int shrink_bucket(struct dlm_ls *ls, int b) for (;;) { found = 0; - spin_lock(&ls->ls_rsbtbl[b].lock); + write_lock(&ls->ls_rsbtbl[b].lock); list_for_each_entry_reverse(r, &ls->ls_rsbtbl[b].toss, res_hashchain) { if (!time_after_eq(jiffies, r->res_toss_time + @@ -978,20 +978,20 @@ static int shrink_bucket(struct dlm_ls *ls, int b) } if (!found) { - spin_unlock(&ls->ls_rsbtbl[b].lock); + write_unlock(&ls->ls_rsbtbl[b].lock); break; } if (kref_put(&r->res_ref, kill_rsb)) { list_del(&r->res_hashchain); - spin_unlock(&ls->ls_rsbtbl[b].lock); + write_unlock(&ls->ls_rsbtbl[b].lock); if (is_master(r)) dir_remove(r); dlm_free_rsb(r); count++; } else { - spin_unlock(&ls->ls_rsbtbl[b].lock); + write_unlock(&ls->ls_rsbtbl[b].lock); log_error(ls, "tossed rsb in use %s", r->res_name); } } @@ -4224,7 +4224,7 @@ static struct dlm_rsb *find_purged_rsb(struct dlm_ls *ls, int bucket) { struct dlm_rsb *r, *r_ret = NULL; - spin_lock(&ls->ls_rsbtbl[bucket].lock); + read_lock(&ls->ls_rsbtbl[bucket].lock); list_for_each_entry(r, &ls->ls_rsbtbl[bucket].list, res_hashchain) { if (!rsb_flag(r, RSB_LOCKS_PURGED)) continue; @@ -4233,7 +4233,7 @@ static struct dlm_rsb *find_purged_rsb(struct dlm_ls *ls, int bucket) r_ret = r; break; } - spin_unlock(&ls->ls_rsbtbl[bucket].lock); + read_unlock(&ls->ls_rsbtbl[bucket].lock); return r_ret; } diff --git a/trunk/fs/dlm/lockspace.c b/trunk/fs/dlm/lockspace.c index aa32e5f02493..8d86b7960f0d 100644 --- a/trunk/fs/dlm/lockspace.c +++ b/trunk/fs/dlm/lockspace.c @@ -464,7 +464,7 @@ static int new_lockspace(char *name, int namelen, void **lockspace, for (i = 0; i < size; i++) { INIT_LIST_HEAD(&ls->ls_rsbtbl[i].list); INIT_LIST_HEAD(&ls->ls_rsbtbl[i].toss); - spin_lock_init(&ls->ls_rsbtbl[i].lock); + rwlock_init(&ls->ls_rsbtbl[i].lock); } size = dlm_config.ci_lkbtbl_size; diff --git a/trunk/fs/dlm/recover.c b/trunk/fs/dlm/recover.c index eda43f362616..80aba5bdd4a4 100644 --- a/trunk/fs/dlm/recover.c +++ b/trunk/fs/dlm/recover.c @@ -726,7 +726,7 @@ int dlm_create_root_list(struct dlm_ls *ls) } for (i = 0; i < ls->ls_rsbtbl_size; i++) { - spin_lock(&ls->ls_rsbtbl[i].lock); + read_lock(&ls->ls_rsbtbl[i].lock); list_for_each_entry(r, &ls->ls_rsbtbl[i].list, res_hashchain) { list_add(&r->res_root_list, &ls->ls_root_list); dlm_hold_rsb(r); @@ -737,7 +737,7 @@ int dlm_create_root_list(struct dlm_ls *ls) but no other recovery steps should do anything with them. */ if (dlm_no_directory(ls)) { - spin_unlock(&ls->ls_rsbtbl[i].lock); + read_unlock(&ls->ls_rsbtbl[i].lock); continue; } @@ -745,7 +745,7 @@ int dlm_create_root_list(struct dlm_ls *ls) list_add(&r->res_root_list, &ls->ls_root_list); dlm_hold_rsb(r); } - spin_unlock(&ls->ls_rsbtbl[i].lock); + read_unlock(&ls->ls_rsbtbl[i].lock); } out: up_write(&ls->ls_root_sem); @@ -775,7 +775,7 @@ void dlm_clear_toss_list(struct dlm_ls *ls) int i; for (i = 0; i < ls->ls_rsbtbl_size; i++) { - spin_lock(&ls->ls_rsbtbl[i].lock); + write_lock(&ls->ls_rsbtbl[i].lock); list_for_each_entry_safe(r, safe, &ls->ls_rsbtbl[i].toss, res_hashchain) { if (dlm_no_directory(ls) || !is_master(r)) { @@ -783,7 +783,7 @@ void dlm_clear_toss_list(struct dlm_ls *ls) dlm_free_rsb(r); } } - spin_unlock(&ls->ls_rsbtbl[i].lock); + write_unlock(&ls->ls_rsbtbl[i].lock); } } diff --git a/trunk/fs/select.c b/trunk/fs/select.c index b0cf1f0896d9..08b91beed806 100644 --- a/trunk/fs/select.c +++ b/trunk/fs/select.c @@ -610,7 +610,7 @@ asmlinkage long sys_pselect7(int n, fd_set __user *inp, fd_set __user *outp, sigprocmask(SIG_SETMASK, &ksigmask, &sigsaved); } - ret = core_sys_select(n, inp, outp, exp, to); + ret = core_sys_select(n, inp, outp, exp, &end_time); ret = poll_select_copy_remaining(&end_time, tsp, 0, ret); if (ret == -ERESTARTNOHAND) { diff --git a/trunk/include/asm-generic/pgtable.h b/trunk/include/asm-generic/pgtable.h index 8e6d0ca70aba..72ebe91005a8 100644 --- a/trunk/include/asm-generic/pgtable.h +++ b/trunk/include/asm-generic/pgtable.h @@ -301,7 +301,7 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm, * track_pfn_vma_new is called when a _new_ pfn mapping is being established * for physical range indicated by pfn and size. */ -static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot, +static inline int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, unsigned long pfn, unsigned long size) { return 0; @@ -332,7 +332,7 @@ static inline void untrack_pfn_vma(struct vm_area_struct *vma, { } #else -extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot, +extern int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t prot, unsigned long pfn, unsigned long size); extern int track_pfn_vma_copy(struct vm_area_struct *vma); extern void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn, diff --git a/trunk/include/asm-m68k/unistd.h b/trunk/include/asm-m68k/unistd.h index 3c19027331fa..965abb8bc7ff 100644 --- a/trunk/include/asm-m68k/unistd.h +++ b/trunk/include/asm-m68k/unistd.h @@ -5,7 +5,6 @@ * This file contains the system call numbers. */ -#define __NR_restart_syscall 0 #define __NR_exit 1 #define __NR_fork 2 #define __NR_read 3 @@ -360,6 +359,9 @@ #define __ARCH_WANT_SYS_SIGPROCMASK #define __ARCH_WANT_SYS_RT_SIGACTION +/* whitelist for checksyscalls */ +#define __IGNORE_restart_syscall + /* * "Conditional" syscalls * diff --git a/trunk/include/linux/dio.h b/trunk/include/linux/dio.h index b2dd31ca1710..1e65ebc2a3db 100644 --- a/trunk/include/linux/dio.h +++ b/trunk/include/linux/dio.h @@ -241,7 +241,7 @@ struct dio_driver { extern int dio_find(int deviceid); extern unsigned long dio_scodetophysaddr(int scode); -extern int dio_create_sysfs_dev_files(struct dio_dev *); +extern void dio_create_sysfs_dev_files(struct dio_dev *); /* New-style probing */ extern int dio_register_driver(struct dio_driver *); diff --git a/trunk/include/linux/dmaengine.h b/trunk/include/linux/dmaengine.h index c73f1e2b59b7..64dea2ab326c 100644 --- a/trunk/include/linux/dmaengine.h +++ b/trunk/include/linux/dmaengine.h @@ -270,18 +270,8 @@ struct dma_device { /* --- public DMA engine API --- */ -#ifdef CONFIG_DMA_ENGINE void dmaengine_get(void); void dmaengine_put(void); -#else -static inline void dmaengine_get(void) -{ -} -static inline void dmaengine_put(void) -{ -} -#endif - dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest, void *src, size_t len); dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, diff --git a/trunk/include/linux/mISDNif.h b/trunk/include/linux/mISDNif.h index 5da3d95b27f1..557477ac3d5b 100644 --- a/trunk/include/linux/mISDNif.h +++ b/trunk/include/linux/mISDNif.h @@ -559,10 +559,7 @@ extern void mISDN_unregister_clock(struct mISDNclock *); static inline struct mISDNdevice *dev_to_mISDN(struct device *dev) { - if (dev) - return dev_get_drvdata(dev); - else - return NULL; + return dev_get_drvdata(dev); } extern void set_channel_address(struct mISDNchannel *, u_int, u_int); diff --git a/trunk/include/linux/mfd/pcf50633/adc.h b/trunk/include/linux/mfd/pcf50633/adc.h deleted file mode 100644 index 56669b4183ad..000000000000 --- a/trunk/include/linux/mfd/pcf50633/adc.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * adc.h -- Driver for NXP PCF50633 ADC - * - * (C) 2006-2008 by Openmoko, Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __LINUX_MFD_PCF50633_ADC_H -#define __LINUX_MFD_PCF50633_ADC_H - -#include -#include - -/* ADC Registers */ -#define PCF50633_REG_ADCC3 0x52 -#define PCF50633_REG_ADCC2 0x53 -#define PCF50633_REG_ADCC1 0x54 -#define PCF50633_REG_ADCS1 0x55 -#define PCF50633_REG_ADCS2 0x56 -#define PCF50633_REG_ADCS3 0x57 - -#define PCF50633_ADCC1_ADCSTART 0x01 -#define PCF50633_ADCC1_RES_10BIT 0x02 -#define PCF50633_ADCC1_AVERAGE_NO 0x00 -#define PCF50633_ADCC1_AVERAGE_4 0x04 -#define PCF50633_ADCC1_AVERAGE_8 0x08 -#define PCF50633_ADCC1_AVERAGE_16 0x0c -#define PCF50633_ADCC1_MUX_BATSNS_RES 0x00 -#define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10 -#define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20 -#define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30 -#define PCF50633_ADCC1_MUX_BATTEMP 0x60 -#define PCF50633_ADCC1_MUX_ADCIN1 0x70 -#define PCF50633_ADCC1_AVERAGE_MASK 0x0c -#define PCF50633_ADCC1_ADCMUX_MASK 0xf0 - -#define PCF50633_ADCC2_RATIO_NONE 0x00 -#define PCF50633_ADCC2_RATIO_BATTEMP 0x01 -#define PCF50633_ADCC2_RATIO_ADCIN1 0x02 -#define PCF50633_ADCC2_RATIO_BOTH 0x03 -#define PCF50633_ADCC2_RATIOSETTL_100US 0x04 - -#define PCF50633_ADCC3_ACCSW_EN 0x01 -#define PCF50633_ADCC3_NTCSW_EN 0x04 -#define PCF50633_ADCC3_RES_DIV_TWO 0x10 -#define PCF50633_ADCC3_RES_DIV_THREE 0x00 - -#define PCF50633_ADCS3_REF_NTCSW 0x00 -#define PCF50633_ADCS3_REF_ACCSW 0x10 -#define PCF50633_ADCS3_REF_2V0 0x20 -#define PCF50633_ADCS3_REF_VISA 0x30 -#define PCF50633_ADCS3_REF_2V0_2 0x70 -#define PCF50633_ADCS3_ADCRDY 0x80 - -#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03 -#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c -#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2 -#define PCF50633_ASCS3_REF_MASK 0x70 - -extern int -pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, - void (*callback)(struct pcf50633 *, void *, int), - void *callback_param); -extern int -pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg); - -#endif /* __LINUX_PCF50633_ADC_H */ diff --git a/trunk/include/linux/mfd/pcf50633/core.h b/trunk/include/linux/mfd/pcf50633/core.h deleted file mode 100644 index 4455b212d75a..000000000000 --- a/trunk/include/linux/mfd/pcf50633/core.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * core.h -- Core driver for NXP PCF50633 - * - * (C) 2006-2008 by Openmoko, Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __LINUX_MFD_PCF50633_CORE_H -#define __LINUX_MFD_PCF50633_CORE_H - -#include -#include -#include -#include -#include - -struct pcf50633; - -#define PCF50633_NUM_REGULATORS 11 - -struct pcf50633_platform_data { - struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; - - char **batteries; - int num_batteries; - - /* Callbacks */ - void (*probe_done)(struct pcf50633 *); - void (*mbc_event_callback)(struct pcf50633 *, int); - void (*regulator_registered)(struct pcf50633 *, int); - void (*force_shutdown)(struct pcf50633 *); - - u8 resumers[5]; -}; - -struct pcf50633_subdev_pdata { - struct pcf50633 *pcf; -}; - -struct pcf50633_irq { - void (*handler) (int, void *); - void *data; -}; - -int pcf50633_register_irq(struct pcf50633 *pcf, int irq, - void (*handler) (int, void *), void *data); -int pcf50633_free_irq(struct pcf50633 *pcf, int irq); - -int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); -int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); -int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); - -int pcf50633_read_block(struct pcf50633 *, u8 reg, - int nr_regs, u8 *data); -int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, - int nr_regs, u8 *data); -u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); -int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); - -int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); -int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); - -/* Interrupt registers */ - -#define PCF50633_REG_INT1 0x02 -#define PCF50633_REG_INT2 0x03 -#define PCF50633_REG_INT3 0x04 -#define PCF50633_REG_INT4 0x05 -#define PCF50633_REG_INT5 0x06 - -#define PCF50633_REG_INT1M 0x07 -#define PCF50633_REG_INT2M 0x08 -#define PCF50633_REG_INT3M 0x09 -#define PCF50633_REG_INT4M 0x0a -#define PCF50633_REG_INT5M 0x0b - -enum { - /* Chip IRQs */ - PCF50633_IRQ_ADPINS, - PCF50633_IRQ_ADPREM, - PCF50633_IRQ_USBINS, - PCF50633_IRQ_USBREM, - PCF50633_IRQ_RESERVED1, - PCF50633_IRQ_RESERVED2, - PCF50633_IRQ_ALARM, - PCF50633_IRQ_SECOND, - PCF50633_IRQ_ONKEYR, - PCF50633_IRQ_ONKEYF, - PCF50633_IRQ_EXTON1R, - PCF50633_IRQ_EXTON1F, - PCF50633_IRQ_EXTON2R, - PCF50633_IRQ_EXTON2F, - PCF50633_IRQ_EXTON3R, - PCF50633_IRQ_EXTON3F, - PCF50633_IRQ_BATFULL, - PCF50633_IRQ_CHGHALT, - PCF50633_IRQ_THLIMON, - PCF50633_IRQ_THLIMOFF, - PCF50633_IRQ_USBLIMON, - PCF50633_IRQ_USBLIMOFF, - PCF50633_IRQ_ADCRDY, - PCF50633_IRQ_ONKEY1S, - PCF50633_IRQ_LOWSYS, - PCF50633_IRQ_LOWBAT, - PCF50633_IRQ_HIGHTMP, - PCF50633_IRQ_AUTOPWRFAIL, - PCF50633_IRQ_DWN1PWRFAIL, - PCF50633_IRQ_DWN2PWRFAIL, - PCF50633_IRQ_LEDPWRFAIL, - PCF50633_IRQ_LEDOVP, - PCF50633_IRQ_LDO1PWRFAIL, - PCF50633_IRQ_LDO2PWRFAIL, - PCF50633_IRQ_LDO3PWRFAIL, - PCF50633_IRQ_LDO4PWRFAIL, - PCF50633_IRQ_LDO5PWRFAIL, - PCF50633_IRQ_LDO6PWRFAIL, - PCF50633_IRQ_HCLDOPWRFAIL, - PCF50633_IRQ_HCLDOOVL, - - /* Always last */ - PCF50633_NUM_IRQ, -}; - -struct pcf50633 { - struct device *dev; - struct i2c_client *i2c_client; - - struct pcf50633_platform_data *pdata; - int irq; - struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; - struct work_struct irq_work; - struct mutex lock; - - u8 mask_regs[5]; - - u8 suspend_irq_masks[5]; - u8 resume_reason[5]; - int is_suspended; - - int onkey1s_held; - - struct platform_device *rtc_pdev; - struct platform_device *mbc_pdev; - struct platform_device *adc_pdev; - struct platform_device *input_pdev; - struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; -}; - -enum pcf50633_reg_int1 { - PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ - PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ - PCF50633_INT1_USBINS = 0x04, /* USB inserted */ - PCF50633_INT1_USBREM = 0x08, /* USB removed */ - /* reserved */ - PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ - PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ -}; - -enum pcf50633_reg_int2 { - PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ - PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ - PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ - PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ - PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ - PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ - PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ - PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ -}; - -enum pcf50633_reg_int3 { - PCF50633_INT3_BATFULL = 0x01, /* Battery full */ - PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ - PCF50633_INT3_THLIMON = 0x04, - PCF50633_INT3_THLIMOFF = 0x08, - PCF50633_INT3_USBLIMON = 0x10, - PCF50633_INT3_USBLIMOFF = 0x20, - PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ - PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ -}; - -enum pcf50633_reg_int4 { - PCF50633_INT4_LOWSYS = 0x01, - PCF50633_INT4_LOWBAT = 0x02, - PCF50633_INT4_HIGHTMP = 0x04, - PCF50633_INT4_AUTOPWRFAIL = 0x08, - PCF50633_INT4_DWN1PWRFAIL = 0x10, - PCF50633_INT4_DWN2PWRFAIL = 0x20, - PCF50633_INT4_LEDPWRFAIL = 0x40, - PCF50633_INT4_LEDOVP = 0x80, -}; - -enum pcf50633_reg_int5 { - PCF50633_INT5_LDO1PWRFAIL = 0x01, - PCF50633_INT5_LDO2PWRFAIL = 0x02, - PCF50633_INT5_LDO3PWRFAIL = 0x04, - PCF50633_INT5_LDO4PWRFAIL = 0x08, - PCF50633_INT5_LDO5PWRFAIL = 0x10, - PCF50633_INT5_LDO6PWRFAIL = 0x20, - PCF50633_INT5_HCLDOPWRFAIL = 0x40, - PCF50633_INT5_HCLDOOVL = 0x80, -}; - -/* misc. registers */ -#define PCF50633_REG_OOCSHDWN 0x0c - -/* LED registers */ -#define PCF50633_REG_LEDOUT 0x28 -#define PCF50633_REG_LEDENA 0x29 -#define PCF50633_REG_LEDCTL 0x2a -#define PCF50633_REG_LEDDIM 0x2b - -#endif - diff --git a/trunk/include/linux/mfd/pcf50633/gpio.h b/trunk/include/linux/mfd/pcf50633/gpio.h deleted file mode 100644 index a42b845efc54..000000000000 --- a/trunk/include/linux/mfd/pcf50633/gpio.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * gpio.h -- GPIO driver for NXP PCF50633 - * - * (C) 2006-2008 by Openmoko, Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __LINUX_MFD_PCF50633_GPIO_H -#define __LINUX_MFD_PCF50633_GPIO_H - -#include - -#define PCF50633_GPIO1 1 -#define PCF50633_GPIO2 2 -#define PCF50633_GPIO3 3 -#define PCF50633_GPO 4 - -#define PCF50633_REG_GPIO1CFG 0x14 -#define PCF50633_REG_GPIO2CFG 0x15 -#define PCF50633_REG_GPIO3CFG 0x16 -#define PCF50633_REG_GPOCFG 0x17 - -#define PCF50633_GPOCFG_GPOSEL_MASK 0x07 - -enum pcf50633_reg_gpocfg { - PCF50633_GPOCFG_GPOSEL_0 = 0x00, - PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01, - PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02, - PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03, - PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04, - PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05, - PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06, - PCF50633_GPOCFG_GPOSEL_1 = 0x07, - PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08, -}; - -int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val); -u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio); - -int pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert); -int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio); - -int pcf50633_gpio_power_supply_set(struct pcf50633 *, - int gpio, int regulator, int on); -#endif /* __LINUX_MFD_PCF50633_GPIO_H */ - - diff --git a/trunk/include/linux/mfd/pcf50633/mbc.h b/trunk/include/linux/mfd/pcf50633/mbc.h deleted file mode 100644 index 6e17619b773a..000000000000 --- a/trunk/include/linux/mfd/pcf50633/mbc.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * mbc.h -- Driver for NXP PCF50633 Main Battery Charger - * - * (C) 2006-2008 by Openmoko, Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __LINUX_MFD_PCF50633_MBC_H -#define __LINUX_MFD_PCF50633_MBC_H - -#include -#include - -#define PCF50633_REG_MBCC1 0x43 -#define PCF50633_REG_MBCC2 0x44 -#define PCF50633_REG_MBCC3 0x45 -#define PCF50633_REG_MBCC4 0x46 -#define PCF50633_REG_MBCC5 0x47 -#define PCF50633_REG_MBCC6 0x48 -#define PCF50633_REG_MBCC7 0x49 -#define PCF50633_REG_MBCC8 0x4a -#define PCF50633_REG_MBCS1 0x4b -#define PCF50633_REG_MBCS2 0x4c -#define PCF50633_REG_MBCS3 0x4d - -enum pcf50633_reg_mbcc1 { - PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */ - PCF50633_MBCC1_AUTOSTOP = 0x02, - PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */ - PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */ - PCF50633_MBCC1_RESTART = 0x10, /* restart charging */ - PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */ - PCF50633_MBCC1_WDTIME_1H = 0x00, - PCF50633_MBCC1_WDTIME_2H = 0x40, - PCF50633_MBCC1_WDTIME_4H = 0x80, - PCF50633_MBCC1_WDTIME_6H = 0xc0, -}; -#define PCF50633_MBCC1_WDTIME_MASK 0xc0 - -enum pcf50633_reg_mbcc2 { - PCF50633_MBCC2_VBATCOND_2V7 = 0x00, - PCF50633_MBCC2_VBATCOND_2V85 = 0x01, - PCF50633_MBCC2_VBATCOND_3V0 = 0x02, - PCF50633_MBCC2_VBATCOND_3V15 = 0x03, - PCF50633_MBCC2_VMAX_4V = 0x00, - PCF50633_MBCC2_VMAX_4V20 = 0x28, - PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */ -}; - -enum pcf50633_reg_mbcc7 { - PCF50633_MBCC7_USB_100mA = 0x00, - PCF50633_MBCC7_USB_500mA = 0x01, - PCF50633_MBCC7_USB_1000mA = 0x02, - PCF50633_MBCC7_USB_SUSPEND = 0x03, - PCF50633_MBCC7_BATTEMP_EN = 0x04, - PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00, - PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40, - PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80, - PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0, -}; -#define PCF50633_MBCC7_USB_MASK 0x03 - -enum pcf50633_reg_mbcc8 { - PCF50633_MBCC8_USBENASUS = 0x10, -}; - -enum pcf50633_reg_mbcs1 { - PCF50633_MBCS1_USBPRES = 0x01, - PCF50633_MBCS1_USBOK = 0x02, - PCF50633_MBCS1_ADAPTPRES = 0x04, - PCF50633_MBCS1_ADAPTOK = 0x08, - PCF50633_MBCS1_TBAT_OK = 0x00, - PCF50633_MBCS1_TBAT_ABOVE = 0x10, - PCF50633_MBCS1_TBAT_BELOW = 0x20, - PCF50633_MBCS1_TBAT_UNDEF = 0x30, - PCF50633_MBCS1_PREWDTEXP = 0x40, - PCF50633_MBCS1_WDTEXP = 0x80, -}; - -enum pcf50633_reg_mbcs2_mbcmod { - PCF50633_MBCS2_MBC_PLAY = 0x00, - PCF50633_MBCS2_MBC_USB_PRE = 0x01, - PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02, - PCF50633_MBCS2_MBC_USB_FAST = 0x03, - PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04, - PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05, - PCF50633_MBCS2_MBC_ADP_PRE = 0x06, - PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07, - PCF50633_MBCS2_MBC_ADP_FAST = 0x08, - PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09, - PCF50633_MBCS2_MBC_BAT_FULL = 0x0a, - PCF50633_MBCS2_MBC_HALT = 0x0b, -}; -#define PCF50633_MBCS2_MBC_MASK 0x0f -enum pcf50633_reg_mbcs2_chgstat { - PCF50633_MBCS2_CHGS_NONE = 0x00, - PCF50633_MBCS2_CHGS_ADAPTER = 0x10, - PCF50633_MBCS2_CHGS_USB = 0x20, - PCF50633_MBCS2_CHGS_BOTH = 0x30, -}; -#define PCF50633_MBCS2_RESSTAT_AUTO 0x40 - -enum pcf50633_reg_mbcs3 { - PCF50633_MBCS3_USBLIM_PLAY = 0x01, - PCF50633_MBCS3_USBLIM_CGH = 0x02, - PCF50633_MBCS3_TLIM_PLAY = 0x04, - PCF50633_MBCS3_TLIM_CHG = 0x08, - PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */ - PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */ - PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */ - PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */ -}; - -#define PCF50633_MBCC2_VBATCOND_MASK 0x03 -#define PCF50633_MBCC2_VMAX_MASK 0x3c - -/* Charger status */ -#define PCF50633_MBC_USB_ONLINE 0x01 -#define PCF50633_MBC_USB_ACTIVE 0x02 -#define PCF50633_MBC_ADAPTER_ONLINE 0x04 -#define PCF50633_MBC_ADAPTER_ACTIVE 0x08 - -int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma); - -int pcf50633_mbc_get_status(struct pcf50633 *); -void pcf50633_mbc_set_status(struct pcf50633 *, int what, int status); - -#endif - diff --git a/trunk/include/linux/mfd/pcf50633/pmic.h b/trunk/include/linux/mfd/pcf50633/pmic.h deleted file mode 100644 index 2d3dbe53b235..000000000000 --- a/trunk/include/linux/mfd/pcf50633/pmic.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef __LINUX_MFD_PCF50633_PMIC_H -#define __LINUX_MFD_PCF50633_PMIC_H - -#include -#include - -#define PCF50633_REG_AUTOOUT 0x1a -#define PCF50633_REG_AUTOENA 0x1b -#define PCF50633_REG_AUTOCTL 0x1c -#define PCF50633_REG_AUTOMXC 0x1d -#define PCF50633_REG_DOWN1OUT 0x1e -#define PCF50633_REG_DOWN1ENA 0x1f -#define PCF50633_REG_DOWN1CTL 0x20 -#define PCF50633_REG_DOWN1MXC 0x21 -#define PCF50633_REG_DOWN2OUT 0x22 -#define PCF50633_REG_DOWN2ENA 0x23 -#define PCF50633_REG_DOWN2CTL 0x24 -#define PCF50633_REG_DOWN2MXC 0x25 -#define PCF50633_REG_MEMLDOOUT 0x26 -#define PCF50633_REG_MEMLDOENA 0x27 -#define PCF50633_REG_LDO1OUT 0x2d -#define PCF50633_REG_LDO1ENA 0x2e -#define PCF50633_REG_LDO2OUT 0x2f -#define PCF50633_REG_LDO2ENA 0x30 -#define PCF50633_REG_LDO3OUT 0x31 -#define PCF50633_REG_LDO3ENA 0x32 -#define PCF50633_REG_LDO4OUT 0x33 -#define PCF50633_REG_LDO4ENA 0x34 -#define PCF50633_REG_LDO5OUT 0x35 -#define PCF50633_REG_LDO5ENA 0x36 -#define PCF50633_REG_LDO6OUT 0x37 -#define PCF50633_REG_LDO6ENA 0x38 -#define PCF50633_REG_HCLDOOUT 0x39 -#define PCF50633_REG_HCLDOENA 0x3a -#define PCF50633_REG_HCLDOOVL 0x40 - -enum pcf50633_regulator_enable { - PCF50633_REGULATOR_ON = 0x01, - PCF50633_REGULATOR_ON_GPIO1 = 0x02, - PCF50633_REGULATOR_ON_GPIO2 = 0x04, - PCF50633_REGULATOR_ON_GPIO3 = 0x08, -}; -#define PCF50633_REGULATOR_ON_MASK 0x0f - -enum pcf50633_regulator_phase { - PCF50633_REGULATOR_ACTPH1 = 0x00, - PCF50633_REGULATOR_ACTPH2 = 0x10, - PCF50633_REGULATOR_ACTPH3 = 0x20, - PCF50633_REGULATOR_ACTPH4 = 0x30, -}; -#define PCF50633_REGULATOR_ACTPH_MASK 0x30 - -enum pcf50633_regulator_id { - PCF50633_REGULATOR_AUTO, - PCF50633_REGULATOR_DOWN1, - PCF50633_REGULATOR_DOWN2, - PCF50633_REGULATOR_LDO1, - PCF50633_REGULATOR_LDO2, - PCF50633_REGULATOR_LDO3, - PCF50633_REGULATOR_LDO4, - PCF50633_REGULATOR_LDO5, - PCF50633_REGULATOR_LDO6, - PCF50633_REGULATOR_HCLDO, - PCF50633_REGULATOR_MEMLDO, -}; -#endif - diff --git a/trunk/include/linux/smp.h b/trunk/include/linux/smp.h index 715196b09d67..b82466968101 100644 --- a/trunk/include/linux/smp.h +++ b/trunk/include/linux/smp.h @@ -24,9 +24,6 @@ struct call_single_data { /* total number of cpus in this system (may exceed NR_CPUS) */ extern unsigned int total_cpus; -int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, - int wait); - #ifdef CONFIG_SMP #include @@ -82,6 +79,8 @@ smp_call_function_mask(cpumask_t mask, void(*func)(void *info), void *info, return 0; } +int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, + int wait); void __smp_call_function_single(int cpuid, struct call_single_data *data); /* @@ -141,6 +140,14 @@ static inline int up_smp_call_function(void (*func)(void *), void *info) static inline void smp_send_reschedule(int cpu) { } #define num_booting_cpus() 1 #define smp_prepare_boot_cpu() do {} while (0) +#define smp_call_function_single(cpuid, func, info, wait) \ +({ \ + WARN_ON(cpuid != 0); \ + local_irq_disable(); \ + (func)(info); \ + local_irq_enable(); \ + 0; \ +}) #define smp_call_function_mask(mask, func, info, wait) \ (up_smp_call_function(func, info)) #define smp_call_function_many(mask, func, info, wait) \ diff --git a/trunk/include/net/wimax.h b/trunk/include/net/wimax.h index 6b3824edb39e..073809ce94f8 100644 --- a/trunk/include/net/wimax.h +++ b/trunk/include/net/wimax.h @@ -323,8 +323,8 @@ struct input_dev; * * @rf_hw: [private] State of the hardware radio switch (OFF/ON) * - * @debugfs_dentry: [private] Used to hook up a debugfs entry. This - * shows up in the debugfs root as wimax\:DEVICENAME. + * @debufs_dentry: [private] Used to hook up a debugfs entry. This + * shows up in the debugfs root as wimax:DEVICENAME. * * Description: * This structure defines a common interface to access all WiMAX diff --git a/trunk/include/sound/soc-dapm.h b/trunk/include/sound/soc-dapm.h index 93a4edb148b5..4af1083e3287 100644 --- a/trunk/include/sound/soc-dapm.h +++ b/trunk/include/sound/soc-dapm.h @@ -178,7 +178,7 @@ .private_value = (unsigned long)&xenum } #define SOC_DAPM_VALUE_ENUM(xname, xenum) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ - .info = snd_soc_info_enum_double, \ + .info = snd_soc_info_value_enum_double, \ .get = snd_soc_dapm_get_value_enum_double, \ .put = snd_soc_dapm_put_value_enum_double, \ .private_value = (unsigned long)&xenum } diff --git a/trunk/include/sound/soc.h b/trunk/include/sound/soc.h index 24593ac3ea19..9b930d342116 100644 --- a/trunk/include/sound/soc.h +++ b/trunk/include/sound/soc.h @@ -106,7 +106,7 @@ .private_value = (unsigned long)&xenum } #define SOC_VALUE_ENUM(xname, xenum) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ - .info = snd_soc_info_enum_double, \ + .info = snd_soc_info_value_enum_double, \ .get = snd_soc_get_value_enum_double, \ .put = snd_soc_put_value_enum_double, \ .private_value = (unsigned long)&xenum } @@ -211,6 +211,8 @@ int snd_soc_get_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_value_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); int snd_soc_get_value_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_put_value_enum_double(struct snd_kcontrol *kcontrol, @@ -412,6 +414,17 @@ struct soc_mixer_control { /* enumerated kcontrol */ struct soc_enum { + unsigned short reg; + unsigned short reg2; + unsigned char shift_l; + unsigned char shift_r; + unsigned int max; + const char **texts; + void *dapm; +}; + +/* semi enumerated kcontrol */ +struct soc_value_enum { unsigned short reg; unsigned short reg2; unsigned char shift_l; diff --git a/trunk/kernel/Makefile b/trunk/kernel/Makefile index 2aebc4cd7878..2921d90ce32f 100644 --- a/trunk/kernel/Makefile +++ b/trunk/kernel/Makefile @@ -40,11 +40,7 @@ obj-$(CONFIG_RT_MUTEXES) += rtmutex.o obj-$(CONFIG_DEBUG_RT_MUTEXES) += rtmutex-debug.o obj-$(CONFIG_RT_MUTEX_TESTER) += rtmutex-tester.o obj-$(CONFIG_GENERIC_ISA_DMA) += dma.o -ifeq ($(CONFIG_USE_GENERIC_SMP_HELPERS),y) -obj-y += smp.o -else -obj-y += up.o -endif +obj-$(CONFIG_USE_GENERIC_SMP_HELPERS) += smp.o obj-$(CONFIG_SMP) += spinlock.o obj-$(CONFIG_DEBUG_SPINLOCK) += spinlock.o obj-$(CONFIG_PROVE_LOCKING) += spinlock.o diff --git a/trunk/kernel/async.c b/trunk/kernel/async.c index 608b32b42812..f286e9f2b736 100644 --- a/trunk/kernel/async.c +++ b/trunk/kernel/async.c @@ -90,12 +90,12 @@ extern int initcall_debug; static async_cookie_t __lowest_in_progress(struct list_head *running) { struct async_entry *entry; - if (!list_empty(running)) { - entry = list_first_entry(running, + if (!list_empty(&async_pending)) { + entry = list_first_entry(&async_pending, struct async_entry, list); return entry->cookie; - } else if (!list_empty(&async_pending)) { - entry = list_first_entry(&async_pending, + } else if (!list_empty(running)) { + entry = list_first_entry(running, struct async_entry, list); return entry->cookie; } else { @@ -104,17 +104,6 @@ static async_cookie_t __lowest_in_progress(struct list_head *running) } } - -static async_cookie_t lowest_in_progress(struct list_head *running) -{ - unsigned long flags; - async_cookie_t ret; - - spin_lock_irqsave(&async_lock, flags); - ret = __lowest_in_progress(running); - spin_unlock_irqrestore(&async_lock, flags); - return ret; -} /* * pick the first pending entry and run it */ @@ -240,7 +229,7 @@ void async_synchronize_cookie_special(async_cookie_t cookie, struct list_head *r starttime = ktime_get(); } - wait_event(async_done, lowest_in_progress(running) >= cookie); + wait_event(async_done, __lowest_in_progress(running) >= cookie); if (initcall_debug && system_state == SYSTEM_BOOTING) { endtime = ktime_get(); diff --git a/trunk/kernel/rcutorture.c b/trunk/kernel/rcutorture.c index 7c4142a79f0a..1cff28db56b6 100644 --- a/trunk/kernel/rcutorture.c +++ b/trunk/kernel/rcutorture.c @@ -136,46 +136,28 @@ static int stutter_pause_test = 0; #endif int rcutorture_runnable = RCUTORTURE_RUNNABLE_INIT; -/* Mediate rmmod and system shutdown. Concurrent rmmod & shutdown illegal! */ - -#define FULLSTOP_DONTSTOP 0 /* Normal operation. */ -#define FULLSTOP_SHUTDOWN 1 /* System shutdown with rcutorture running. */ -#define FULLSTOP_RMMOD 2 /* Normal rmmod of rcutorture. */ -static int fullstop = FULLSTOP_RMMOD; -DEFINE_MUTEX(fullstop_mutex); /* Protect fullstop transitions and spawning */ - /* of kthreads. */ +#define FULLSTOP_SHUTDOWN 1 /* Bail due to system shutdown/panic. */ +#define FULLSTOP_CLEANUP 2 /* Orderly shutdown. */ +static int fullstop; /* stop generating callbacks at test end. */ +DEFINE_MUTEX(fullstop_mutex); /* protect fullstop transitions and */ + /* spawning of kthreads. */ /* - * Detect and respond to a system shutdown. + * Detect and respond to a signal-based shutdown. */ static int rcutorture_shutdown_notify(struct notifier_block *unused1, unsigned long unused2, void *unused3) { + if (fullstop) + return NOTIFY_DONE; mutex_lock(&fullstop_mutex); - if (fullstop == FULLSTOP_DONTSTOP) + if (!fullstop) fullstop = FULLSTOP_SHUTDOWN; - else - printk(KERN_WARNING /* but going down anyway, so... */ - "Concurrent 'rmmod rcutorture' and shutdown illegal!\n"); mutex_unlock(&fullstop_mutex); return NOTIFY_DONE; } -/* - * Absorb kthreads into a kernel function that won't return, so that - * they won't ever access module text or data again. - */ -static void rcutorture_shutdown_absorb(char *title) -{ - if (ACCESS_ONCE(fullstop) == FULLSTOP_SHUTDOWN) { - printk(KERN_NOTICE - "rcutorture thread %s parking due to system shutdown\n", - title); - schedule_timeout_uninterruptible(MAX_SCHEDULE_TIMEOUT); - } -} - /* * Allocate an element from the rcu_tortures pool. */ @@ -237,14 +219,13 @@ rcu_random(struct rcu_random_state *rrsp) } static void -rcu_stutter_wait(char *title) +rcu_stutter_wait(void) { - while (stutter_pause_test || !rcutorture_runnable) { + while ((stutter_pause_test || !rcutorture_runnable) && !fullstop) { if (rcutorture_runnable) schedule_timeout_interruptible(1); else schedule_timeout_interruptible(round_jiffies_relative(HZ)); - rcutorture_shutdown_absorb(title); } } @@ -306,7 +287,7 @@ rcu_torture_cb(struct rcu_head *p) int i; struct rcu_torture *rp = container_of(p, struct rcu_torture, rtort_rcu); - if (fullstop != FULLSTOP_DONTSTOP) { + if (fullstop) { /* Test is ending, just drop callbacks on the floor. */ /* The next initialization will pick up the pieces. */ return; @@ -638,11 +619,10 @@ rcu_torture_writer(void *arg) } rcu_torture_current_version++; oldbatch = cur_ops->completed(); - rcu_stutter_wait("rcu_torture_writer"); - } while (!kthread_should_stop() && fullstop == FULLSTOP_DONTSTOP); + rcu_stutter_wait(); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_writer task stopping"); - rcutorture_shutdown_absorb("rcu_torture_writer"); - while (!kthread_should_stop()) + while (!kthread_should_stop() && fullstop != FULLSTOP_SHUTDOWN) schedule_timeout_uninterruptible(1); return 0; } @@ -663,12 +643,11 @@ rcu_torture_fakewriter(void *arg) schedule_timeout_uninterruptible(1 + rcu_random(&rand)%10); udelay(rcu_random(&rand) & 0x3ff); cur_ops->sync(); - rcu_stutter_wait("rcu_torture_fakewriter"); - } while (!kthread_should_stop() && fullstop == FULLSTOP_DONTSTOP); + rcu_stutter_wait(); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_fakewriter task stopping"); - rcutorture_shutdown_absorb("rcu_torture_fakewriter"); - while (!kthread_should_stop()) + while (!kthread_should_stop() && fullstop != FULLSTOP_SHUTDOWN) schedule_timeout_uninterruptible(1); return 0; } @@ -773,13 +752,12 @@ rcu_torture_reader(void *arg) preempt_enable(); cur_ops->readunlock(idx); schedule(); - rcu_stutter_wait("rcu_torture_reader"); - } while (!kthread_should_stop() && fullstop == FULLSTOP_DONTSTOP); + rcu_stutter_wait(); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_reader task stopping"); - rcutorture_shutdown_absorb("rcu_torture_reader"); if (irqreader && cur_ops->irqcapable) del_timer_sync(&t); - while (!kthread_should_stop()) + while (!kthread_should_stop() && fullstop != FULLSTOP_SHUTDOWN) schedule_timeout_uninterruptible(1); return 0; } @@ -876,8 +854,7 @@ rcu_torture_stats(void *arg) do { schedule_timeout_interruptible(stat_interval * HZ); rcu_torture_stats_print(); - rcutorture_shutdown_absorb("rcu_torture_stats"); - } while (!kthread_should_stop()); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_stats task stopping"); return 0; } @@ -889,49 +866,52 @@ static int rcu_idle_cpu; /* Force all torture tasks off this CPU */ */ static void rcu_torture_shuffle_tasks(void) { - cpumask_t tmp_mask; + cpumask_var_t tmp_mask; int i; - cpus_setall(tmp_mask); + if (!alloc_cpumask_var(&tmp_mask, GFP_KERNEL)) + BUG(); + + cpumask_setall(tmp_mask); get_online_cpus(); /* No point in shuffling if there is only one online CPU (ex: UP) */ - if (num_online_cpus() == 1) { - put_online_cpus(); - return; - } + if (num_online_cpus() == 1) + goto out; if (rcu_idle_cpu != -1) - cpu_clear(rcu_idle_cpu, tmp_mask); + cpumask_clear_cpu(rcu_idle_cpu, tmp_mask); - set_cpus_allowed_ptr(current, &tmp_mask); + set_cpus_allowed_ptr(current, tmp_mask); if (reader_tasks) { for (i = 0; i < nrealreaders; i++) if (reader_tasks[i]) set_cpus_allowed_ptr(reader_tasks[i], - &tmp_mask); + tmp_mask); } if (fakewriter_tasks) { for (i = 0; i < nfakewriters; i++) if (fakewriter_tasks[i]) set_cpus_allowed_ptr(fakewriter_tasks[i], - &tmp_mask); + tmp_mask); } if (writer_task) - set_cpus_allowed_ptr(writer_task, &tmp_mask); + set_cpus_allowed_ptr(writer_task, tmp_mask); if (stats_task) - set_cpus_allowed_ptr(stats_task, &tmp_mask); + set_cpus_allowed_ptr(stats_task, tmp_mask); if (rcu_idle_cpu == -1) rcu_idle_cpu = num_online_cpus() - 1; else rcu_idle_cpu--; +out: put_online_cpus(); + free_cpumask_var(tmp_mask); } /* Shuffle tasks across CPUs, with the intent of allowing each CPU in the @@ -945,8 +925,7 @@ rcu_torture_shuffle(void *arg) do { schedule_timeout_interruptible(shuffle_interval * HZ); rcu_torture_shuffle_tasks(); - rcutorture_shutdown_absorb("rcu_torture_shuffle"); - } while (!kthread_should_stop()); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_shuffle task stopping"); return 0; } @@ -961,11 +940,10 @@ rcu_torture_stutter(void *arg) do { schedule_timeout_interruptible(stutter * HZ); stutter_pause_test = 1; - if (!kthread_should_stop()) + if (!kthread_should_stop() && !fullstop) schedule_timeout_interruptible(stutter * HZ); stutter_pause_test = 0; - rcutorture_shutdown_absorb("rcu_torture_stutter"); - } while (!kthread_should_stop()); + } while (!kthread_should_stop() && !fullstop); VERBOSE_PRINTK_STRING("rcu_torture_stutter task stopping"); return 0; } @@ -992,16 +970,15 @@ rcu_torture_cleanup(void) int i; mutex_lock(&fullstop_mutex); - if (fullstop == FULLSTOP_SHUTDOWN) { - printk(KERN_WARNING /* but going down anyway, so... */ - "Concurrent 'rmmod rcutorture' and shutdown illegal!\n"); + if (!fullstop) { + /* If being signaled, let it happen, then exit. */ mutex_unlock(&fullstop_mutex); - schedule_timeout_uninterruptible(10); + schedule_timeout_interruptible(10 * HZ); if (cur_ops->cb_barrier != NULL) cur_ops->cb_barrier(); return; } - fullstop = FULLSTOP_RMMOD; + fullstop = FULLSTOP_CLEANUP; mutex_unlock(&fullstop_mutex); unregister_reboot_notifier(&rcutorture_nb); if (stutter_task) { @@ -1101,7 +1078,7 @@ rcu_torture_init(void) else nrealreaders = 2 * num_online_cpus(); rcu_torture_print_module_parms("Start of test"); - fullstop = FULLSTOP_DONTSTOP; + fullstop = 0; /* Set up the freelist. */ diff --git a/trunk/kernel/sched.c b/trunk/kernel/sched.c index 8be2c13b50d0..deb5ac8c12f3 100644 --- a/trunk/kernel/sched.c +++ b/trunk/kernel/sched.c @@ -125,9 +125,6 @@ DEFINE_TRACE(sched_switch); DEFINE_TRACE(sched_migrate_task); #ifdef CONFIG_SMP - -static void double_rq_lock(struct rq *rq1, struct rq *rq2); - /* * Divide a load by a sched group cpu_power : (load / sg->__cpu_power) * Since cpu_power is a 'constant', we can use a reciprocal divide. @@ -7285,10 +7282,10 @@ cpu_to_phys_group(int cpu, const struct cpumask *cpu_map, * groups, so roll our own. Now each node has its own list of groups which * gets dynamically allocated. */ -static DEFINE_PER_CPU(struct static_sched_domain, node_domains); +static DEFINE_PER_CPU(struct sched_domain, node_domains); static struct sched_group ***sched_group_nodes_bycpu; -static DEFINE_PER_CPU(struct static_sched_domain, allnodes_domains); +static DEFINE_PER_CPU(struct sched_domain, allnodes_domains); static DEFINE_PER_CPU(struct static_sched_group, sched_group_allnodes); static int cpu_to_allnodes_group(int cpu, const struct cpumask *cpu_map, @@ -7563,7 +7560,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, #ifdef CONFIG_NUMA if (cpumask_weight(cpu_map) > SD_NODES_PER_DOMAIN*cpumask_weight(nodemask)) { - sd = &per_cpu(allnodes_domains, i).sd; + sd = &per_cpu(allnodes_domains, i); SD_INIT(sd, ALLNODES); set_domain_attribute(sd, attr); cpumask_copy(sched_domain_span(sd), cpu_map); @@ -7573,7 +7570,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, } else p = NULL; - sd = &per_cpu(node_domains, i).sd; + sd = &per_cpu(node_domains, i); SD_INIT(sd, NODE); set_domain_attribute(sd, attr); sched_domain_node_span(cpu_to_node(i), sched_domain_span(sd)); @@ -7691,7 +7688,7 @@ static int __build_sched_domains(const struct cpumask *cpu_map, for_each_cpu(j, nodemask) { struct sched_domain *sd; - sd = &per_cpu(node_domains, j).sd; + sd = &per_cpu(node_domains, j); sd->groups = sg; } sg->__cpu_power = 0; diff --git a/trunk/kernel/sched_debug.c b/trunk/kernel/sched_debug.c index 16eeba4e4169..4293cfa9681d 100644 --- a/trunk/kernel/sched_debug.c +++ b/trunk/kernel/sched_debug.c @@ -145,19 +145,6 @@ static void print_rq(struct seq_file *m, struct rq *rq, int rq_cpu) read_unlock_irqrestore(&tasklist_lock, flags); } -#if defined(CONFIG_CGROUP_SCHED) && \ - (defined(CONFIG_FAIR_GROUP_SCHED) || defined(CONFIG_RT_GROUP_SCHED)) -static void task_group_path(struct task_group *tg, char *buf, int buflen) -{ - /* may be NULL if the underlying cgroup isn't fully-created yet */ - if (!tg->css.cgroup) { - buf[0] = '\0'; - return; - } - cgroup_path(tg->css.cgroup, buf, buflen); -} -#endif - void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) { s64 MIN_vruntime = -1, min_vruntime, max_vruntime = -1, @@ -167,10 +154,10 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) unsigned long flags; #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) - char path[128]; + char path[128] = ""; struct task_group *tg = cfs_rq->tg; - task_group_path(tg, path, sizeof(path)); + cgroup_path(tg->css.cgroup, path, sizeof(path)); SEQ_printf(m, "\ncfs_rq[%d]:%s\n", cpu, path); #elif defined(CONFIG_USER_SCHED) && defined(CONFIG_FAIR_GROUP_SCHED) @@ -221,10 +208,10 @@ void print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq) void print_rt_rq(struct seq_file *m, int cpu, struct rt_rq *rt_rq) { #if defined(CONFIG_CGROUP_SCHED) && defined(CONFIG_RT_GROUP_SCHED) - char path[128]; + char path[128] = ""; struct task_group *tg = rt_rq->tg; - task_group_path(tg, path, sizeof(path)); + cgroup_path(tg->css.cgroup, path, sizeof(path)); SEQ_printf(m, "\nrt_rq[%d]:%s\n", cpu, path); #else diff --git a/trunk/kernel/up.c b/trunk/kernel/up.c deleted file mode 100644 index 1ff27a28bb7d..000000000000 --- a/trunk/kernel/up.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Uniprocessor-only support functions. The counterpart to kernel/smp.c - */ - -#include -#include -#include -#include - -int smp_call_function_single(int cpu, void (*func) (void *info), void *info, - int wait) -{ - WARN_ON(cpu != 0); - - local_irq_disable(); - (func)(info); - local_irq_enable(); - - return 0; -} -EXPORT_SYMBOL(smp_call_function_single); diff --git a/trunk/mm/memory.c b/trunk/mm/memory.c index 22bfa7a47a0b..e009ce870859 100644 --- a/trunk/mm/memory.c +++ b/trunk/mm/memory.c @@ -1511,7 +1511,6 @@ int vm_insert_pfn(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) { int ret; - pgprot_t pgprot = vma->vm_page_prot; /* * Technically, architectures with pte_special can avoid all these * restrictions (same for remap_pfn_range). However we would like @@ -1526,10 +1525,10 @@ int vm_insert_pfn(struct vm_area_struct *vma, unsigned long addr, if (addr < vma->vm_start || addr >= vma->vm_end) return -EFAULT; - if (track_pfn_vma_new(vma, &pgprot, pfn, PAGE_SIZE)) + if (track_pfn_vma_new(vma, vma->vm_page_prot, pfn, PAGE_SIZE)) return -EINVAL; - ret = insert_pfn(vma, addr, pfn, pgprot); + ret = insert_pfn(vma, addr, pfn, vma->vm_page_prot); if (ret) untrack_pfn_vma(vma, pfn, PAGE_SIZE); @@ -1672,15 +1671,9 @@ int remap_pfn_range(struct vm_area_struct *vma, unsigned long addr, vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP; - err = track_pfn_vma_new(vma, &prot, pfn, PAGE_ALIGN(size)); - if (err) { - /* - * To indicate that track_pfn related cleanup is not - * needed from higher level routine calling unmap_vmas - */ - vma->vm_flags &= ~(VM_IO | VM_RESERVED | VM_PFNMAP); + err = track_pfn_vma_new(vma, prot, pfn, PAGE_ALIGN(size)); + if (err) return -EINVAL; - } BUG_ON(addr >= end); pfn -= addr >> PAGE_SHIFT; @@ -3172,15 +3165,6 @@ void print_vma_addr(char *prefix, unsigned long ip) #ifdef CONFIG_PROVE_LOCKING void might_fault(void) { - /* - * Some code (nfs/sunrpc) uses socket ops on kernel memory while - * holding the mmap_sem, this is safe because kernel memory doesn't - * get paged out, therefore we'll never actually fault, and the - * below annotations will generate false positives. - */ - if (segment_eq(get_fs(), KERNEL_DS)) - return; - might_sleep(); /* * it would be nicer only to annotate paths which are not under diff --git a/trunk/net/bridge/netfilter/ebtables.c b/trunk/net/bridge/netfilter/ebtables.c index 8a8743d7d6e7..fa108c46e851 100644 --- a/trunk/net/bridge/netfilter/ebtables.c +++ b/trunk/net/bridge/netfilter/ebtables.c @@ -85,13 +85,12 @@ static inline int ebt_do_match (struct ebt_entry_match *m, static inline int ebt_dev_check(char *entry, const struct net_device *device) { int i = 0; - const char *devname; + const char *devname = device->name; if (*entry == '\0') return 0; if (!device) return 1; - devname = device->name; /* 1 is the wildcard token */ while (entry[i] != '\0' && entry[i] != 1 && entry[i] == devname[i]) i++; diff --git a/trunk/net/core/dev.c b/trunk/net/core/dev.c index b715a55cccc4..5f736f1ceeae 100644 --- a/trunk/net/core/dev.c +++ b/trunk/net/core/dev.c @@ -1087,11 +1087,6 @@ int dev_open(struct net_device *dev) */ dev->flags |= IFF_UP; - /* - * Enable NET_DMA - */ - dmaengine_get(); - /* * Initialize multicasting status */ @@ -1169,11 +1164,6 @@ int dev_close(struct net_device *dev) */ call_netdevice_notifiers(NETDEV_DOWN, dev); - /* - * Shutdown NET_DMA - */ - dmaengine_put(); - return 0; } @@ -5161,6 +5151,9 @@ static int __init net_dev_init(void) hotcpu_notifier(dev_cpu_callback, 0); dst_init(); dev_mcast_init(); + #ifdef CONFIG_NET_DMA + dmaengine_get(); + #endif rc = 0; out: return rc; diff --git a/trunk/net/dccp/ccids/Kconfig b/trunk/net/dccp/ccids/Kconfig index 4b5db44970aa..b28bf962edc3 100644 --- a/trunk/net/dccp/ccids/Kconfig +++ b/trunk/net/dccp/ccids/Kconfig @@ -29,7 +29,7 @@ config IP_DCCP_CCID3 http://www.ietf.org/rfc/rfc4342.txt The TFRC congestion control algorithms were initially described in - RFC 5348. + RFC 5448. This text was extracted from RFC 4340 (sec. 10.2), http://www.ietf.org/rfc/rfc4340.txt diff --git a/trunk/net/dccp/ccids/lib/tfrc.c b/trunk/net/dccp/ccids/lib/tfrc.c index 4902029854d8..60c412ccfeef 100644 --- a/trunk/net/dccp/ccids/lib/tfrc.c +++ b/trunk/net/dccp/ccids/lib/tfrc.c @@ -36,7 +36,7 @@ int __init tfrc_lib_init(void) return rc; } -void tfrc_lib_exit(void) +void __exit tfrc_lib_exit(void) { tfrc_rx_packet_history_exit(); tfrc_tx_packet_history_exit(); diff --git a/trunk/net/tipc/bcast.h b/trunk/net/tipc/bcast.h index 2f2d731bc1c2..5aa024b99c55 100644 --- a/trunk/net/tipc/bcast.h +++ b/trunk/net/tipc/bcast.h @@ -124,7 +124,7 @@ static inline int tipc_nmap_equal(struct tipc_node_map *nm_a, struct tipc_node_m static inline void tipc_nmap_diff(struct tipc_node_map *nm_a, struct tipc_node_map *nm_b, struct tipc_node_map *nm_diff) { - int stop = ARRAY_SIZE(nm_a->map); + int stop = sizeof(nm_a->map) / sizeof(u32); int w; int b; u32 map; diff --git a/trunk/net/xfrm/xfrm_ipcomp.c b/trunk/net/xfrm/xfrm_ipcomp.c index 42cd18391f46..c609a4b98e15 100644 --- a/trunk/net/xfrm/xfrm_ipcomp.c +++ b/trunk/net/xfrm/xfrm_ipcomp.c @@ -63,6 +63,7 @@ static int ipcomp_decompress(struct xfrm_state *x, struct sk_buff *skb) if (len > skb_tailroom(skb)) len = skb_tailroom(skb); + skb->truesize += len; __skb_put(skb, len); len += plen; diff --git a/trunk/scripts/markup_oops.pl b/trunk/scripts/markup_oops.pl index d40449cafa84..700a7a654a3f 100644 --- a/trunk/scripts/markup_oops.pl +++ b/trunk/scripts/markup_oops.pl @@ -1,7 +1,5 @@ #!/usr/bin/perl -w -use File::Basename; - # Copyright 2008, Intel Corporation # # This file is part of the Linux kernel @@ -15,41 +13,23 @@ my $vmlinux_name = $ARGV[0]; -if (!defined($vmlinux_name)) { - my $kerver = `uname -r`; - chomp($kerver); - $vmlinux_name = "/lib/modules/$kerver/build/vmlinux"; - print "No vmlinux specified, assuming $vmlinux_name\n"; -} -my $filename = $vmlinux_name; + # # Step 1: Parse the oops to find the EIP value # my $target = "0"; -my $function; -my $module = ""; -my $func_offset; -my $vmaoffset = 0; - while () { - my $line = $_; - if ($line =~ /EIP: 0060:\[\<([a-z0-9]+)\>\]/) { + if ($_ =~ /EIP: 0060:\[\<([a-z0-9]+)\>\]/) { $target = $1; } - if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]/) { - $function = $1; - $func_offset = $2; - } +} - # check if it's a module - if ($line =~ /EIP is at ([a-zA-Z0-9\_]+)\+(0x[0-9a-f]+)\/0x[a-f0-9]+\W\[([a-zA-Z0-9\_\-]+)\]/) { - $module = $3; - } +if ($target =~ /^f8/) { + print "This script does not work on modules ... \n"; + exit; } -my $decodestart = hex($target) - hex($func_offset); -my $decodestop = $decodestart + 8192; if ($target eq "0") { print "No oops found!\n"; print "Usage: \n"; @@ -57,29 +37,6 @@ exit; } -# if it's a module, we need to find the .ko file and calculate a load offset -if ($module ne "") { - my $dir = dirname($filename); - $dir = $dir . "/"; - my $mod = $module . ".ko"; - my $modulefile = `find $dir -name $mod | head -1`; - chomp($modulefile); - $filename = $modulefile; - if ($filename eq "") { - print "Module .ko file for $module not found. Aborting\n"; - exit; - } - # ok so we found the module, now we need to calculate the vma offset - open(FILE, "objdump -dS $filename |") || die "Cannot start objdump"; - while () { - if ($_ =~ /^([0-9a-f]+) \<$function\>\:/) { - my $fu = $1; - $vmaoffset = hex($target) - hex($fu) - hex($func_offset); - } - } - close(FILE); -} - my $counter = 0; my $state = 0; my $center = 0; @@ -102,7 +59,9 @@ sub InRange { # first, parse the input into the lines array, but to keep size down, # we only do this for 4Kb around the sweet spot -open(FILE, "objdump -dS --adjust-vma=$vmaoffset --start-address=$decodestart --stop-address=$decodestop $filename |") || die "Cannot start objdump"; +my $filename; + +open(FILE, "objdump -dS $vmlinux_name |") || die "Cannot start objdump"; while () { my $line = $_; diff --git a/trunk/sound/oss/dmasound/dmasound_atari.c b/trunk/sound/oss/dmasound/dmasound_atari.c index 57d9f154c88b..4d45bd63718b 100644 --- a/trunk/sound/oss/dmasound/dmasound_atari.c +++ b/trunk/sound/oss/dmasound/dmasound_atari.c @@ -851,9 +851,8 @@ static int __init AtaIrqInit(void) mfp.tim_dt_a = 1; /* Cause interrupt after first event. */ mfp.tim_ct_a = 8; /* Turn on event counting. */ /* Register interrupt handler. */ - if (request_irq(IRQ_MFP_TIMA, AtaInterrupt, IRQ_TYPE_SLOW, "DMA sound", - AtaInterrupt)) - return 0; + request_irq(IRQ_MFP_TIMA, AtaInterrupt, IRQ_TYPE_SLOW, "DMA sound", + AtaInterrupt); mfp.int_en_a |= 0x20; /* Turn interrupt on. */ mfp.int_mk_a |= 0x20; return 1; diff --git a/trunk/sound/oss/dmasound/dmasound_q40.c b/trunk/sound/oss/dmasound/dmasound_q40.c index 99bcb21c2281..1855b14d90c3 100644 --- a/trunk/sound/oss/dmasound/dmasound_q40.c +++ b/trunk/sound/oss/dmasound/dmasound_q40.c @@ -371,9 +371,8 @@ static void Q40Free(void *ptr, unsigned int size) static int __init Q40IrqInit(void) { /* Register interrupt handler. */ - if (request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, - "DMA sound", Q40Interrupt)) - return 0; + request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, + "DMA sound", Q40Interrupt); return(1); } @@ -402,7 +401,6 @@ static void Q40PlayNextFrame(int index) u_char *start; u_long size; u_char speed; - int error; /* used by Q40Play() if all doubts whether there really is something * to be played are already wiped out. @@ -421,13 +419,11 @@ static void Q40PlayNextFrame(int index) master_outb( 0,SAMPLE_ENABLE_REG); free_irq(Q40_IRQ_SAMPLE, Q40Interrupt); if (dmasound.soft.stereo) - error = request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, - "Q40 sound", Q40Interrupt); + request_irq(Q40_IRQ_SAMPLE, Q40StereoInterrupt, 0, + "Q40 sound", Q40Interrupt); else - error = request_irq(Q40_IRQ_SAMPLE, Q40MonoInterrupt, 0, - "Q40 sound", Q40Interrupt); - if (error && printk_ratelimit()) - pr_err("Couldn't register sound interrupt\n"); + request_irq(Q40_IRQ_SAMPLE, Q40MonoInterrupt, 0, + "Q40 sound", Q40Interrupt); master_outb( speed, SAMPLE_RATE_REG); master_outb( 1,SAMPLE_CLEAR_REG); diff --git a/trunk/sound/pci/hda/hda_beep.c b/trunk/sound/pci/hda/hda_beep.c index 960fd7970384..e00421c0d8ba 100644 --- a/trunk/sound/pci/hda/hda_beep.c +++ b/trunk/sound/pci/hda/hda_beep.c @@ -135,6 +135,7 @@ void snd_hda_detach_beep_device(struct hda_codec *codec) struct hda_beep *beep = codec->beep; if (beep) { cancel_work_sync(&beep->beep_work); + flush_scheduled_work(); input_unregister_device(beep->dev); kfree(beep); diff --git a/trunk/sound/pci/hda/hda_codec.c b/trunk/sound/pci/hda/hda_codec.c index 3c596da2b9b5..e16cf63821ae 100644 --- a/trunk/sound/pci/hda/hda_codec.c +++ b/trunk/sound/pci/hda/hda_codec.c @@ -373,7 +373,7 @@ int snd_hda_queue_unsol_event(struct hda_bus *bus, u32 res, u32 res_ex) unsol->queue[wp] = res; unsol->queue[wp + 1] = res_ex; - queue_work(bus->workq, &unsol->work); + schedule_work(&unsol->work); return 0; } @@ -437,17 +437,15 @@ static int snd_hda_bus_free(struct hda_bus *bus) if (!bus) return 0; - if (bus->workq) - flush_workqueue(bus->workq); - if (bus->unsol) + if (bus->unsol) { + flush_scheduled_work(); kfree(bus->unsol); + } list_for_each_entry_safe(codec, n, &bus->codec_list, list) { snd_hda_codec_free(codec); } if (bus->ops.private_free) bus->ops.private_free(bus); - if (bus->workq) - destroy_workqueue(bus->workq); kfree(bus); return 0; } @@ -487,7 +485,6 @@ int /*__devinit*/ snd_hda_bus_new(struct snd_card *card, { struct hda_bus *bus; int err; - char qname[8]; static struct snd_device_ops dev_ops = { .dev_register = snd_hda_bus_dev_register, .dev_free = snd_hda_bus_dev_free, @@ -517,14 +514,6 @@ int /*__devinit*/ snd_hda_bus_new(struct snd_card *card, mutex_init(&bus->cmd_mutex); INIT_LIST_HEAD(&bus->codec_list); - snprintf(qname, sizeof(qname), "hda%d", card->number); - bus->workq = create_workqueue(qname); - if (!bus->workq) { - snd_printk(KERN_ERR "cannot create workqueue %s\n", qname); - kfree(bus); - return -ENOMEM; - } - err = snd_device_new(card, SNDRV_DEV_BUS, bus, &dev_ops); if (err < 0) { snd_hda_bus_free(bus); @@ -695,7 +684,7 @@ static void snd_hda_codec_free(struct hda_codec *codec) return; #ifdef CONFIG_SND_HDA_POWER_SAVE cancel_delayed_work(&codec->power_work); - flush_workqueue(codec->bus->workq); + flush_scheduled_work(); #endif list_del(&codec->list); snd_array_free(&codec->mixers); @@ -746,7 +735,6 @@ int /*__devinit*/ snd_hda_codec_new(struct hda_bus *bus, unsigned int codec_addr codec->bus = bus; codec->addr = codec_addr; mutex_init(&codec->spdif_mutex); - mutex_init(&codec->control_mutex); init_hda_cache(&codec->amp_cache, sizeof(struct hda_amp_info)); init_hda_cache(&codec->cmd_cache, sizeof(struct hda_cache_head)); snd_array_init(&codec->mixers, sizeof(struct snd_kcontrol *), 32); @@ -1284,7 +1272,7 @@ void snd_hda_codec_reset(struct hda_codec *codec) #ifdef CONFIG_SND_HDA_POWER_SAVE cancel_delayed_work(&codec->power_work); - flush_workqueue(codec->bus->workq); + flush_scheduled_work(); #endif snd_hda_ctls_clear(codec); /* relase PCMs */ @@ -1430,12 +1418,12 @@ int snd_hda_mixer_bind_switch_get(struct snd_kcontrol *kcontrol, unsigned long pval; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ pval = kcontrol->private_value; kcontrol->private_value = pval & ~AMP_VAL_IDX_MASK; /* index 0 */ err = snd_hda_mixer_amp_switch_get(kcontrol, ucontrol); kcontrol->private_value = pval; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_get); @@ -1447,7 +1435,7 @@ int snd_hda_mixer_bind_switch_put(struct snd_kcontrol *kcontrol, unsigned long pval; int i, indices, err = 0, change = 0; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ pval = kcontrol->private_value; indices = (pval & AMP_VAL_IDX_MASK) >> AMP_VAL_IDX_SHIFT; for (i = 0; i < indices; i++) { @@ -1459,7 +1447,7 @@ int snd_hda_mixer_bind_switch_put(struct snd_kcontrol *kcontrol, change |= err; } kcontrol->private_value = pval; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err < 0 ? err : change; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_switch_put); @@ -1474,12 +1462,12 @@ int snd_hda_mixer_bind_ctls_info(struct snd_kcontrol *kcontrol, struct hda_bind_ctls *c; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ c = (struct hda_bind_ctls *)kcontrol->private_value; kcontrol->private_value = *c->values; err = c->ops->info(kcontrol, uinfo); kcontrol->private_value = (long)c; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_info); @@ -1491,12 +1479,12 @@ int snd_hda_mixer_bind_ctls_get(struct snd_kcontrol *kcontrol, struct hda_bind_ctls *c; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ c = (struct hda_bind_ctls *)kcontrol->private_value; kcontrol->private_value = *c->values; err = c->ops->get(kcontrol, ucontrol); kcontrol->private_value = (long)c; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_get); @@ -1509,7 +1497,7 @@ int snd_hda_mixer_bind_ctls_put(struct snd_kcontrol *kcontrol, unsigned long *vals; int err = 0, change = 0; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ c = (struct hda_bind_ctls *)kcontrol->private_value; for (vals = c->values; *vals; vals++) { kcontrol->private_value = *vals; @@ -1519,7 +1507,7 @@ int snd_hda_mixer_bind_ctls_put(struct snd_kcontrol *kcontrol, change |= err; } kcontrol->private_value = (long)c; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err < 0 ? err : change; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_ctls_put); @@ -1531,12 +1519,12 @@ int snd_hda_mixer_bind_tlv(struct snd_kcontrol *kcontrol, int op_flag, struct hda_bind_ctls *c; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ c = (struct hda_bind_ctls *)kcontrol->private_value; kcontrol->private_value = *c->values; err = c->ops->tlv(kcontrol, op_flag, size, tlv); kcontrol->private_value = (long)c; - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); return err; } EXPORT_SYMBOL_HDA(snd_hda_mixer_bind_tlv); diff --git a/trunk/sound/pci/hda/hda_codec.h b/trunk/sound/pci/hda/hda_codec.h index 5810ef588402..729fc7642d7f 100644 --- a/trunk/sound/pci/hda/hda_codec.h +++ b/trunk/sound/pci/hda/hda_codec.h @@ -614,7 +614,6 @@ struct hda_bus { /* unsolicited event queue */ struct hda_bus_unsolicited *unsol; - struct workqueue_struct *workq; /* common workqueue for codecs */ /* assigned PCMs */ DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES); @@ -772,7 +771,6 @@ struct hda_codec { struct hda_cache_rec cmd_cache; /* cache for other commands */ struct mutex spdif_mutex; - struct mutex control_mutex; unsigned int spdif_status; /* IEC958 status bits */ unsigned short spdif_ctls; /* SPDIF control bits */ unsigned int spdif_in_enable; /* SPDIF input enable? */ diff --git a/trunk/sound/pci/hda/hda_intel.c b/trunk/sound/pci/hda/hda_intel.c index 11e791b965f6..f04de115ee11 100644 --- a/trunk/sound/pci/hda/hda_intel.c +++ b/trunk/sound/pci/hda/hda_intel.c @@ -996,11 +996,10 @@ static irqreturn_t azx_interrupt(int irq, void *dev_id) spin_unlock(&chip->reg_lock); snd_pcm_period_elapsed(azx_dev->substream); spin_lock(&chip->reg_lock); - } else if (chip->bus && chip->bus->workq) { + } else { /* bogus IRQ, process it later */ azx_dev->irq_pending = 1; - queue_work(chip->bus->workq, - &chip->irq_pending_work); + schedule_work(&chip->irq_pending_work); } } } @@ -1742,6 +1741,7 @@ static void azx_clear_irq_pending(struct azx *chip) for (i = 0; i < chip->num_streams; i++) chip->azx_dev[i].irq_pending = 0; spin_unlock_irq(&chip->reg_lock); + flush_scheduled_work(); } static struct snd_pcm_ops azx_pcm_ops = { diff --git a/trunk/sound/pci/hda/patch_analog.c b/trunk/sound/pci/hda/patch_analog.c index 2e7371ec2e23..26247cfe749d 100644 --- a/trunk/sound/pci/hda/patch_analog.c +++ b/trunk/sound/pci/hda/patch_analog.c @@ -3900,7 +3900,6 @@ static const char *ad1884a_models[AD1884A_MODELS] = { static struct snd_pci_quirk ad1884a_cfg_tbl[] = { SND_PCI_QUIRK(0x103c, 0x3030, "HP", AD1884A_MOBILE), - SND_PCI_QUIRK(0x103c, 0x3037, "HP 2230s", AD1884A_LAPTOP), SND_PCI_QUIRK(0x103c, 0x3056, "HP", AD1884A_MOBILE), SND_PCI_QUIRK(0x103c, 0x30e6, "HP 6730b", AD1884A_LAPTOP), SND_PCI_QUIRK(0x103c, 0x30e7, "HP EliteBook 8530p", AD1884A_LAPTOP), @@ -4263,13 +4262,13 @@ static int patch_ad1882(struct hda_codec *codec) spec->num_adc_nids = ARRAY_SIZE(ad1882_adc_nids); spec->adc_nids = ad1882_adc_nids; spec->capsrc_nids = ad1882_capsrc_nids; - if (codec->vendor_id == 0x11d41882) + if (codec->vendor_id == 0x11d1882) spec->input_mux = &ad1882_capture_source; else spec->input_mux = &ad1882a_capture_source; spec->num_mixers = 2; spec->mixers[0] = ad1882_base_mixers; - if (codec->vendor_id == 0x11d41882) + if (codec->vendor_id == 0x11d1882) spec->mixers[1] = ad1882_loopback_mixers; else spec->mixers[1] = ad1882a_loopback_mixers; diff --git a/trunk/sound/pci/hda/patch_nvhdmi.c b/trunk/sound/pci/hda/patch_nvhdmi.c index 96952a37d884..0270fda0bda5 100644 --- a/trunk/sound/pci/hda/patch_nvhdmi.c +++ b/trunk/sound/pci/hda/patch_nvhdmi.c @@ -162,14 +162,12 @@ static struct hda_codec_preset snd_hda_preset_nvhdmi[] = { { .id = 0x10de0002, .name = "MCP78 HDMI", .patch = patch_nvhdmi }, { .id = 0x10de0007, .name = "MCP7A HDMI", .patch = patch_nvhdmi }, { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi }, - { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi }, {} /* terminator */ }; MODULE_ALIAS("snd-hda-codec-id:10de0002"); MODULE_ALIAS("snd-hda-codec-id:10de0007"); MODULE_ALIAS("snd-hda-codec-id:10de0067"); -MODULE_ALIAS("snd-hda-codec-id:10de8001"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Nvidia HDMI HD-audio codec"); diff --git a/trunk/sound/pci/hda/patch_realtek.c b/trunk/sound/pci/hda/patch_realtek.c index ea4c88fe05c4..9065ebf9c065 100644 --- a/trunk/sound/pci/hda/patch_realtek.c +++ b/trunk/sound/pci/hda/patch_realtek.c @@ -1502,11 +1502,11 @@ static int alc_cap_vol_info(struct snd_kcontrol *kcontrol, struct alc_spec *spec = codec->spec; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, HDA_INPUT); err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ return err; } @@ -1517,11 +1517,11 @@ static int alc_cap_vol_tlv(struct snd_kcontrol *kcontrol, int op_flag, struct alc_spec *spec = codec->spec; int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[0], 3, 0, HDA_INPUT); err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ return err; } @@ -1537,11 +1537,11 @@ static int alc_cap_getput_caller(struct snd_kcontrol *kcontrol, unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); int err; - mutex_lock(&codec->control_mutex); + mutex_lock(&codec->spdif_mutex); /* reuse spdif_mutex */ kcontrol->private_value = HDA_COMPOSE_AMP_VAL(spec->adc_nids[adc_idx], 3, 0, HDA_INPUT); err = func(kcontrol, ucontrol); - mutex_unlock(&codec->control_mutex); + mutex_unlock(&codec->spdif_mutex); /* reuse spdif_mutex */ return err; } @@ -8461,10 +8461,6 @@ static struct snd_pci_quirk alc883_cfg_tbl[] = { SND_PCI_QUIRK(0x1025, 0x0121, "Acer Aspire 5920G", ALC883_ACER_ASPIRE), SND_PCI_QUIRK(0x1025, 0x013e, "Acer Aspire 4930G", ALC888_ACER_ASPIRE_4930G), - SND_PCI_QUIRK(0x1025, 0x013f, "Acer Aspire 5930G", - ALC888_ACER_ASPIRE_4930G), - SND_PCI_QUIRK(0x1025, 0x015e, "Acer Aspire 6930G", - ALC888_ACER_ASPIRE_4930G), SND_PCI_QUIRK(0x1025, 0, "Acer laptop", ALC883_ACER), /* default Acer */ SND_PCI_QUIRK(0x1028, 0x020d, "Dell Inspiron 530", ALC888_6ST_DELL), SND_PCI_QUIRK(0x103c, 0x2a3d, "HP Pavillion", ALC883_6ST_DIG), @@ -8526,7 +8522,6 @@ static struct snd_pci_quirk alc883_cfg_tbl[] = { SND_PCI_QUIRK(0x1991, 0x5625, "Haier W66", ALC883_HAIER_W66), SND_PCI_QUIRK(0x8086, 0x0001, "DG33BUC", ALC883_3ST_6ch_INTEL), SND_PCI_QUIRK(0x8086, 0x0002, "DG33FBC", ALC883_3ST_6ch_INTEL), - SND_PCI_QUIRK(0x8086, 0x0022, "DX58SO", ALC883_3ST_6ch_INTEL), SND_PCI_QUIRK(0x8086, 0xd601, "D102GGC", ALC883_3ST_6ch), {} }; @@ -11694,7 +11689,6 @@ static struct snd_pci_quirk alc268_cfg_tbl[] = { SND_PCI_QUIRK(0x1025, 0x015b, "Acer Aspire One", ALC268_ACER_ASPIRE_ONE), SND_PCI_QUIRK(0x1028, 0x0253, "Dell OEM", ALC268_DELL), - SND_PCI_QUIRK(0x1028, 0x02b0, "Dell Inspiron Mini9", ALC268_DELL), SND_PCI_QUIRK(0x103c, 0x30cc, "TOSHIBA", ALC268_TOSHIBA), SND_PCI_QUIRK(0x1043, 0x1205, "ASUS W7J", ALC268_3ST), SND_PCI_QUIRK(0x1179, 0xff10, "TOSHIBA A205", ALC268_TOSHIBA), diff --git a/trunk/sound/soc/codecs/twl4030.c b/trunk/sound/soc/codecs/twl4030.c index ea370a4f86d5..fd0f338374a7 100644 --- a/trunk/sound/soc/codecs/twl4030.c +++ b/trunk/sound/soc/codecs/twl4030.c @@ -197,7 +197,7 @@ static const char *twl4030_earpiece_texts[] = static const unsigned int twl4030_earpiece_values[] = {0x0, 0x1, 0x2, 0x4}; -static const struct soc_enum twl4030_earpiece_enum = +static const struct soc_value_enum twl4030_earpiece_enum = SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7, ARRAY_SIZE(twl4030_earpiece_texts), twl4030_earpiece_texts, @@ -213,7 +213,7 @@ static const char *twl4030_predrivel_texts[] = static const unsigned int twl4030_predrivel_values[] = {0x0, 0x1, 0x2, 0x4}; -static const struct soc_enum twl4030_predrivel_enum = +static const struct soc_value_enum twl4030_predrivel_enum = SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7, ARRAY_SIZE(twl4030_predrivel_texts), twl4030_predrivel_texts, @@ -229,7 +229,7 @@ static const char *twl4030_predriver_texts[] = static const unsigned int twl4030_predriver_values[] = {0x0, 0x1, 0x2, 0x4}; -static const struct soc_enum twl4030_predriver_enum = +static const struct soc_value_enum twl4030_predriver_enum = SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7, ARRAY_SIZE(twl4030_predriver_texts), twl4030_predriver_texts, @@ -317,7 +317,7 @@ static const char *twl4030_analoglmic_texts[] = static const unsigned int twl4030_analoglmic_values[] = {0x0, 0x1, 0x2, 0x4, 0x8}; -static const struct soc_enum twl4030_analoglmic_enum = +static const struct soc_value_enum twl4030_analoglmic_enum = SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, ARRAY_SIZE(twl4030_analoglmic_texts), twl4030_analoglmic_texts, @@ -333,7 +333,7 @@ static const char *twl4030_analogrmic_texts[] = static const unsigned int twl4030_analogrmic_values[] = {0x0, 0x1, 0x4}; -static const struct soc_enum twl4030_analogrmic_enum = +static const struct soc_value_enum twl4030_analogrmic_enum = SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, ARRAY_SIZE(twl4030_analogrmic_texts), twl4030_analogrmic_texts, @@ -1280,8 +1280,6 @@ static int twl4030_remove(struct platform_device *pdev) struct snd_soc_codec *codec = socdev->codec; printk(KERN_INFO "TWL4030 Audio Codec remove\n"); - snd_soc_free_pcms(socdev); - snd_soc_dapm_free(socdev); kfree(codec); return 0; diff --git a/trunk/sound/soc/soc-core.c b/trunk/sound/soc/soc-core.c index 55fdb4abb179..6cbe7e82f238 100644 --- a/trunk/sound/soc/soc-core.c +++ b/trunk/sound/soc/soc-core.c @@ -1584,6 +1584,37 @@ int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, } EXPORT_SYMBOL_GPL(snd_soc_put_enum_double); +/** + * snd_soc_info_value_enum_double - semi enumerated double mixer info callback + * @kcontrol: mixer control + * @uinfo: control element information + * + * Callback to provide information about a double semi enumerated + * mixer control. + * + * Semi enumerated mixer: the enumerated items are referred as values. Can be + * used for handling bitfield coded enumeration for example. + * + * Returns 0 for success. + */ +int snd_soc_info_value_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = e->shift_l == e->shift_r ? 1 : 2; + uinfo->value.enumerated.items = e->max; + + if (uinfo->value.enumerated.item > e->max - 1) + uinfo->value.enumerated.item = e->max - 1; + strcpy(uinfo->value.enumerated.name, + e->texts[uinfo->value.enumerated.item]); + return 0; +} +EXPORT_SYMBOL_GPL(snd_soc_info_value_enum_double); + /** * snd_soc_get_value_enum_double - semi enumerated double mixer get callback * @kcontrol: mixer control @@ -1600,7 +1631,8 @@ int snd_soc_get_value_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; unsigned short reg_val, val, mux; reg_val = snd_soc_read(codec, e->reg); @@ -1639,7 +1671,8 @@ int snd_soc_put_value_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; unsigned short val; unsigned short mask; diff --git a/trunk/sound/soc/soc-dapm.c b/trunk/sound/soc/soc-dapm.c index 493a4e8aa273..ad0d801677c1 100644 --- a/trunk/sound/soc/soc-dapm.c +++ b/trunk/sound/soc/soc-dapm.c @@ -137,7 +137,7 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, } break; case snd_soc_dapm_value_mux: { - struct soc_enum *e = (struct soc_enum *) + struct soc_value_enum *e = (struct soc_value_enum *) w->kcontrols[i].private_value; int val, item; @@ -200,6 +200,30 @@ static int dapm_connect_mux(struct snd_soc_codec *codec, return -ENODEV; } +/* connect value_mux widget to it's interconnecting audio paths */ +static int dapm_connect_value_mux(struct snd_soc_codec *codec, + struct snd_soc_dapm_widget *src, struct snd_soc_dapm_widget *dest, + struct snd_soc_dapm_path *path, const char *control_name, + const struct snd_kcontrol_new *kcontrol) +{ + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; + int i; + + for (i = 0; i < e->max; i++) { + if (!(strcmp(control_name, e->texts[i]))) { + list_add(&path->list, &codec->dapm_paths); + list_add(&path->list_sink, &dest->sources); + list_add(&path->list_source, &src->sinks); + path->name = (char *)e->texts[i]; + dapm_set_path_status(dest, path, 0); + return 0; + } + } + + return -ENODEV; +} + /* connect mixer widget to it's interconnecting audio paths */ static int dapm_connect_mixer(struct snd_soc_codec *codec, struct snd_soc_dapm_widget *src, struct snd_soc_dapm_widget *dest, @@ -750,6 +774,45 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, return 0; } +/* test and update the power status of a value_mux widget */ +static int dapm_value_mux_update_power(struct snd_soc_dapm_widget *widget, + struct snd_kcontrol *kcontrol, int mask, + int mux, int val, struct soc_value_enum *e) +{ + struct snd_soc_dapm_path *path; + int found = 0; + + if (widget->id != snd_soc_dapm_value_mux) + return -ENODEV; + + if (!snd_soc_test_bits(widget->codec, e->reg, mask, val)) + return 0; + + /* find dapm widget path assoc with kcontrol */ + list_for_each_entry(path, &widget->codec->dapm_paths, list) { + if (path->kcontrol != kcontrol) + continue; + + if (!path->name || !e->texts[mux]) + continue; + + found = 1; + /* we now need to match the string in the enum to the path */ + if (!(strcmp(path->name, e->texts[mux]))) + path->connect = 1; /* new connection */ + else + path->connect = 0; /* old connection must be + powered down */ + } + + if (found) { + dapm_power_widgets(widget->codec, SND_SOC_DAPM_STREAM_NOP); + dump_dapm(widget->codec, "mux power update"); + } + + return 0; +} + /* test and update the power status of a mixer or switch widget */ static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, struct snd_kcontrol *kcontrol, int reg, @@ -982,12 +1045,17 @@ static int snd_soc_dapm_add_route(struct snd_soc_codec *codec, path->connect = 1; return 0; case snd_soc_dapm_mux: - case snd_soc_dapm_value_mux: ret = dapm_connect_mux(codec, wsource, wsink, path, control, &wsink->kcontrols[0]); if (ret != 0) goto err; break; + case snd_soc_dapm_value_mux: + ret = dapm_connect_value_mux(codec, wsource, wsink, path, + control, &wsink->kcontrols[0]); + if (ret != 0) + goto err; + break; case snd_soc_dapm_switch: case snd_soc_dapm_mixer: ret = dapm_connect_mixer(codec, wsource, wsink, path, control); @@ -1314,7 +1382,8 @@ int snd_soc_dapm_get_value_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; unsigned short reg_val, val, mux; reg_val = snd_soc_read(widget->codec, e->reg); @@ -1354,7 +1423,8 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct soc_value_enum *e = (struct soc_value_enum *) + kcontrol->private_value; unsigned short val, mux; unsigned short mask; int ret = 0; @@ -1373,7 +1443,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; - dapm_mux_update_power(widget, kcontrol, mask, mux, val, e); + dapm_value_mux_update_power(widget, kcontrol, mask, mux, val, e); if (widget->event) { if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { ret = widget->event(widget, diff --git a/trunk/sound/usb/caiaq/caiaq-device.c b/trunk/sound/usb/caiaq/caiaq-device.c index 41c36b055f6b..a62500e387a6 100644 --- a/trunk/sound/usb/caiaq/caiaq-device.c +++ b/trunk/sound/usb/caiaq/caiaq-device.c @@ -42,7 +42,7 @@ #endif MODULE_AUTHOR("Daniel Mack "); -MODULE_DESCRIPTION("caiaq USB audio, version 1.3.10"); +MODULE_DESCRIPTION("caiaq USB audio, version 1.3.9"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Native Instruments, RigKontrol2}," "{Native Instruments, RigKontrol3}," diff --git a/trunk/sound/usb/caiaq/caiaq-device.h b/trunk/sound/usb/caiaq/caiaq-device.h index ab56e738c5fc..f9fbdbae269d 100644 --- a/trunk/sound/usb/caiaq/caiaq-device.h +++ b/trunk/sound/usb/caiaq/caiaq-device.h @@ -75,7 +75,6 @@ struct snd_usb_caiaqdev { wait_queue_head_t ep1_wait_queue; wait_queue_head_t prepare_wait_queue; int spec_received, audio_parm_answer; - int midi_out_active; char vendor_name[CAIAQ_USB_STR_LEN]; char product_name[CAIAQ_USB_STR_LEN]; diff --git a/trunk/sound/usb/caiaq/caiaq-midi.c b/trunk/sound/usb/caiaq/caiaq-midi.c index f19fd360c936..30b57f97c6e4 100644 --- a/trunk/sound/usb/caiaq/caiaq-midi.c +++ b/trunk/sound/usb/caiaq/caiaq-midi.c @@ -59,11 +59,6 @@ static int snd_usb_caiaq_midi_output_open(struct snd_rawmidi_substream *substrea static int snd_usb_caiaq_midi_output_close(struct snd_rawmidi_substream *substream) { - struct snd_usb_caiaqdev *dev = substream->rmidi->private_data; - if (dev->midi_out_active) { - usb_kill_urb(&dev->midi_out_urb); - dev->midi_out_active = 0; - } return 0; } @@ -74,8 +69,7 @@ static void snd_usb_caiaq_midi_send(struct snd_usb_caiaqdev *dev, dev->midi_out_buf[0] = EP1_CMD_MIDI_WRITE; dev->midi_out_buf[1] = 0; /* port */ - len = snd_rawmidi_transmit(substream, dev->midi_out_buf + 3, - EP1_BUFSIZE - 3); + len = snd_rawmidi_transmit_peek(substream, dev->midi_out_buf+3, EP1_BUFSIZE-3); if (len <= 0) return; @@ -85,24 +79,24 @@ static void snd_usb_caiaq_midi_send(struct snd_usb_caiaqdev *dev, ret = usb_submit_urb(&dev->midi_out_urb, GFP_ATOMIC); if (ret < 0) - log("snd_usb_caiaq_midi_send(%p): usb_submit_urb() failed," - "ret=%d, len=%d\n", - substream, ret, len); - else - dev->midi_out_active = 1; + log("snd_usb_caiaq_midi_send(%p): usb_submit_urb() failed, %d\n", + substream, ret); } static void snd_usb_caiaq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) { struct snd_usb_caiaqdev *dev = substream->rmidi->private_data; - if (up) { - dev->midi_out_substream = substream; - if (!dev->midi_out_active) - snd_usb_caiaq_midi_send(dev, substream); - } else { + if (dev->midi_out_substream != NULL) + return; + + if (!up) { dev->midi_out_substream = NULL; + return; } + + dev->midi_out_substream = substream; + snd_usb_caiaq_midi_send(dev, substream); } @@ -167,14 +161,16 @@ int snd_usb_caiaq_midi_init(struct snd_usb_caiaqdev *device) void snd_usb_caiaq_midi_output_done(struct urb* urb) { struct snd_usb_caiaqdev *dev = urb->context; + char *buf = urb->transfer_buffer; - dev->midi_out_active = 0; if (urb->status != 0) return; if (!dev->midi_out_substream) return; + snd_rawmidi_transmit_ack(dev->midi_out_substream, buf[2]); + dev->midi_out_substream = NULL; snd_usb_caiaq_midi_send(dev, dev->midi_out_substream); }