From af5d5e45502412e4cf1c4db00001be15721fbc71 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 1 Feb 2006 19:26:01 +0000 Subject: [PATCH] --- yaml --- r: 19726 b: refs/heads/master c: 18afea04f1dfc5d52fd2579cd17adc3956acd4ad h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/cache-v6.S | 18 ++++++------------ 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/[refs] b/[refs] index 452aeea274d1..5334b780b56a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8a052e0bc25ff52f17b3dff150846ca9eb969162 +refs/heads/master: 18afea04f1dfc5d52fd2579cd17adc3956acd4ad diff --git a/trunk/arch/arm/mm/cache-v6.S b/trunk/arch/arm/mm/cache-v6.S index 72966d90e956..d921c1024ae0 100644 --- a/trunk/arch/arm/mm/cache-v6.S +++ b/trunk/arch/arm/mm/cache-v6.S @@ -92,22 +92,16 @@ ENTRY(v6_coherent_kern_range) * - the Icache does not read data from the write buffer */ ENTRY(v6_coherent_user_range) - bic r0, r0, #CACHE_LINE_SIZE - 1 -1: + #ifdef HARVARD_CACHE - mcr p15, 0, r0, c7, c10, 1 @ clean D line + bic r0, r0, #CACHE_LINE_SIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D line mcr p15, 0, r0, c7, c5, 1 @ invalidate I line -#endif - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE + add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b +#endif + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #ifdef HARVARD_CACHE mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer