From afd41824c944046aef3503a8bfc23d388b242de8 Mon Sep 17 00:00:00 2001
From: Bruce Allan <bruce.w.allan@intel.com>
Date: Fri, 20 Nov 2009 23:26:24 +0000
Subject: [PATCH] --- yaml --- r: 171790 b: refs/heads/master c:
 84efb7b968ab91d0099620865b3f563eb0ddf5a6 h: refs/heads/master v: v3

---
 [refs]                           | 2 +-
 trunk/drivers/net/e1000e/82571.c | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 5231cd891e97..7bb793d9f8ee 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fe4016746d2c0b3b690f5d1921c826d14008b118
+refs/heads/master: 84efb7b968ab91d0099620865b3f563eb0ddf5a6
diff --git a/trunk/drivers/net/e1000e/82571.c b/trunk/drivers/net/e1000e/82571.c
index 7cdf1768afac..0e8aa3441b97 100644
--- a/trunk/drivers/net/e1000e/82571.c
+++ b/trunk/drivers/net/e1000e/82571.c
@@ -1114,6 +1114,13 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 		reg |= (1 << 22);
 		ew32(GCR, reg);
 
+		/*
+		 * Workaround for hardware errata.
+		 * apply workaround for hardware errata documented in errata
+		 * docs Fixes issue where some error prone or unreliable PCIe
+		 * completions are occurring, particularly with ASPM enabled.
+		 * Without fix, issue can cause tx timeouts.
+		 */
 		reg = er32(GCR2);
 		reg |= 1;
 		ew32(GCR2, reg);