From b09694c393b228802c16c1db290d06013ec8ba5a Mon Sep 17 00:00:00 2001 From: Roy Spliet Date: Tue, 7 Feb 2012 00:29:06 +0100 Subject: [PATCH] --- yaml --- r: 293760 b: refs/heads/master c: e6084257d07fffc394ac6e4cf4496c946fd904ed h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_mem.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 804d4ac483d4..1f8f8f359a90 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1ae73f2f16f1a905ada71e2a190d5760b4f17ed8 +refs/heads/master: e6084257d07fffc394ac6e4cf4496c946fd904ed diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c b/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c index 8ff0027302a6..b08065f981df 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -26,7 +26,8 @@ * DEALINGS IN THE SOFTWARE. * * Authors: - * Keith Whitwell + * Ben Skeggs + * Roy Spliet */ @@ -613,13 +614,13 @@ nvc0_mem_timing_calc(struct drm_device *dev, u32 freq, t->reg[1] = (boot->reg[1] & 0xff000000) | (e->tRCDWR & 0x0f) << 20 | (e->tRCDRD & 0x0f) << 14 | - (e->tCWL << 7) | + (t->tCWL << 7) | (e->tCL & 0x0f); t->reg[2] = (boot->reg[2] & 0xff0000ff) | e->tWR << 16 | e->tWTR << 8; - t->reg[3] = (e->tUNK_20 & 0xf) << 9 | + t->reg[3] = (e->tUNK_20 & 0x1f) << 9 | (e->tUNK_21 & 0xf) << 5 | (e->tUNK_13 & 0x1f); @@ -930,6 +931,8 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t) t->tCWL = 0; if (dev_priv->card_type < NV_C0) { t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1; + } else if (dev_priv->card_type <= NV_D0) { + t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7); } t->mr[0] = nv_rd32(dev, mr_base);