diff --git a/[refs] b/[refs]
index 734fdefd0d48..1f834cddb7b1 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 184cddd1e004d3ebd473f9e1ce20dec1d2576fd1
+refs/heads/master: 857d90f7014f4fe0acc49947ad5309174111a4e8
diff --git a/trunk/drivers/cpufreq/exynos-cpufreq.c b/trunk/drivers/cpufreq/exynos-cpufreq.c
index 0e415e5fb53b..0d40eb7b1dee 100644
--- a/trunk/drivers/cpufreq/exynos-cpufreq.c
+++ b/trunk/drivers/cpufreq/exynos-cpufreq.c
@@ -87,6 +87,9 @@ static int exynos_target(struct cpufreq_policy *policy,
 	freqs.new = freq_table[index].frequency;
 	freqs.cpu = policy->cpu;
 
+	if (freqs.new == freqs.old)
+		goto out;
+
 	/*
 	 * ARM clock source will be changed APLL to MPLL temporary
 	 * To support this level, need to control regulator for
@@ -113,8 +116,8 @@ static int exynos_target(struct cpufreq_policy *policy,
 	if (safe_arm_volt)
 		regulator_set_voltage(arm_regulator, safe_arm_volt,
 				      safe_arm_volt);
-	if (freqs.new != freqs.old)
-		exynos_info->set_freq(old_index, index);
+
+	exynos_info->set_freq(old_index, index);
 
 	for_each_cpu(freqs.cpu, policy->cpus)
 		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);