From b11dfa252d8eca69237dcb11b4bce59190b3f463 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@stericsson.com>
Date: Mon, 13 Sep 2010 13:40:04 +0100
Subject: [PATCH] --- yaml --- r: 211045 b: refs/heads/master c:
 a0719f52d90aed5b82ecf2f3ed14bc4ced3d1a8a h: refs/heads/master i:   211043:
 b58a80e692a6b1ad909c31f99ffb612021309b4e v: v3

---
 [refs]                              |  2 +-
 trunk/arch/arm/plat-nomadik/timer.c | 17 ++++++++++-------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/[refs] b/[refs]
index 86908055cee0..b31843de5d85 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 99f76891a33d130776da3b01935d978b1e75fe68
+refs/heads/master: a0719f52d90aed5b82ecf2f3ed14bc4ced3d1a8a
diff --git a/trunk/arch/arm/plat-nomadik/timer.c b/trunk/arch/arm/plat-nomadik/timer.c
index d673888af18e..aedf9c1d645e 100644
--- a/trunk/arch/arm/plat-nomadik/timer.c
+++ b/trunk/arch/arm/plat-nomadik/timer.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-nomadik/timer.c
+ *  linux/arch/arm/plat-nomadik/timer.c
  *
  * Copyright (C) 2008 STMicroelectronics
  * Copyright (C) 2010 Alessandro Rubini
@@ -75,7 +75,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
 		cr = readl(mtu_base + MTU_CR(1));
 		writel(0, mtu_base + MTU_LR(1));
 		writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
-		writel(0x2, mtu_base + MTU_IMSC);
+		writel(1 << 1, mtu_base + MTU_IMSC);
 		break;
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	case CLOCK_EVT_MODE_UNUSED:
@@ -131,7 +131,7 @@ void __init nmdk_timer_init(void)
 {
 	unsigned long rate;
 	struct clk *clk0;
-	u32 cr;
+	u32 cr = MTU_CRn_32BITS;
 
 	clk0 = clk_get_sys("mtu0", NULL);
 	BUG_ON(IS_ERR(clk0));
@@ -139,12 +139,15 @@ void __init nmdk_timer_init(void)
 	clk_enable(clk0);
 
 	/*
-	 * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
-	 * use a divide-by-16 counter if it's more than 16MHz
+	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
+	 * for ux500.
+	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
+	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
+	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
+	 * with 16 gives too low timer resolution.
 	 */
-	cr = MTU_CRn_32BITS;;
 	rate = clk_get_rate(clk0);
-	if (rate > 16 << 20) {
+	if (rate > 32000000) {
 		rate /= 16;
 		cr |= MTU_CRn_PRESCALE_16;
 	} else {