From b1ea5668f827d28489ef68380b141bd9ef0b49bd Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@opensource.se>
Date: Fri, 14 Dec 2012 14:54:37 +0900
Subject: [PATCH] --- yaml --- r: 372272 b: refs/heads/master c:
 118aee4dd91cf3c0b9546788ef66b65d3e9e31b1 h: refs/heads/master v: v3

---
 [refs]                             |  2 +-
 trunk/drivers/clocksource/sh_cmt.c | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 420a4d3ba7f7..51010df216a8 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: cccd70455c351604d0a9075d35298ed4ff66dab3
+refs/heads/master: 118aee4dd91cf3c0b9546788ef66b65d3e9e31b1
diff --git a/trunk/drivers/clocksource/sh_cmt.c b/trunk/drivers/clocksource/sh_cmt.c
index 7108963a6ab8..b72b7242125e 100644
--- a/trunk/drivers/clocksource/sh_cmt.c
+++ b/trunk/drivers/clocksource/sh_cmt.c
@@ -66,6 +66,21 @@ struct sh_cmt_priv {
 			    unsigned long value);
 };
 
+/* Examples of supported CMT timer register layouts and I/O access widths:
+ *
+ * "16-bit counter and 16-bit control" as found on sh7263:
+ * CMSTR 0xfffec000 16-bit
+ * CMCSR 0xfffec002 16-bit
+ * CMCNT 0xfffec004 16-bit
+ * CMCOR 0xfffec006 16-bit
+ *
+ * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
+ * CMSTR 0xffca0000 16-bit
+ * CMCSR 0xffca0060 16-bit
+ * CMCNT 0xffca0064 32-bit
+ * CMCOR 0xffca0068 32-bit
+ */
+
 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
 {
 	return ioread16(base + (offs << 1));