From b209fb7a8ecf83f66bebb897ff8be80e71d578e2 Mon Sep 17 00:00:00 2001
From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Date: Thu, 27 Sep 2012 19:13:03 +0530
Subject: [PATCH] --- yaml --- r: 345081 b: refs/heads/master c:
 b56747aace48a269fefa7d337963cbae6e95b0a0 h: refs/heads/master i:   345079:
 49e9662bf64b24cce1215663c49aef7bc78d252f v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 3602f68fc896..c6ac26016d5b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ae33cdcfc6aba86505f7a8ec288e3e1f7277de62
+refs/heads/master: b56747aace48a269fefa7d337963cbae6e95b0a0
diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h
index a828e90602b9..3f75ee6b5b21 100644
--- a/trunk/drivers/gpu/drm/i915/i915_reg.h
+++ b/trunk/drivers/gpu/drm/i915/i915_reg.h
@@ -369,6 +369,7 @@
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_PLL_REFCLK_SEL_MASK	3
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
 #define _DPIO_REFSFR_B			0x8034
@@ -384,6 +385,13 @@
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
+#define _DPIO_DATA_LANE0		0x0220
+#define _DPIO_DATA_LANE1		0x0420
+#define _DPIO_DATA_LANE2		0x2620
+#define _DPIO_DATA_LANE3		0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+
 /*
  * Fence registers
  */