From b22ae9aab000d684128cdabb4b925461421e176d Mon Sep 17 00:00:00 2001 From: Barry Song Date: Thu, 23 Aug 2012 13:41:57 +0800 Subject: [PATCH] --- yaml --- r: 326422 b: refs/heads/master c: d0ec63f852f8e5171ad5f6728599560393daced6 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/Documentation/arm/memory.txt | 3 - trunk/arch/arm/Kconfig | 16 +- trunk/arch/arm/include/asm/hardware/iop3xx.h | 12 +- trunk/arch/arm/include/asm/io.h | 8 - trunk/arch/arm/include/asm/mach/map.h | 8 - trunk/arch/arm/include/asm/mach/pci.h | 13 - trunk/arch/arm/kernel/bios32.c | 54 +- trunk/arch/arm/mach-bcmring/arch.c | 2 +- trunk/arch/arm/mach-bcmring/core.c | 3 +- .../arch/arm/mach-bcmring/csp/chipc/chipcHw.c | 137 +- .../arm/mach-bcmring/csp/chipc/chipcHw_init.c | 90 +- .../mach-bcmring/csp/chipc/chipcHw_reset.c | 19 +- trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c | 27 +- .../arm/mach-bcmring/csp/dmac/dmacHw_extra.c | 6 +- trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c | 6 +- .../arm/mach-bcmring/include/cfg_global.h | 13 + .../cfg_global.h => cfg_global_defines.h} | 11 - .../arch/arm/mach-bcmring/include/csp/cache.h | 35 + .../arch/arm/mach-bcmring/include/csp/delay.h | 36 + .../include/{mach => }/csp/dmacHw.h | 4 +- .../arch/arm/mach-bcmring/include/csp/errno.h | 32 + .../arm/mach-bcmring/include/csp/intcHw.h | 40 + .../arm/mach-bcmring/include/csp/module.h | 32 + .../mach-bcmring/include/{mach => }/csp/reg.h | 25 +- .../arch/arm/mach-bcmring/include/csp/secHw.h | 65 + .../arm/mach-bcmring/include/csp/stdint.h | 30 + .../arm/mach-bcmring/include/csp/string.h | 34 + .../include/{mach => }/csp/tmrHw.h | 2 +- .../include/mach/csp/cap_inline.h | 2 +- .../include/mach/csp/chipcHw_def.h | 6 +- .../include/mach/csp/chipcHw_inline.h | 119 +- .../include/mach/csp/chipcHw_reg.h | 6 +- .../mach-bcmring/include/mach/csp/ddrcReg.h | 6 +- .../include/mach/csp/dmacHw_priv.h | 2 +- .../include/mach/csp/dmacHw_reg.h | 106 +- .../mach-bcmring/include/mach/csp/hw_cfg.h | 2 +- .../include/mach/csp/intcHw_reg.h | 18 +- .../mach-bcmring/include/mach/csp/mm_addr.h | 2 +- .../arm/mach-bcmring/include/mach/csp/mm_io.h | 8 +- .../include/mach/csp/secHw_inline.h | 10 +- .../arch/arm/mach-bcmring/include/mach/dma.h | 2 +- .../arm/mach-bcmring/include/mach/hardware.h | 2 +- .../arm/mach-bcmring/include/mach/reg_nand.h | 2 +- .../arm/mach-bcmring/include/mach/reg_umi.h | 4 +- trunk/arch/arm/mach-bcmring/mm.c | 4 +- trunk/arch/arm/mach-bcmring/timer.c | 2 +- trunk/arch/arm/mach-dove/common.c | 10 + trunk/arch/arm/mach-dove/include/mach/dove.h | 8 +- trunk/arch/arm/mach-dove/include/mach/io.h | 19 + trunk/arch/arm/mach-dove/pcie.c | 43 +- trunk/arch/arm/mach-footbridge/common.c | 12 +- trunk/arch/arm/mach-footbridge/dc21285.c | 16 +- .../include/mach/debug-macro.S | 3 +- .../arm/mach-footbridge/include/mach/io.h | 12 +- .../arm/mach-integrator/include/mach/io.h | 33 + .../mach-integrator/include/mach/platform.h | 4 - .../arch/arm/mach-integrator/integrator_ap.c | 9 +- trunk/arch/arm/mach-integrator/pci_v3.c | 50 +- trunk/arch/arm/mach-iop13xx/include/mach/io.h | 28 + .../arm/mach-iop13xx/include/mach/iop13xx.h | 28 +- trunk/arch/arm/mach-iop13xx/io.c | 27 + trunk/arch/arm/mach-iop13xx/pci.c | 37 +- trunk/arch/arm/mach-iop13xx/setup.c | 10 + trunk/arch/arm/mach-iop32x/include/mach/io.h | 19 + trunk/arch/arm/mach-iop33x/include/mach/io.h | 19 + trunk/arch/arm/mach-kirkwood/common.c | 10 + .../arch/arm/mach-kirkwood/include/mach/io.h | 24 + .../arm/mach-kirkwood/include/mach/kirkwood.h | 8 +- trunk/arch/arm/mach-kirkwood/pcie.c | 44 +- trunk/arch/arm/mach-mv78xx0/addr-map.c | 3 +- trunk/arch/arm/mach-mv78xx0/common.c | 5 + trunk/arch/arm/mach-mv78xx0/include/mach/io.h | 24 + .../arm/mach-mv78xx0/include/mach/mv78xx0.h | 21 +- trunk/arch/arm/mach-mv78xx0/pcie.c | 110 +- trunk/arch/arm/mach-orion5x/common.c | 10 + trunk/arch/arm/mach-orion5x/include/mach/io.h | 22 + .../arm/mach-orion5x/include/mach/orion5x.h | 20 +- trunk/arch/arm/mach-orion5x/pci.c | 56 +- trunk/arch/arm/mach-prima2/Makefile | 3 +- trunk/arch/arm/mach-prima2/clock.c | 510 ------- .../arm/mach-prima2/{prima2.c => common.c} | 12 +- trunk/arch/arm/mach-prima2/timer.c | 8 +- trunk/arch/arm/mach-shark/core.c | 18 + .../arm/mach-shark/include/mach/debug-macro.S | 7 +- .../arm/mach-shark/include/mach/entry-macro.S | 3 +- trunk/arch/arm/mach-shark/include/mach/io.h | 18 + trunk/arch/arm/mach-shark/pci.c | 5 - trunk/arch/arm/mach-tegra/include/mach/io.h | 46 + .../arch/arm/mach-tegra/include/mach/iomap.h | 3 - trunk/arch/arm/mach-tegra/pcie.c | 95 +- trunk/arch/arm/mach-u300/Kconfig | 43 +- trunk/arch/arm/mach-u300/Makefile | 1 + trunk/arch/arm/mach-u300/core.c | 100 +- trunk/arch/arm/mach-u300/i2c.c | 6 +- .../arch/arm/mach-u300/include/mach/clkdev.h | 7 + .../{ => include/mach}/dma_channels.h | 11 +- .../arm/mach-u300/include/mach/gpio-u300.h} | 13 +- trunk/arch/arm/mach-u300/include/mach/irqs.h | 36 +- .../arm/mach-u300/include/mach/platform.h | 20 + .../arch/arm/mach-u300/include/mach/syscon.h | 32 +- .../arm/mach-u300/include/mach/u300-regs.h | 19 +- trunk/arch/arm/mach-u300/spi.c | 2 +- trunk/arch/arm/mach-u300/timer.c | 5 +- trunk/arch/arm/mach-u300/timer.h | 1 - trunk/arch/arm/mach-u300/u300-gpio.h | 46 +- trunk/arch/arm/mach-u300/u300.c | 57 + trunk/arch/arm/mach-versatile/core.c | 5 + .../mach-versatile/include/mach/hardware.h | 1 + .../arch/arm/mach-versatile/include/mach/io.h | 27 + trunk/arch/arm/mach-versatile/pci.c | 22 +- trunk/arch/arm/mm/ioremap.c | 14 - trunk/arch/arm/mm/mm.h | 3 - trunk/arch/arm/mm/mmu.c | 56 +- trunk/arch/arm/plat-iop/pci.c | 25 +- trunk/arch/arm/plat-iop/setup.c | 5 + trunk/drivers/clk/Makefile | 1 + trunk/drivers/clk/clk-prima2.c | 1171 +++++++++++++++++ trunk/drivers/i2c/busses/i2c-iop3xx.c | 121 +- trunk/drivers/mtd/nand/bcm_umi_nand.c | 12 +- trunk/drivers/mtd/nand/nand_bcm_umi.h | 73 +- trunk/drivers/pinctrl/pinctrl-coh901.c | 220 +++- 122 files changed, 3303 insertions(+), 1392 deletions(-) create mode 100644 trunk/arch/arm/mach-bcmring/include/cfg_global.h rename trunk/arch/arm/mach-bcmring/include/{mach/cfg_global.h => cfg_global_defines.h} (74%) create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/cache.h create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/delay.h rename trunk/arch/arm/mach-bcmring/include/{mach => }/csp/dmacHw.h (99%) create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/errno.h create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/intcHw.h create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/module.h rename trunk/arch/arm/mach-bcmring/include/{mach => }/csp/reg.h (81%) create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/secHw.h create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/stdint.h create mode 100644 trunk/arch/arm/mach-bcmring/include/csp/string.h rename trunk/arch/arm/mach-bcmring/include/{mach => }/csp/tmrHw.h (99%) create mode 100644 trunk/arch/arm/mach-dove/include/mach/io.h create mode 100644 trunk/arch/arm/mach-integrator/include/mach/io.h create mode 100644 trunk/arch/arm/mach-iop13xx/include/mach/io.h create mode 100644 trunk/arch/arm/mach-iop32x/include/mach/io.h create mode 100644 trunk/arch/arm/mach-iop33x/include/mach/io.h create mode 100644 trunk/arch/arm/mach-kirkwood/include/mach/io.h create mode 100644 trunk/arch/arm/mach-mv78xx0/include/mach/io.h create mode 100644 trunk/arch/arm/mach-orion5x/include/mach/io.h delete mode 100644 trunk/arch/arm/mach-prima2/clock.c rename trunk/arch/arm/mach-prima2/{prima2.c => common.c} (81%) create mode 100644 trunk/arch/arm/mach-shark/include/mach/io.h create mode 100644 trunk/arch/arm/mach-tegra/include/mach/io.h create mode 100644 trunk/arch/arm/mach-u300/include/mach/clkdev.h rename trunk/arch/arm/mach-u300/{ => include/mach}/dma_channels.h (88%) rename trunk/{include/linux/platform_data/pinctrl-coh901.h => arch/arm/mach-u300/include/mach/gpio-u300.h} (72%) create mode 100644 trunk/arch/arm/mach-u300/include/mach/platform.h delete mode 100644 trunk/arch/arm/mach-u300/timer.h create mode 100644 trunk/arch/arm/mach-u300/u300.c create mode 100644 trunk/arch/arm/mach-versatile/include/mach/io.h create mode 100644 trunk/drivers/clk/clk-prima2.c diff --git a/[refs] b/[refs] index b56bdafb6d0e..eab880184cba 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3fbb96d275989c604b343b9e39aeea50386756e9 +refs/heads/master: d0ec63f852f8e5171ad5f6728599560393daced6 diff --git a/trunk/Documentation/arm/memory.txt b/trunk/Documentation/arm/memory.txt index 4bfb9ffbdbc1..208a2d465b92 100644 --- a/trunk/Documentation/arm/memory.txt +++ b/trunk/Documentation/arm/memory.txt @@ -51,9 +51,6 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned ff000000 ffbfffff Reserved for future expansion of DMA mapping region. -fee00000 feffffff Mapping of PCI I/O space. This is a static - mapping within the vmalloc space. - VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 24d955c21d35..fb6014868d33 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -279,6 +279,7 @@ config ARCH_INTEGRATOR select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER @@ -311,6 +312,7 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB + select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD @@ -411,7 +413,7 @@ config ARCH_PRIMA2 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select CLKDEV_LOOKUP + select COMMON_CLK select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL @@ -454,7 +456,7 @@ config ARCH_FOOTBRIDGE select FOOTBRIDGE select GENERIC_CLOCKEVENTS select HAVE_IDE - select NEED_MACH_IO_H if !MMU + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -511,6 +513,7 @@ config ARCH_IOP13XX select PCI select ARCH_SUPPORTS_MSI select VMSPLIT_1G + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NEED_RET_TO_USER help @@ -520,6 +523,7 @@ config ARCH_IOP32X bool "IOP32x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -532,6 +536,7 @@ config ARCH_IOP33X bool "IOP33x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -571,6 +576,7 @@ config ARCH_DOVE select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the Marvell Dove SoC 88AP510 @@ -581,6 +587,7 @@ config ARCH_KIRKWOOD select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: @@ -607,6 +614,7 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: @@ -619,6 +627,7 @@ config ARCH_ORION5X select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: @@ -674,6 +683,7 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ select USE_OF help @@ -902,6 +912,7 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H + select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). @@ -920,7 +931,6 @@ config ARCH_U300 select COMMON_CLK select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. diff --git a/trunk/arch/arm/include/asm/hardware/iop3xx.h b/trunk/arch/arm/include/asm/hardware/iop3xx.h index 02fe2fbe2477..2ff2c75a4639 100644 --- a/trunk/arch/arm/include/asm/hardware/iop3xx.h +++ b/trunk/arch/arm/include/asm/hardware/iop3xx.h @@ -217,8 +217,18 @@ extern int iop3xx_get_init_atu(void); #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 +#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 +#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 +#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 +#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ + IOP3XX_PCI_LOWER_IO_PA) +\ + IOP3XX_PCI_LOWER_IO_VA) + #ifndef __ASSEMBLY__ diff --git a/trunk/arch/arm/include/asm/io.h b/trunk/arch/arm/include/asm/io.h index 8f4db67533e5..815c669fec0a 100644 --- a/trunk/arch/arm/include/asm/io.h +++ b/trunk/arch/arm/include/asm/io.h @@ -113,19 +113,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif -/* PCI fixed i/o mapping */ -#define PCI_IO_VIRT_BASE 0xfee00000 - -extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); - /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include -#elif defined(CONFIG_PCI) -#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) -#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/trunk/arch/arm/include/asm/mach/map.h b/trunk/arch/arm/include/asm/mach/map.h index 195ac2f9d3d3..a6efcdd6fd25 100644 --- a/trunk/arch/arm/include/asm/mach/map.h +++ b/trunk/arch/arm/include/asm/mach/map.h @@ -9,9 +9,6 @@ * * Page table mapping constructs and function prototypes */ -#ifndef __ASM_MACH_MAP_H -#define __ASM_MACH_MAP_H - #include struct map_desc { @@ -37,8 +34,6 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); -extern void vm_reserve_area_early(unsigned long addr, unsigned long size, - void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -49,7 +44,4 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) -#define vm_reserve_area_early(a,s,c) do { } while (0) -#endif - #endif diff --git a/trunk/arch/arm/include/asm/mach/pci.h b/trunk/arch/arm/include/asm/mach/pci.h index db9fedb57f2c..26c511fddf8f 100644 --- a/trunk/arch/arm/include/asm/mach/pci.h +++ b/trunk/arch/arm/include/asm/mach/pci.h @@ -11,8 +11,6 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H -#include - struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -44,8 +42,6 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ - struct resource io_res; - char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ @@ -58,15 +54,6 @@ struct pci_sys_data { */ void pci_common_init(struct hw_pci *); -/* - * Setup early fixed I/O mapping. - */ -#if defined(CONFIG_PCI) -extern void pci_map_io_early(unsigned long pfn); -#else -static inline void pci_map_io_early(unsigned long pfn) {} -#endif - /* * PCI controllers */ diff --git a/trunk/arch/arm/kernel/bios32.c b/trunk/arch/arm/kernel/bios32.c index b244696de1a3..2b2f25e7fef5 100644 --- a/trunk/arch/arm/kernel/bios32.c +++ b/trunk/arch/arm/kernel/bios32.c @@ -13,7 +13,6 @@ #include #include -#include #include static int debug_pci; @@ -424,38 +423,6 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) -{ - int ret; - struct pci_host_bridge_window *window; - - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); - } - - list_for_each_entry(window, &sys->resources, list) { - if (resource_type(window->res) == IORESOURCE_IO) - return 0; - } - - sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; - sys->io_res.end = (busnr + 1) * SZ_64K - 1; - sys->io_res.flags = IORESOURCE_IO; - sys->io_res.name = sys->io_res_name; - sprintf(sys->io_res_name, "PCI%d I/O", busnr); - - ret = request_resource(&ioport_resource, &sys->io_res); - if (ret) { - pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); - return ret; - } - pci_add_resource_offset(&sys->resources, &sys->io_res, - sys->io_offset); - - return 0; -} - static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -478,10 +445,11 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - ret = pcibios_init_resources(nr, sys); - if (ret) { - kfree(sys); - break; + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); } if (hw->scan) @@ -659,15 +627,3 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } - -void __init pci_map_io_early(unsigned long pfn) -{ - struct map_desc pci_io_desc = { - .virtual = PCI_IO_VIRT_BASE, - .type = MT_DEVICE, - .length = SZ_64K, - }; - - pci_io_desc.pfn = pfn; - iotable_init(&pci_io_desc, 1); -} diff --git a/trunk/arch/arm/mach-bcmring/arch.c b/trunk/arch/arm/mach-bcmring/arch.c index 7799e910e271..45c97b1ee9b1 100644 --- a/trunk/arch/arm/mach-bcmring/arch.c +++ b/trunk/arch/arm/mach-bcmring/arch.c @@ -38,7 +38,7 @@ #include #include -#include +#include #include "core.h" diff --git a/trunk/arch/arm/mach-bcmring/core.c b/trunk/arch/arm/mach-bcmring/core.c index 4b50228a6771..adbfb1994582 100644 --- a/trunk/arch/arm/mach-bcmring/core.c +++ b/trunk/arch/arm/mach-bcmring/core.c @@ -43,10 +43,11 @@ #include #include -#include +#include #include "clock.h" +#include #include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 5050833817b7..96273ff34956 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ @@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom) /****************************************************************************/ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ ) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; - uint32_t __iomem *pDependentClock = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + volatile uint32_t *pDependentClock = (uint32_t *) 0x0; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ uint32_t dependentClockType = 0; uint32_t vcoHz = 0; /* Get VCO frequencies */ - if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur } else { vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur if (pPLLReg) { /* Obtain PLL clock frequency */ - if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (clock == chipcHw_CLOCK_DDR) { /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); + return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { vcoHz >>= 1; } /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } } else if (pClockCtrl) { /* Obtain divider clock frequency */ uint32_t div; uint32_t freq = 0; - if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (pDependentClock) { /* Identify the dependent clock frequency */ switch (dependentClockType) { case PLL_CLOCK: - if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent PLL clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain PLL clock frequency using VCO dividers */ - div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK; + div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; freq = div ? chipcHw_divide(vcoHz, div) : 0; } break; case NON_PLL_CLOCK: - if (pDependentClock == &pChipcHw->ACLKClock) { + if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent divider clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain divider clock frequency using XTAL dividers */ - div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); } } @@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur freq = chipcHw_XTAL_FREQ_Hz; } - div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; return chipcHw_divide(freq, (div ? div : 256)); } return 0; @@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ uint32_t freq /* [ IN ] Clock frequency in Hz */ ) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; - uint32_t __iomem *pDependentClock = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + volatile uint32_t *pDependentClock = (uint32_t *) 0x0; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ @@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu uint32_t desVcoHz = 0; /* Get VCO frequencies */ - if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Desired VCO frequency */ desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); } else { vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -307,7 +307,8 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu { REG_LOCAL_IRQ_SAVE; /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock); + pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) + << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->DDRClock; @@ -328,7 +329,8 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Configure the VPM:BUS ratio settings */ { REG_LOCAL_IRQ_SAVE; - writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock); + pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) + << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->VPMClock; @@ -426,9 +428,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* For DDR settings use only the PLL divider clock */ if (pPLLReg == &pChipcHw->DDRClock) { /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); + reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); + freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { @@ -439,7 +441,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } /* Wait for for atleast 200ns as per the protocol to change frequency */ udelay(1); @@ -458,16 +460,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (pDependentClock) { switch (dependentClockType) { case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); + divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); break; case NON_PLL_CLOCK: { uint32_t sourceClock = 0; - if (pDependentClock == &pChipcHw->ACLKClock) { + if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); } divider = chipcHw_divide(sourceClock, freq); @@ -481,7 +483,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (divider) { REG_LOCAL_IRQ_SAVE; /* Set the divider to obtain the required frequency */ - writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl); + *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); REG_LOCAL_IRQ_RESTORE; return freq; } @@ -513,26 +515,25 @@ static int vpmPhaseAlignA0(void) int count = 0; for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; + phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; phaseValue = 0; prevPhaseComp = 0; /* Step 1: Look for falling PH_COMP transition */ /* Read the contents of VPM Clock resgister */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; do { /* Store previous value of phase comparator */ prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Read the contents of VPM Clock resgister. */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -556,13 +557,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -581,13 +581,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -606,13 +605,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -633,14 +631,14 @@ static int vpmPhaseAlignA0(void) /* Store previous value of phase comparator */ prevPhaseComp = phaseValue; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= + chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Read the contents of VPM Clock resgister. */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -663,13 +661,13 @@ static int vpmPhaseAlignA0(void) } /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); + phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); { REG_LOCAL_IRQ_SAVE; - writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock); + pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); /* Load new phase value */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -699,7 +697,7 @@ int chipcHw_vpmPhaseAlign(void) int adjustCount = 0; /* Disable VPM access */ - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; /* Disable HW VPM phase alignment */ chipcHw_vpmHwPhaseAlignDisable(); /* Enable SW VPM phase alignment */ @@ -717,24 +715,23 @@ int chipcHw_vpmPhaseAlign(void) phaseControl--; } else { /* Enable VPM access */ - writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; /* Return adjust count */ return adjustCount; } /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Count adjustment */ adjustCount++; } } /* Disable VPM access */ - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; return -1; } diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index 8377d8054168..367df75d4bb3 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; - writel(chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 = + chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET; pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | @@ -87,30 +87,28 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); /* Enable CHIPC registers to control the PLL */ - writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); + pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; /* Set pre divider to get desired VCO frequency */ - writel(pllPreDivider2, &pChipcHw->PLLPreDivider2); + pChipcHw->PLLPreDivider2 = pllPreDivider2; /* Set NDIV Frac */ - writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2); + pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; /* This has to be removed once the default values are fixed for PLL2. */ - writel(0x38000700, &pChipcHw->PLLControl12); - writel(0x00000015, &pChipcHw->PLLControl22); + pChipcHw->PLLControl12 = 0x38000700; + pChipcHw->PLLControl22 = 0x00000015; /* Reset PLL2 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | + pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } else { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | + pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } REG_LOCAL_IRQ_RESTORE; } @@ -121,25 +119,22 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - writel(readl(&pChipcHw->PLLConfig2) & + pChipcHw->PLLConfig2 &= ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN), - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) ; { REG_LOCAL_IRQ_SAVE; /* Remove digital reset */ - writel(readl(&pChipcHw->PLLConfig2) & - ~chipcHw_REG_PLL_CONFIG_D_RESET, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; REG_LOCAL_IRQ_RESTORE; } @@ -162,9 +157,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; - writel(chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET, - &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = + chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET; /* Setting VCO frequency */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { pllPreDivider = @@ -187,22 +182,30 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) } /* Enable CHIPC registers to control the PLL */ - writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); + pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; /* Set pre divider to get desired VCO frequency */ - writel(pllPreDivider, &pChipcHw->PLLPreDivider); + pChipcHw->PLLPreDivider = pllPreDivider; /* Set NDIV Frac */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider); + pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | + chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; } else { - writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider); + pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | + chipcHw_REG_PLL_DIVIDER_NDIV_f; } /* Reset PLL1 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } else { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_VCO_800_1600 | + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } REG_LOCAL_IRQ_RESTORE; @@ -213,19 +216,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig); + pChipcHw->PLLConfig &= + ~(chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_POWER_DOWN); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED) - || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) + || !(pChipcHw-> + PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) ; /* Remove digital reset */ { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; REG_LOCAL_IRQ_RESTORE; } } @@ -261,7 +267,11 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock); + pChipcHw->ACLKClock = + (pChipcHw-> + ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> + armBusRatio & + chipcHw_REG_ACLKClock_CLK_DIV_MASK); /* Set various core component frequencies. The order in which this is done is important for some. */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index f95ce913fa1e..2671d8896bbb 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -13,11 +13,11 @@ *****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */ @@ -50,18 +50,17 @@ void chipcHw_reset(uint32_t mask) chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); } /* Bypass the PLL clocks before reboot */ - writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, - &pChipcHw->UARTClock); - writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, - &pChipcHw->SPIClock); + pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; + pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ do { - writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i); + ((uint32_t *) MM_IO_BASE_ARAM)[i] = + ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; i++; - } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ + } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - flush_cache_all(); + CSP_CACHE_FLUSH_ALL; /* run the function from ARAM */ runFunc(); diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 547f746c7ff4..6b9be2e98e51 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -25,11 +25,11 @@ /****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include -#include +#include #include #include #include @@ -55,32 +55,33 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ) { uint32_t val = 0; dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module); + dmacHw_MISC_t *pMiscReg = + (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); switch (pCblk->channel) { case 0: - val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; break; case 1: - val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; break; case 2: - val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; break; case 3: - val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; break; case 4: - val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; break; case 5: - val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; break; case 6: - val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; break; case 7: - val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; break; } diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index fe438699d11e..a1f328357aa4 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c index dc4137ff75ca..16225e43f3c3 100644 --- a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 diff --git a/trunk/arch/arm/mach-bcmring/include/cfg_global.h b/trunk/arch/arm/mach-bcmring/include/cfg_global.h new file mode 100644 index 000000000000..f01da877148e --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/cfg_global.h @@ -0,0 +1,13 @@ +#ifndef _CFG_GLOBAL_H_ +#define _CFG_GLOBAL_H_ + +#include + +#define CFG_GLOBAL_CHIP BCM11107 +#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING +#define CFG_GLOBAL_CHIP_REV 0xB0 +#define CFG_GLOBAL_RAM_SIZE 0x10000000 +#define CFG_GLOBAL_RAM_BASE 0x00000000 +#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 + +#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h b/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h similarity index 74% rename from trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h rename to trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h index 449133eacdf5..b5beb0b30734 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h +++ b/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h @@ -38,14 +38,3 @@ #define IMAGE_HEADER_SIZE_CHECKSUM 4 #endif -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/cache.h b/trunk/arch/arm/mach-bcmring/include/csp/cache.h new file mode 100644 index 000000000000..caa20e59db99 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/cache.h @@ -0,0 +1,35 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_CACHE_H +#define CSP_CACHE_H + +/* ---- Include Files ---------------------------------------------------- */ + +#include + +/* ---- Public Constants and Types --------------------------------------- */ + +#if defined(__KERNEL__) && !defined(STANDALONE) +#include + +#define CSP_CACHE_FLUSH_ALL flush_cache_all() + +#else + +#define CSP_CACHE_FLUSH_ALL + +#endif + +#endif /* CSP_CACHE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/delay.h b/trunk/arch/arm/mach-bcmring/include/csp/delay.h new file mode 100644 index 000000000000..8b3d80367293 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/delay.h @@ -0,0 +1,36 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +#ifndef CSP_DELAY_H +#define CSP_DELAY_H + +/* ---- Include Files ---------------------------------------------------- */ + +/* Some CSP routines require use of the following delay routines. Use the OS */ +/* version if available, otherwise use a CSP specific definition. */ +/* void udelay(unsigned long usecs); */ +/* void mdelay(unsigned long msecs); */ + +#if defined(__KERNEL__) && !defined(STANDALONE) + #include +#else + #include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_DELAY_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h rename to trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h index 9dc90f46a84d..e6a1dc484ca7 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h @@ -23,9 +23,9 @@ #ifndef _DMACHW_H #define _DMACHW_H -#include +#include -#include +#include #include /* Define DMA Channel ID using DMA controller number (m) and channel number (c). diff --git a/trunk/arch/arm/mach-bcmring/include/csp/errno.h b/trunk/arch/arm/mach-bcmring/include/csp/errno.h new file mode 100644 index 000000000000..51357dd5b666 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/errno.h @@ -0,0 +1,32 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_ERRNO_H +#define CSP_ERRNO_H + +/* ---- Include Files ---------------------------------------------------- */ + +#if defined(__KERNEL__) +#include +#elif defined(CSP_SIMULATION) +#include +#else +#include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_ERRNO_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h b/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h new file mode 100644 index 000000000000..1c639c8ee08f --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h @@ -0,0 +1,40 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +/****************************************************************************/ +/** +* @file intcHw.h +* +* @brief generic interrupt controller API +* +* @note +* None +*/ +/****************************************************************************/ + +#ifndef _INTCHW_H +#define _INTCHW_H + +/* ---- Include Files ---------------------------------------------------- */ +#include + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ +static inline void intcHw_irq_disable(void *basep, uint32_t mask); +static inline void intcHw_irq_enable(void *basep, uint32_t mask); + +#endif /* _INTCHW_H */ + diff --git a/trunk/arch/arm/mach-bcmring/include/csp/module.h b/trunk/arch/arm/mach-bcmring/include/csp/module.h new file mode 100644 index 000000000000..c30d2a5975a6 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/module.h @@ -0,0 +1,32 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +#ifndef CSP_MODULE_H +#define CSP_MODULE_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ + #include +#else + #define EXPORT_SYMBOL(symbol) +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + + +#endif /* CSP_MODULE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h b/trunk/arch/arm/mach-bcmring/include/csp/reg.h similarity index 81% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h rename to trunk/arch/arm/mach-bcmring/include/csp/reg.h index d9cbdca8cd25..56654d23c3d7 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/reg.h @@ -25,14 +25,13 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ -#define __REG32(x) (*((volatile uint32_t __iomem *)(x))) -#define __REG16(x) (*((volatile uint16_t __iomem *)(x))) -#define __REG8(x) (*((volatile uint8_t __iomem *) (x))) +#define __REG32(x) (*((volatile uint32_t *)(x))) +#define __REG16(x) (*((volatile uint16_t *)(x))) +#define __REG8(x) (*((volatile uint8_t *) (x))) /* Macros used to define a sequence of reserved registers. The start / end */ /* are byte offsets in the particular register definition, with the "end" */ @@ -85,31 +84,31 @@ #endif -static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel(__raw_readl(reg) & value, reg); + *reg &= value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel(__raw_readl(reg) | value, reg); + *reg |= value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask, +static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel((__raw_readl(reg) & mask) | value, reg); + *reg = (*reg & mask) | value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_write(volatile uint32_t *reg, uint32_t value) { - __raw_writel(value, reg); + *reg = value; } #endif /* CSP_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/secHw.h b/trunk/arch/arm/mach-bcmring/include/csp/secHw.h new file mode 100644 index 000000000000..b9d7e0732dfc --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/secHw.h @@ -0,0 +1,65 @@ +/***************************************************************************** +* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +/****************************************************************************/ +/** +* @file secHw.h +* +* @brief Definitions for accessing low level security features +* +*/ +/****************************************************************************/ +#ifndef SECHW_H +#define SECHW_H + +typedef void (*secHw_FUNC_t) (void); + +typedef enum { + secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ + secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ +} secHw_MODE; + +/****************************************************************************/ +/** +* @brief Requesting to execute the function in secure mode +* +* This function requests the given function to run in secure mode +* +*/ +/****************************************************************************/ +void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ + ); + +/****************************************************************************/ +/** +* @brief Sets the mode +* +* his function sets the processor mode (secure/non-secure) +* +*/ +/****************************************************************************/ +void secHw_SetMode(secHw_MODE /* Processor mode */ + ); + +/****************************************************************************/ +/** +* @brief Get the current mode +* +* This function retieves the processor mode (secure/non-secure) +* +*/ +/****************************************************************************/ +void secHw_GetMode(secHw_MODE *); + +#endif /* SECHW_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/stdint.h b/trunk/arch/arm/mach-bcmring/include/csp/stdint.h new file mode 100644 index 000000000000..3a8718bbf700 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/stdint.h @@ -0,0 +1,30 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_STDINT_H +#define CSP_STDINT_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_STDINT_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/string.h b/trunk/arch/arm/mach-bcmring/include/csp/string.h new file mode 100644 index 000000000000..ad9e4005f141 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/string.h @@ -0,0 +1,34 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + + +#ifndef CSP_STRING_H +#define CSP_STRING_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ + #include +#else + #include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + + +#endif /* CSP_STRING_H */ + diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h b/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h rename to trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h index 1cc882ae60f5..2cbb530db8ea 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h @@ -23,7 +23,7 @@ #ifndef _TMRHW_H #define _TMRHW_H -#include +#include typedef uint32_t tmrHw_ID_t; /* Timer ID */ typedef uint32_t tmrHw_COUNT_t; /* Timer count */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h index 0a89e0c63419..933ce68ed90b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ #define CAP_CONFIG0_VPM_DIS 0x00000001 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 39f09cb89208..161973385faf 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -17,9 +17,9 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include /* ---- Public Constants and Types ---------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index a66f3f7abb86..03238c299001 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -17,8 +17,8 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include +#include +#include #include #include @@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, /****************************************************************************/ static inline uint32_t chipcHw_getChipId(void) { - return readl(&pChipcHw->ChipId); + return pChipcHw->ChipId; } /****************************************************************************/ @@ -59,16 +59,15 @@ static inline uint32_t chipcHw_getChipId(void) /****************************************************************************/ static inline void chipcHw_enableSpreadSpectrum(void) { - if ((readl(&pChipcHw-> - PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != + if ((pChipcHw-> + PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | + ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = + (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT), - &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg); - writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) | - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE, - &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl); + ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); + ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= + ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; } } @@ -94,8 +93,8 @@ static inline void chipcHw_disableSpreadSpectrum(void) /****************************************************************************/ static inline uint32_t chipcHw_getChipProductId(void) { - return (readl(&pChipcHw-> - ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >> + return (pChipcHw-> + ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> chipcHw_REG_CHIPID_BASE_SHIFT; } @@ -110,7 +109,7 @@ static inline uint32_t chipcHw_getChipProductId(void) /****************************************************************************/ static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) { - return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK; + return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; } /****************************************************************************/ @@ -157,7 +156,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) { - return readl(&pChipcHw->BusIntfClock); + return pChipcHw->BusIntfClock; } /****************************************************************************/ @@ -216,9 +215,8 @@ static inline void chipcHw_softResetDisable(uint64_t mask) /* Deassert module soft reset */ REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1); - writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 & - (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); + pChipcHw->SoftReset1 ^= ctrl1; + pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); REG_LOCAL_IRQ_RESTORE; } @@ -229,10 +227,9 @@ static inline void chipcHw_softResetEnable(uint64_t mask) uint32_t unhold = 0; REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1); + pChipcHw->SoftReset1 |= ctrl1; /* Mask out unhold request bits */ - writel(readl(&pChipcHw->SoftReset2) | (ctrl2 & - (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); + pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); /* Process unhold requests */ if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { @@ -249,7 +246,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask) if (unhold) { /* Make sure unhold request is effective */ - writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1); + pChipcHw->SoftReset1 &= ~unhold; } REG_LOCAL_IRQ_RESTORE; } @@ -310,7 +307,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getStickyBits(void) { - return readl(&pChipcHw->Sticky); + return pChipcHw->Sticky; } /****************************************************************************/ @@ -331,7 +328,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_POR_BROM; } else { uint32_t sticky; - sticky = readl(pChipcHw->Sticky); + sticky = pChipcHw->Sticky; if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { @@ -358,7 +355,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_GENERAL_5; } } - writel(bits, pChipcHw->Sticky); + pChipcHw->Sticky = bits; REG_LOCAL_IRQ_RESTORE; } @@ -380,7 +377,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = readl(&pChipcHw->Sticky); + uint32_t sticky = pChipcHw->Sticky; if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { @@ -413,7 +410,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) mask &= ~chipcHw_REG_STICKY_GENERAL_5; } } - writel(bits | mask, &pChipcHw->Sticky); + pChipcHw->Sticky = bits | mask; REG_LOCAL_IRQ_RESTORE; } @@ -429,7 +426,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getSoftStraps(void) { - return readl(&pChipcHw->SoftStraps); + return pChipcHw->SoftStraps; } /****************************************************************************/ @@ -459,7 +456,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions) /****************************************************************************/ static inline uint32_t chipcHw_getPinStraps(void) { - return readl(&pChipcHw->PinStraps); + return pChipcHw->PinStraps; } /****************************************************************************/ @@ -674,9 +671,9 @@ static inline void chipcHw_selectGE3(void) /****************************************************************************/ static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) { - return (readl(chipcHw_REG_GPIO_MUX(pin))) & + return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin)) >> + chipcHw_REG_GPIO_MUX_POSITION(pin))) >> chipcHw_REG_GPIO_MUX_POSITION(pin); } @@ -844,8 +841,8 @@ static inline void chipcHw_setUsbDevice(void) static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, chipcHw_OPTYPE_e type, int mode) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; switch (clock) { case chipcHw_CLOCK_DDR: @@ -1074,7 +1071,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) /****************************************************************************/ static inline int chipcHw_isSoftwareStrapsEnable(void) { - return readl(&pChipcHw->SoftStraps) & 0x00000001; + return pChipcHw->SoftStraps & 0x00000001; } /****************************************************************************/ @@ -1141,7 +1138,7 @@ static inline void chipcHw_pll2TestDisable(void) /****************************************************************************/ static inline int chipcHw_isPllTestEnable(void) { - return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1150,7 +1147,7 @@ static inline int chipcHw_isPllTestEnable(void) /****************************************************************************/ static inline int chipcHw_isPll2TestEnable(void) { - return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1186,8 +1183,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val) /****************************************************************************/ static inline uint8_t chipcHw_getPllTestSelected(void) { - return (uint8_t) ((readl(&pChipcHw-> - PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((pChipcHw-> + PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1197,8 +1194,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void) /****************************************************************************/ static inline uint8_t chipcHw_getPll2TestSelected(void) { - return (uint8_t) ((readl(&pChipcHw-> - PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((pChipcHw-> + PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1211,8 +1208,7 @@ static inline uint8_t chipcHw_getPll2TestSelected(void) static inline void chipcHw_pll1Disable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig); + pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; REG_LOCAL_IRQ_RESTORE; } @@ -1225,8 +1221,7 @@ static inline void chipcHw_pll1Disable(void) static inline void chipcHw_pll2Disable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; REG_LOCAL_IRQ_RESTORE; } @@ -1238,8 +1233,7 @@ static inline void chipcHw_pll2Disable(void) static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, - &pChipcHw->Spare1); + pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1251,8 +1245,7 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, - &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1340,8 +1333,7 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void) static inline void chipcHw_vpmSwPhaseAlignEnable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE, - &pChipcHw->VPMPhaseCtrl1); + pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1380,8 +1372,7 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void) static inline void chipcHw_vpmHwPhaseAlignDisable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE, - &pChipcHw->VPMPhaseCtrl1); + pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1483,8 +1474,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) /****************************************************************************/ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1497,8 +1488,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1509,8 +1500,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> chipcHw_REG_DDR_PHASE_STATUS_SHIFT; } @@ -1522,8 +1513,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> chipcHw_REG_VPM_PHASE_STATUS_SHIFT; } @@ -1535,8 +1526,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrPhaseControl(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> chipcHw_REG_DDR_PHASE_CTRL_SHIFT; } @@ -1548,8 +1539,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmPhaseControl(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> chipcHw_REG_VPM_PHASE_CTRL_SHIFT; } diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index 26f5d0e4e1dd..b162448f613c 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -24,7 +24,7 @@ #define CHIPCHW_REG_H #include -#include +#include #include #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC @@ -131,8 +131,8 @@ typedef struct { uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ } chipcHw_REG_t; -#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical (MM_ADDR_IO_CHIPC) +#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) +#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_SHIFT 12 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index 39da2c1fdafb..f1b68e26fa6d 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -30,8 +30,8 @@ extern "C" { /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include @@ -416,7 +416,7 @@ extern "C" { } ddrcReg_PHY_ADDR_CTL_REG_t; #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) +#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) /* @todo These SS definitions are duplicates of ones below */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h index 9d9455e0c391..d67e2f8c22de 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_PRIV_H #define _DMACHW_PRIV_H -#include +#include /* Data type for DMA Link List Item */ typedef struct { diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index 7cd0aafa6f6e..f1ecf96f2da5 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_REG_H #define _DMACHW_REG_H -#include +#include #include /* Data type for 64 bit little endian register */ @@ -121,75 +121,75 @@ typedef struct { } dmacHw_MISC_t; /* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ +#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ +#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ extern uint32_t dmaChannelCount_0; extern uint32_t dmaChannelCount_1; /* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) +#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) /* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) +#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) +#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) +#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) +#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) +#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) +#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) +#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) +#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) +#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) +#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) +#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) +#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) +#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) +#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) +#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) +#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) +#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) +#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) /* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) +#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) +#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) +#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) +#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) +#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) +#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) +#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) /* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) +#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) +#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) /* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) +#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) +#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) +#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) +#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) +#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) +#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) +#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) +#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) +#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) +#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) +#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) +#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) +#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) +#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) +#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) /* Channel control registers */ #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h index 27f59dd27792..cfa91bed9d34 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h @@ -18,7 +18,7 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #if defined(__KERNEL__) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index f59db25b5632..0aeb6a6fe7f8 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -27,8 +27,8 @@ #define _INTCHW_REG_H /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include /* ---- Public Constants and Types --------------------------------------- */ @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 (MM_IO_BASE_INTC0) -#define INTCHW_INTC1 (MM_IO_BASE_INTC1) -#define INTCHW_SINTC (MM_IO_BASE_SINTC) +#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) +#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) +#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) +static inline void intcHw_irq_disable(void *basep, uint32_t mask) { - writel(mask, basep + INTCHW_INTENCLEAR); + __REG32(basep + INTCHW_INTENCLEAR) = mask; } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) +static inline void intcHw_irq_enable(void *basep, uint32_t mask) { - writel(mask, basep + INTCHW_INTENABLE); + __REG32(basep + INTCHW_INTENABLE) = mask; } #endif /* _INTCHW_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h index d571962f2904..ad58cf873377 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h @@ -29,7 +29,7 @@ /* ---- Include Files ---------------------------------------------------- */ #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index 47450c23685a..de92ec6a01aa 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -30,7 +30,7 @@ #include #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ @@ -49,7 +49,7 @@ #ifdef __ASSEMBLY__ #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #else -#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ +#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) #endif #endif @@ -60,8 +60,8 @@ #ifdef __ASSEMBLY__ #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #else -#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF))) +#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ + ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) #endif #endif diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h index 55d3cd4fd1e7..9cd6a032ab71 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h @@ -34,7 +34,7 @@ /****************************************************************************/ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; @@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK /****************************************************************************/ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { - writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure); + regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; } if (mask & 0xFFFF0000) { - writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure); + regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; } } @@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA /****************************************************************************/ static inline uint32_t secHw_getStatus(void) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; return (regp->reg[1].status << 16) + regp->reg[0].status; } diff --git a/trunk/arch/arm/mach-bcmring/include/mach/dma.h b/trunk/arch/arm/mach-bcmring/include/mach/dma.h index 13e01384d6fc..72543781207b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/dma.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/dma.h @@ -27,7 +27,7 @@ #include #include -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h index a0c92b4b8c60..6ae20a649a97 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #include /* Hardware addresses of major areas. diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h index f8d51a8b0b15..387376ffb56b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_NAND_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h index 56dd9de7d83f..0992842caa77 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_UMI_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ @@ -233,5 +233,5 @@ #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 /* location within a page (512 byte) */ #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) +#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #endif diff --git a/trunk/arch/arm/mach-bcmring/mm.c b/trunk/arch/arm/mach-bcmring/mm.c index 33824a81cac4..1adec78ec940 100644 --- a/trunk/arch/arm/mach-bcmring/mm.c +++ b/trunk/arch/arm/mach-bcmring/mm.c @@ -20,12 +20,12 @@ #include #include -#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \ +#define IO_DESC(va, sz) { .virtual = va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_DEVICE } -#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \ +#define MEM_DESC(va, sz) { .virtual = va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_MEMORY } diff --git a/trunk/arch/arm/mach-bcmring/timer.c b/trunk/arch/arm/mach-bcmring/timer.c index 59412903466e..af9c3d7e2a0c 100644 --- a/trunk/arch/arm/mach-bcmring/timer.c +++ b/trunk/arch/arm/mach-bcmring/timer.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index ed4fa5f316ea..4db5de54b6a7 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -49,6 +49,16 @@ static struct map_desc dove_io_desc[] __initdata = { .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE0_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), + .length = DOVE_PCIE0_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), + .length = DOVE_PCIE1_IO_SIZE, + .type = MT_DEVICE, }, }; diff --git a/trunk/arch/arm/mach-dove/include/mach/dove.h b/trunk/arch/arm/mach-dove/include/mach/dove.h index c91e3004a47b..d52b0ef313b7 100644 --- a/trunk/arch/arm/mach-dove/include/mach/dove.h +++ b/trunk/arch/arm/mach-dove/include/mach/dove.h @@ -50,12 +50,14 @@ #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 +#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_64K +#define DOVE_PCIE0_IO_SIZE SZ_1M #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 -#define DOVE_PCIE1_IO_SIZE SZ_64K +#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 +#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 +#define DOVE_PCIE1_IO_SIZE SZ_1M /* * Dove Core Registers Map diff --git a/trunk/arch/arm/mach-dove/include/mach/io.h b/trunk/arch/arm/mach-dove/include/mach/io.h new file mode 100644 index 000000000000..29c8b85355a5 --- /dev/null +++ b/trunk/arch/arm/mach-dove/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-dove/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "dove.h" + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \ + DOVE_PCIE0_IO_VIRT_BASE)) + +#endif diff --git a/trunk/arch/arm/mach-dove/pcie.c b/trunk/arch/arm/mach-dove/pcie.c index 355332d502cb..47921b0cdc65 100644 --- a/trunk/arch/arm/mach-dove/pcie.c +++ b/trunk/arch/arm/mach-dove/pcie.c @@ -26,8 +26,9 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; + char io_space_name[16]; char mem_space_name[16]; - struct resource res; + struct resource res[2]; }; static struct pcie_port pcie_port[2]; @@ -52,10 +53,24 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - if (pp->index == 0) - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); - else - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); + /* + * IORESOURCE_IO + */ + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d I/O", pp->index); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + if (pp->index == 0) { + pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; + } else { + pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; + } + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); /* * IORESOURCE_MEM @@ -63,18 +78,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res.name = pp->mem_space_name; + pp->res[1].name = pp->mem_space_name; if (pp->index == 0) { - pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; - pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; + pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; } else { - pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; - pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; + pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; } - pp->res.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res)) + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -195,7 +210,7 @@ static void __init add_pcie_port(int index, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(&pp->res, 0, sizeof(pp->res)); + memset(pp->res, 0, sizeof(pp->res)); } else { printk(KERN_INFO "link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-footbridge/common.c b/trunk/arch/arm/mach-footbridge/common.c index a42b369bc439..3e6aaa6361da 100644 --- a/trunk/arch/arm/mach-footbridge/common.c +++ b/trunk/arch/arm/mach-footbridge/common.c @@ -15,7 +15,7 @@ #include #include #include - + #include #include #include @@ -26,7 +26,6 @@ #include #include -#include #include "common.h" @@ -176,6 +175,11 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_PCI_IACK), .length = PCIIACK_SIZE, .type = MT_DEVICE, + }, { + .virtual = PCIO_BASE, + .pfn = __phys_to_pfn(DC21285_PCI_IO), + .length = PCIO_SIZE, + .type = MT_DEVICE, }, #endif }; @@ -192,10 +196,8 @@ void __init footbridge_map_io(void) * Now, work out what we've got to map in addition on this * platform. */ - if (footbridge_cfn_mode()) { + if (footbridge_cfn_mode()) iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); - pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); - } } void footbridge_restart(char mode, const char *cmd) diff --git a/trunk/arch/arm/mach-footbridge/dc21285.c b/trunk/arch/arm/mach-footbridge/dc21285.c index a7cd2cf5e08d..9d62e3381024 100644 --- a/trunk/arch/arm/mach-footbridge/dc21285.c +++ b/trunk/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_ioremap_io(0, DC21285_PCI_IO); - + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,6 +350,14 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { + static struct resource csrio; + + csrio.flags = IORESOURCE_IO; + csrio.name = "Footbridge"; + + allocate_resource(&ioport_resource, &csrio, 128, + 0xff00, 0xffff, 128, NULL, NULL); + /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -357,7 +365,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = 0; + *CSR_PCICSRIOBASE = csrio.start; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | diff --git a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S index c169f0c99b2a..e5acde25ffc5 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -17,8 +17,7 @@ /* For NetWinder debugging */ .macro addruart, rp, rv, tmp mov \rp, #0x000003f8 - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00e00000 @ virtual + orr \rv, \rp, #0xff000000 @ virtual orr \rp, \rp, #0x7c000000 @ physical .endm diff --git a/trunk/arch/arm/mach-footbridge/include/mach/io.h b/trunk/arch/arm/mach-footbridge/include/mach/io.h index aba46388cc0c..aba531eebbc6 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/io.h +++ b/trunk/arch/arm/mach-footbridge/include/mach/io.h @@ -14,10 +14,18 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + +#define PCIO_SIZE 0x00100000 +#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) + /* - * Translation of various i/o addresses to host addresses for !CONFIG_MMU + * Translation of various region addresses to virtual addresses */ -#define PCIO_BASE 0x7c000000 #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) #endif diff --git a/trunk/arch/arm/mach-integrator/include/mach/io.h b/trunk/arch/arm/mach-integrator/include/mach/io.h new file mode 100644 index 000000000000..8de70de3dd0a --- /dev/null +++ b/trunk/arch/arm/mach-integrator/include/mach/io.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-integrator/include/mach/io.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* + * WARNING: this has to mirror definitions in platform.h + */ +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 +#define PCI_IO_VADDR 0xee000000 + +#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) + +#endif diff --git a/trunk/arch/arm/mach-integrator/include/mach/platform.h b/trunk/arch/arm/mach-integrator/include/mach/platform.h index 4c0347526851..ec467baade09 100644 --- a/trunk/arch/arm/mach-integrator/include/mach/platform.h +++ b/trunk/arch/arm/mach-integrator/include/mach/platform.h @@ -324,10 +324,6 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 - /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c index fd3ef28d2c1a..3b2267529f5e 100644 --- a/trunk/arch/arm/mach-integrator/integrator_ap.c +++ b/trunk/arch/arm/mach-integrator/integrator_ap.c @@ -50,7 +50,6 @@ #include #include #include -#include #include #include @@ -74,7 +73,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -148,6 +147,11 @@ static struct map_desc ap_io_desc[] __initdata = { .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE + }, { + .virtual = PCI_IO_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), + .length = SZ_64K, + .type = MT_DEVICE } }; @@ -155,7 +159,6 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; - pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff diff --git a/trunk/arch/arm/mach-integrator/pci_v3.c b/trunk/arch/arm/mach-integrator/pci_v3.c index 495f181fc937..b866880e82ac 100644 --- a/trunk/arch/arm/mach-integrator/pci_v3.c +++ b/trunk/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); @@ -374,9 +374,12 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* + * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -495,6 +498,7 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; + pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/io.h b/trunk/arch/arm/mach-iop13xx/include/mach/io.h new file mode 100644 index 000000000000..f13188518025 --- /dev/null +++ b/trunk/arch/arm/mach-iop13xx/include/mach/io.h @@ -0,0 +1,28 @@ +/* + * iop13xx custom ioremap implementation + * Copyright (c) 2005-2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. + * + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __iop13xx_io(a) + +extern void __iomem * __iop13xx_io(unsigned long io_addr); + +#endif diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h index e10e101645dd..e190dcd7d72d 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -69,11 +69,21 @@ extern unsigned long get_iop_tick_rate(void); * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP - * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window - * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window + * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window + * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window */ +#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL +#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ +#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIX_LOWER_IO_PA\ + - IOP13XX_PCIX_LOWER_IO_VA)) #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL @@ -93,8 +103,20 @@ extern unsigned long get_iop_tick_rate(void); IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ +#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ +#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL +#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ +#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIE_LOWER_IO_PA\ + - IOP13XX_PCIE_LOWER_IO_VA)) #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL diff --git a/trunk/arch/arm/mach-iop13xx/io.c b/trunk/arch/arm/mach-iop13xx/io.c index 851dc8f2b6b5..3c364198db9c 100644 --- a/trunk/arch/arm/mach-iop13xx/io.c +++ b/trunk/arch/arm/mach-iop13xx/io.c @@ -23,6 +23,25 @@ #include "pci.h" +void * __iomem __iop13xx_io(unsigned long io_addr) +{ + void __iomem * io_virt; + + switch (io_addr) { + case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: + io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); + break; + case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: + io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); + break; + default: + BUG(); + } + + return io_virt; +} +EXPORT_SYMBOL(__iop13xx_io); + static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, size_t size, unsigned int mtype, void *caller) { @@ -48,6 +67,12 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, (cookie - IOP13XX_PBI_LOWER_MEM_RA), size, mtype, __builtin_return_address(0)); break; + case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: + retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); + break; + case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: + retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); + break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; @@ -74,6 +99,8 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) goto skip; switch ((u32) addr) { + case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: + case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } diff --git a/trunk/arch/arm/mach-iop13xx/pci.c b/trunk/arch/arm/mach-iop13xx/pci.c index 91f731a2957b..861cb12ef436 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.c +++ b/trunk/arch/arm/mach-iop13xx/pci.c @@ -970,6 +970,7 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ + pcibios_min_io = 0; pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU @@ -1002,7 +1003,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kzalloc(sizeof(struct resource), GFP_KERNEL); + res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1041,13 +1042,17 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); + res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; + res[0].end = IOP13XX_PCIX_UPPER_IO_PA; + res[0].name = "IQ81340 ATUX PCI I/O Space"; + res[0].flags = IORESOURCE_IO; - res->start = IOP13XX_PCIX_LOWER_MEM_RA; - res->end = IOP13XX_PCIX_UPPER_MEM_RA; - res->name = "IQ81340 ATUX PCI Memory Space"; - res->flags = IORESOURCE_MEM; + res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; + res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; + res[1].name = "IQ81340 ATUX PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; + sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1058,13 +1063,17 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); + res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; + res[0].end = IOP13XX_PCIE_UPPER_IO_PA; + res[0].name = "IQ81340 ATUE PCI I/O Space"; + res[0].flags = IORESOURCE_IO; - res->start = IOP13XX_PCIE_LOWER_MEM_RA; - res->end = IOP13XX_PCIE_UPPER_MEM_RA; - res->name = "IQ81340 ATUE PCI Memory Space"; - res->flags = IORESOURCE_MEM; + res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; + res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; + res[1].name = "IQ81340 ATUE PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; + sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: @@ -1072,9 +1081,11 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) return 0; } - request_resource(&iomem_resource, res); + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); return 1; } diff --git a/trunk/arch/arm/mach-iop13xx/setup.c b/trunk/arch/arm/mach-iop13xx/setup.c index 4a7f20d7fb6e..daabb1fa6c2c 100644 --- a/trunk/arch/arm/mach-iop13xx/setup.c +++ b/trunk/arch/arm/mach-iop13xx/setup.c @@ -40,6 +40,16 @@ static struct map_desc iop13xx_std_desc[] __initdata = { .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, + }, { /* PCIE IO space */ + .virtual = IOP13XX_PCIE_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), + .length = IOP13XX_PCIX_IO_WINDOW_SIZE, + .type = MT_DEVICE, + }, { /* PCIX IO space */ + .virtual = IOP13XX_PCIX_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), + .length = IOP13XX_PCIX_IO_WINDOW_SIZE, + .type = MT_DEVICE, }, }; diff --git a/trunk/arch/arm/mach-iop32x/include/mach/io.h b/trunk/arch/arm/mach-iop32x/include/mach/io.h new file mode 100644 index 000000000000..e2ada265bb8d --- /dev/null +++ b/trunk/arch/arm/mach-iop32x/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-iop32x/include/mach/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IO_H +#define __IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff +#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) + +#endif diff --git a/trunk/arch/arm/mach-iop33x/include/mach/io.h b/trunk/arch/arm/mach-iop33x/include/mach/io.h new file mode 100644 index 000000000000..f7c1b6595660 --- /dev/null +++ b/trunk/arch/arm/mach-iop33x/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-iop33x/include/mach/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IO_H +#define __IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff +#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) + +#endif diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 31d9f400ed82..c4b64adcbfce 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -42,6 +42,16 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { + .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/io.h b/trunk/arch/arm/mach-kirkwood/include/mach/io.h new file mode 100644 index 000000000000..5d0ab61700d2 --- /dev/null +++ b/trunk/arch/arm/mach-kirkwood/include/mach/io.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-kirkwood/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "kirkwood.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE) + + KIRKWOOD_PCIE_IO_VIRT_BASE); +} + +#define __io(a) __io(a) + +#endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h index af4f0000dcef..c5b68510776b 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,12 +37,14 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K +#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE_IO_SIZE SZ_64K +#define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 diff --git a/trunk/arch/arm/mach-kirkwood/pcie.c b/trunk/arch/arm/mach-kirkwood/pcie.c index 532d8acb38f9..6e8b2efa3c35 100644 --- a/trunk/arch/arm/mach-kirkwood/pcie.c +++ b/trunk/arch/arm/mach-kirkwood/pcie.c @@ -56,7 +56,7 @@ struct pcie_port { void __iomem *base; spinlock_t conf_lock; int irq; - struct resource res; + struct resource res[2]; }; static int pcie_port_map[2]; @@ -136,13 +136,21 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE; + /* + * IORESOURCE_IO + */ + pp->res[0].name = "PCIe 0 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + /* * IORESOURCE_MEM */ - pp->res.name = "PCIe 0 MEM"; - pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res.flags = IORESOURCE_MEM; + pp->res[1].name = "PCIe 0 MEM"; + pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; } static void __init pcie1_ioresources_init(struct pcie_port *pp) @@ -150,13 +158,21 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE1_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE1; + /* + * IORESOURCE_IO + */ + pp->res[0].name = "PCIe 1 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + /* * IORESOURCE_MEM */ - pp->res.name = "PCIe 1 MEM"; - pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res.flags = IORESOURCE_MEM; + pp->res[1].name = "PCIe 1 MEM"; + pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; } static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) @@ -181,21 +197,23 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) case 0: kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); - pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE); break; case 1: kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); - pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE); break; default: panic("PCIe setup: invalid controller %d", index); } - if (request_resource(&iomem_resource, &pp->res)) + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe%d IO resource failed\n", index); + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe%d Memory resource failed\n", index); - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + sys->io_offset = 0; + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); /* * Generic PCIe unit setup. diff --git a/trunk/arch/arm/mach-mv78xx0/addr-map.c b/trunk/arch/arm/mach-mv78xx0/addr-map.c index 7764d9386f2a..62b53d710efd 100644 --- a/trunk/arch/arm/mach-mv78xx0/addr-map.c +++ b/trunk/arch/arm/mach-mv78xx0/addr-map.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "common.h" /* @@ -82,7 +81,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); + TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index 20826449e61b..b4c53b846c9c 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -134,6 +134,11 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, + }, { + .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), + .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), + .length = MV78XX0_PCIE_IO_SIZE * 8, + .type = MT_DEVICE, }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/io.h b/trunk/arch/arm/mach-mv78xx0/include/mach/io.h new file mode 100644 index 000000000000..c7d9d00d8fc1 --- /dev/null +++ b/trunk/arch/arm/mach-mv78xx0/include/mach/io.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-mv78xx0/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "mv78xx0.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) + + MV78XX0_PCIE_IO_VIRT_BASE(0)); +} + +#define __io(a) __io(a) + +#endif diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index bd03fed1128e..e807c4c52a0b 100644 --- a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fee00000 f0800000 64K PCIe #0 I/O space - * fee10000 f0900000 64K PCIe #1 I/O space - * fee20000 f0a00000 64K PCIe #2 I/O space - * fee30000 f0b00000 64K PCIe #3 I/O space - * fee40000 f0c00000 64K PCIe #4 I/O space - * fee50000 f0d00000 64K PCIe #5 I/O space - * fee60000 f0e00000 64K PCIe #6 I/O space - * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers + * fe700000 f0800000 1M PCIe #0 I/O space + * fe800000 f0900000 1M PCIe #1 I/O space + * fe900000 f0a00000 1M PCIe #2 I/O space + * fea00000 f0b00000 1M PCIe #3 I/O space + * feb00000 f0c00000 1M PCIe #4 I/O space + * fec00000 f0d00000 1M PCIe #5 I/O space + * fed00000 f0e00000 1M PCIe #6 I/O space + * fee00000 f0f00000 1M PCIe #7 I/O space + * fef00000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,10 +46,11 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfd000000 +#define MV78XX0_REGS_VIRT_BASE 0xfef00000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/trunk/arch/arm/mach-mv78xx0/pcie.c b/trunk/arch/arm/mach-mv78xx0/pcie.c index 26a059b4f472..2e56e86b6d68 100644 --- a/trunk/arch/arm/mach-mv78xx0/pcie.c +++ b/trunk/arch/arm/mach-mv78xx0/pcie.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "common.h" struct pcie_port { @@ -24,13 +23,16 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; + char io_space_name[16]; char mem_space_name[16]; - struct resource res; + struct resource res[2]; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; +static struct resource pcie_mem_space; + void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -38,59 +40,102 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); } -u32 pcie_port_size[8] = { - 0, - 0x30000000, - 0x10000000, - 0x10000000, - 0x08000000, - 0x08000000, - 0x08000000, - 0x04000000, -}; - static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win = 0; + int win; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_MEM; + pcie_io_space.flags = IORESOURCE_IO; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - if (num_pcie_ports > 7) - panic("invalid number of PCIe ports"); - - size_each = pcie_port_size[num_pcie_ports]; + pcie_mem_space.name = "PCIe MEM Space"; + pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; + pcie_mem_space.end = + MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; + pcie_mem_space.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pcie_mem_space)) + panic("can't allocate PCIe MEM space"); - start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d.%d I/O", pp->maj, pp->min); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); + pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res.name = pp->mem_space_name; - pp->res.flags = IORESOURCE_MEM; - pp->res.start = start; - pp->res.end = start + size_each - 1; + pp->res[1].name = pp->mem_space_name; + pp->res[1].flags = IORESOURCE_MEM; + } + + switch (num_pcie_ports) { + case 0: + size_each = 0; + break; + + case 1: + size_each = 0x30000000; + break; + + case 2 ... 3: + size_each = 0x10000000; + break; + + case 4 ... 6: + size_each = 0x08000000; + break; + + case 7: + size_each = 0x04000000; + break; + + default: + panic("invalid number of PCIe ports"); + } + + start = MV78XX0_PCIE_MEM_PHYS_BASE; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + pp->res[1].start = start; + pp->res[1].end = start + size_each - 1; start += size_each; + } + + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; - if (request_resource(&iomem_resource, &pp->res)) + if (request_resource(&pcie_io_space, &pp->res[0])) + panic("can't allocate PCIe I/O sub-space"); + + if (request_resource(&pcie_mem_space, &pp->res[1])) panic("can't allocate PCIe MEM sub-space"); + } - mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, - resource_size(&pp->res), - pp->maj, pp->min); + win = 0; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; - mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, + mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, + resource_size(&pp->res[0]), pp->maj, pp->min); + + mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, + resource_size(&pp->res[1]), + pp->maj, pp->min); } } @@ -111,9 +156,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); - - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -237,7 +281,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(&pp->res, 0, sizeof(pp->res)); + memset(pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-orion5x/common.c b/trunk/arch/arm/mach-orion5x/common.c index 70f7d712d6f4..9148b229d0de 100644 --- a/trunk/arch/arm/mach-orion5x/common.c +++ b/trunk/arch/arm/mach-orion5x/common.c @@ -46,6 +46,16 @@ static struct map_desc orion5x_io_desc[] __initdata = { .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, + }, { + .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), + .length = ORION5X_PCIE_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = ORION5X_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), + .length = ORION5X_PCI_IO_SIZE, + .type = MT_DEVICE, }, { .virtual = ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), diff --git a/trunk/arch/arm/mach-orion5x/include/mach/io.h b/trunk/arch/arm/mach-orion5x/include/mach/io.h new file mode 100644 index 000000000000..1aa5d0a50a0b --- /dev/null +++ b/trunk/arch/arm/mach-orion5x/include/mach/io.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-orion5x/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include +#include + +#define IO_SPACE_LIMIT SZ_2M +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE); +} + +#define __io(a) __io(a) +#endif diff --git a/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h b/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h index 1b60131b7f60..683e085ce162 100644 --- a/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/trunk/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -31,29 +31,31 @@ * fc000000 device bus mappings (cs0/cs1) * * virt phys size - * fe000000 f1000000 1M on-chip peripheral registers - * fee00000 f2000000 64K PCIe I/O space - * fee10000 f2100000 64K PCI I/O space - * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfe000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_64K +#define ORION5X_PCIE_IO_SIZE SZ_1M #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_BUS_BASE 0x00010000 -#define ORION5X_PCI_IO_SIZE SZ_64K +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M #define ORION5X_SRAM_PHYS_BASE (0xf2200000) #define ORION5X_SRAM_SIZE SZ_8K /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/trunk/arch/arm/mach-orion5x/pci.c b/trunk/arch/arm/mach-orion5x/pci.c index 6921d49b988d..cb19e1661bb3 100644 --- a/trunk/arch/arm/mach-orion5x/pci.c +++ b/trunk/arch/arm/mach-orion5x/pci.c @@ -162,25 +162,35 @@ static int __init pcie_setup(struct pci_sys_data *sys) pcie_ops.read = pcie_rd_conf_wa; } - pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE); - /* * Request resources. */ - res = kzalloc(sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) panic("pcie_setup unable to alloc resources"); + /* + * IORESOURCE_IO + */ + sys->io_offset = 0; + res[0].name = "PCIe I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION5X_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); + pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); + /* * IORESOURCE_MEM */ - res->name = "PCIe Memory Space"; - res->flags = IORESOURCE_MEM; - res->start = ORION5X_PCIE_MEM_PHYS_BASE; - res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, res)) + res[1].name = "PCIe Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); return 1; } @@ -479,25 +489,35 @@ static int __init pci_setup(struct pci_sys_data *sys) */ orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); - pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE); - /* * Request resources */ - res = kzalloc(sizeof(struct resource), GFP_KERNEL); + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) panic("pci_setup unable to alloc resources"); + /* + * IORESOURCE_IO + */ + sys->io_offset = 0; + res[0].name = "PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION5X_PCI_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCI IO resource failed\n"); + pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); + /* * IORESOURCE_MEM */ - res->name = "PCI Memory Space"; - res->flags = IORESOURCE_MEM; - res->start = ORION5X_PCI_MEM_PHYS_BASE; - res->end = res->start + ORION5X_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, res)) + res[1].name = "PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION5X_PCI_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) panic("Request PCI Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); return 1; } diff --git a/trunk/arch/arm/mach-prima2/Makefile b/trunk/arch/arm/mach-prima2/Makefile index 13dd1604d951..f2cde60812a6 100644 --- a/trunk/arch/arm/mach-prima2/Makefile +++ b/trunk/arch/arm/mach-prima2/Makefile @@ -1,8 +1,7 @@ obj-y := timer.o obj-y += irq.o -obj-y += clock.o obj-y += rstc.o -obj-y += prima2.o +obj-y += common.o obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o diff --git a/trunk/arch/arm/mach-prima2/clock.c b/trunk/arch/arm/mach-prima2/clock.c deleted file mode 100644 index aebad7e565cf..000000000000 --- a/trunk/arch/arm/mach-prima2/clock.c +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Clock tree for CSR SiRFprimaII - * - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SIRFSOC_CLKC_CLK_EN0 0x0000 -#define SIRFSOC_CLKC_CLK_EN1 0x0004 -#define SIRFSOC_CLKC_REF_CFG 0x0014 -#define SIRFSOC_CLKC_CPU_CFG 0x0018 -#define SIRFSOC_CLKC_MEM_CFG 0x001c -#define SIRFSOC_CLKC_SYS_CFG 0x0020 -#define SIRFSOC_CLKC_IO_CFG 0x0024 -#define SIRFSOC_CLKC_DSP_CFG 0x0028 -#define SIRFSOC_CLKC_GFX_CFG 0x002c -#define SIRFSOC_CLKC_MM_CFG 0x0030 -#define SIRFSOC_LKC_LCD_CFG 0x0034 -#define SIRFSOC_CLKC_MMC_CFG 0x0038 -#define SIRFSOC_CLKC_PLL1_CFG0 0x0040 -#define SIRFSOC_CLKC_PLL2_CFG0 0x0044 -#define SIRFSOC_CLKC_PLL3_CFG0 0x0048 -#define SIRFSOC_CLKC_PLL1_CFG1 0x004c -#define SIRFSOC_CLKC_PLL2_CFG1 0x0050 -#define SIRFSOC_CLKC_PLL3_CFG1 0x0054 -#define SIRFSOC_CLKC_PLL1_CFG2 0x0058 -#define SIRFSOC_CLKC_PLL2_CFG2 0x005c -#define SIRFSOC_CLKC_PLL3_CFG2 0x0060 - -#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000) - -#define KHZ 1000 -#define MHZ (KHZ * KHZ) - -struct clk_ops { - unsigned long (*get_rate)(struct clk *clk); - long (*round_rate)(struct clk *clk, unsigned long rate); - int (*set_rate)(struct clk *clk, unsigned long rate); - int (*enable)(struct clk *clk); - int (*disable)(struct clk *clk); - struct clk *(*get_parent)(struct clk *clk); - int (*set_parent)(struct clk *clk, struct clk *parent); -}; - -struct clk { - struct clk *parent; /* parent clk */ - unsigned long rate; /* clock rate in Hz */ - signed char usage; /* clock enable count */ - signed char enable_bit; /* enable bit: 0 ~ 63 */ - unsigned short regofs; /* register offset */ - struct clk_ops *ops; /* clock operation */ -}; - -static DEFINE_SPINLOCK(clocks_lock); - -static inline unsigned long clkc_readl(unsigned reg) -{ - return readl(SIRFSOC_CLOCK_VA_BASE + reg); -} - -static inline void clkc_writel(u32 val, unsigned reg) -{ - writel(val, SIRFSOC_CLOCK_VA_BASE + reg); -} - -/* - * osc_rtc - real time oscillator - 32.768KHz - * osc_sys - high speed oscillator - 26MHz - */ - -static struct clk clk_rtc = { - .rate = 32768, -}; - -static struct clk clk_osc = { - .rate = 26 * MHZ, -}; - -/* - * std pll - */ -static unsigned long std_pll_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - - SIRFSOC_CLKC_PLL1_CFG0; - - if (clkc_readl(regcfg2) & BIT(2)) { - /* pll bypass mode */ - clk->rate = fin; - } else { - /* fout = fin * nf / nr / od */ - u32 cfg0 = clkc_readl(clk->regofs); - u32 nf = (cfg0 & (BIT(13) - 1)) + 1; - u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; - u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; - WARN_ON(fin % MHZ); - clk->rate = fin / MHZ * nf / nr / od * MHZ; - } - - return clk->rate; -} - -static int std_pll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin, nf, nr, od, reg; - - /* - * fout = fin * nf / (nr * od); - * set od = 1, nr = fin/MHz, so fout = nf * MHz - */ - - nf = rate / MHZ; - if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) - return -EINVAL; - - fin = clk_get_rate(clk->parent); - BUG_ON(fin < MHZ); - - nr = fin / MHZ; - BUG_ON((fin % MHZ) || nr > BIT(6)); - - od = 1; - - reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); - clkc_writel(reg, clk->regofs); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; - clkc_writel((nf >> 1) - 1, reg); - - reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; - while (!(clkc_readl(reg) & BIT(6))) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - return 0; -} - -static struct clk_ops std_pll_ops = { - .get_rate = std_pll_get_rate, - .set_rate = std_pll_set_rate, -}; - -static struct clk clk_pll1 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL1_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll2 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL2_CFG0, - .ops = &std_pll_ops, -}; - -static struct clk clk_pll3 = { - .parent = &clk_osc, - .regofs = SIRFSOC_CLKC_PLL3_CFG0, - .ops = &std_pll_ops, -}; - -/* - * clock domains - cpu, mem, sys/io - */ - -static struct clk clk_mem; - -static struct clk *dmn_get_parent(struct clk *clk) -{ - struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - WARN_ON((cfg & (BIT(3) - 1)) > 4); - return clks[cfg & (BIT(3) - 1)]; -} - -static int dmn_set_parent(struct clk *clk, struct clk *parent) -{ - const struct clk *clks[] = { - &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3 - }; - u32 cfg = clkc_readl(clk->regofs); - int i; - for (i = 0; i < ARRAY_SIZE(clks); i++) { - if (clks[i] == parent) { - cfg &= ~(BIT(3) - 1); - clkc_writel(cfg | i, clk->regofs); - /* BIT(3) - switching status: 1 - busy, 0 - done */ - while (clkc_readl(clk->regofs) & BIT(3)) - cpu_relax(); - return 0; - } - } - return -EINVAL; -} - -static unsigned long dmn_get_rate(struct clk *clk) -{ - unsigned long fin = clk_get_rate(clk->parent); - u32 cfg = clkc_readl(clk->regofs); - if (cfg & BIT(24)) { - /* fcd bypass mode */ - clk->rate = fin; - } else { - /* - * wait count: bit[19:16], hold count: bit[23:20] - */ - u32 wait = (cfg >> 16) & (BIT(4) - 1); - u32 hold = (cfg >> 20) & (BIT(4) - 1); - - clk->rate = fin / (wait + hold + 2); - } - - return clk->rate; -} - -static int dmn_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long fin; - unsigned ratio, wait, hold, reg; - unsigned bits = (clk == &clk_mem) ? 3 : 4; - - fin = clk_get_rate(clk->parent); - ratio = fin / rate; - - if (unlikely(ratio < 2 || ratio > BIT(bits + 1))) - return -EINVAL; - - WARN_ON(fin % rate); - - wait = (ratio >> 1) - 1; - hold = ratio - wait - 2; - - reg = clkc_readl(clk->regofs); - reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); - reg |= (wait << 16) | (hold << 20) | BIT(25); - clkc_writel(reg, clk->regofs); - - /* waiting FCD been effective */ - while (clkc_readl(clk->regofs) & BIT(25)) - cpu_relax(); - - clk->rate = 0; /* set to zero will force recalculation */ - - return 0; -} - -/* - * cpu clock has no FCD register in Prima2, can only change pll - */ -static int cpu_set_rate(struct clk *clk, unsigned long rate) -{ - int ret1, ret2; - struct clk *cur_parent, *tmp_parent; - - cur_parent = dmn_get_parent(clk); - BUG_ON(cur_parent == NULL || cur_parent->usage > 1); - - /* switch to tmp pll before setting parent clock's rate */ - tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1; - ret1 = dmn_set_parent(clk, tmp_parent); - BUG_ON(ret1); - - ret2 = clk_set_rate(cur_parent, rate); - - ret1 = dmn_set_parent(clk, cur_parent); - - clk->rate = 0; /* set to zero will force recalculation */ - - return ret2 ? ret2 : ret1; -} - -static struct clk_ops cpu_ops = { - .get_parent = dmn_get_parent, - .set_parent = dmn_set_parent, - .set_rate = cpu_set_rate, -}; - -static struct clk clk_cpu = { - .parent = &clk_pll1, - .regofs = SIRFSOC_CLKC_CPU_CFG, - .ops = &cpu_ops, -}; - - -static struct clk_ops msi_ops = { - .set_rate = dmn_set_rate, - .get_rate = dmn_get_rate, - .set_parent = dmn_set_parent, - .get_parent = dmn_get_parent, -}; - -static struct clk clk_mem = { - .parent = &clk_pll2, - .regofs = SIRFSOC_CLKC_MEM_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_sys = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_SYS_CFG, - .ops = &msi_ops, -}; - -static struct clk clk_io = { - .parent = &clk_pll3, - .regofs = SIRFSOC_CLKC_IO_CFG, - .ops = &msi_ops, -}; - -/* - * on-chip clock sets - */ -static struct clk_lookup onchip_clks[] = { - { - .dev_id = "rtc", - .clk = &clk_rtc, - }, { - .dev_id = "osc", - .clk = &clk_osc, - }, { - .dev_id = "pll1", - .clk = &clk_pll1, - }, { - .dev_id = "pll2", - .clk = &clk_pll2, - }, { - .dev_id = "pll3", - .clk = &clk_pll3, - }, { - .dev_id = "cpu", - .clk = &clk_cpu, - }, { - .dev_id = "mem", - .clk = &clk_mem, - }, { - .dev_id = "sys", - .clk = &clk_sys, - }, { - .dev_id = "io", - .clk = &clk_io, - }, -}; - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, flags); - if (!clk->usage++ && clk->ops && clk->ops->enable) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return; - - WARN_ON(!clk->usage); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->usage == 0 && clk->ops && clk->ops->disable) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->rate) - return clk->rate; - - if (clk->ops && clk->ops->get_rate) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return 0; - - if (clk->ops && clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_rate) - return -EINVAL; - - return clk->ops->set_rate(clk, rate); -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret; - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return -EINVAL; - - if (!clk->ops || !clk->ops->set_parent) - return -EINVAL; - - spin_lock_irqsave(&clocks_lock, flags); - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - BUG_ON(clk->parent->usage < 0); - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, flags); - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - unsigned long flags; - - if (unlikely(IS_ERR_OR_NULL(clk))) - return NULL; - - if (!clk->ops || !clk->ops->get_parent) - return clk->parent; - - spin_lock_irqsave(&clocks_lock, flags); - clk->parent = clk->ops->get_parent(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static void __init sirfsoc_clk_init(void) -{ - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); -} - -static struct of_device_id clkc_ids[] = { - { .compatible = "sirf,prima2-clkc" }, - {}, -}; - -void __init sirfsoc_of_clk_init(void) -{ - struct device_node *np; - struct resource res; - struct map_desc sirfsoc_clkc_iodesc = { - .virtual = SIRFSOC_CLOCK_VA_BASE, - .type = MT_DEVICE, - }; - - np = of_find_matching_node(NULL, clkc_ids); - if (!np) - panic("unable to find compatible clkc node in dtb\n"); - - if (of_address_to_resource(np, 0, &res)) - panic("unable to find clkc range in dtb"); - of_node_put(np); - - sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start); - sirfsoc_clkc_iodesc.length = 1 + res.end - res.start; - - iotable_init(&sirfsoc_clkc_iodesc, 1); - - sirfsoc_clk_init(); -} diff --git a/trunk/arch/arm/mach-prima2/prima2.c b/trunk/arch/arm/mach-prima2/common.c similarity index 81% rename from trunk/arch/arm/mach-prima2/prima2.c rename to trunk/arch/arm/mach-prima2/common.c index 8f0429d4b79f..f25a54194639 100644 --- a/trunk/arch/arm/mach-prima2/prima2.c +++ b/trunk/arch/arm/mach-prima2/common.c @@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void) sirfsoc_pm_init(); } -static const char *prima2cb_dt_match[] __initdata = { - "sirf,prima2-cb", +#ifdef CONFIG_ARCH_PRIMA2 +static const char *prima2_dt_match[] __initdata = { + "sirf,prima2", NULL }; -MACHINE_START(PRIMA2_EVB, "prima2cb") +DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song */ - .atag_offset = 0x100, - .init_early = sirfsoc_of_clk_init, .map_io = sirfsoc_map_lluart, .init_irq = sirfsoc_of_irq_init, .timer = &sirfsoc_timer, .dma_zone_size = SZ_256M, .init_machine = sirfsoc_mach_init, .init_late = sirfsoc_init_late, - .dt_compat = prima2cb_dt_match, + .dt_compat = prima2_dt_match, .restart = sirfsoc_restart, MACHINE_END +#endif diff --git a/trunk/arch/arm/mach-prima2/timer.c b/trunk/arch/arm/mach-prima2/timer.c index f224107de7bc..d95bf252f694 100644 --- a/trunk/arch/arm/mach-prima2/timer.c +++ b/trunk/arch/arm/mach-prima2/timer.c @@ -21,6 +21,8 @@ #include #include +#include "common.h" + #define SIRFSOC_TIMER_COUNTER_LO 0x0000 #define SIRFSOC_TIMER_COUNTER_HI 0x0004 #define SIRFSOC_TIMER_MATCH_0 0x0008 @@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void) static void __init sirfsoc_timer_init(void) { unsigned long rate; + struct clk *clk; + + /* initialize clocking early, we want to set the OS timer */ + sirfsoc_of_clk_init(); /* timer's input clock is io clock */ - struct clk *clk = clk_get_sys("io", NULL); + clk = clk_get_sys("io", NULL); BUG_ON(IS_ERR(clk)); diff --git a/trunk/arch/arm/mach-shark/core.c b/trunk/arch/arm/mach-shark/core.c index d35b94ef73b7..2704bcd869cd 100644 --- a/trunk/arch/arm/mach-shark/core.c +++ b/trunk/arch/arm/mach-shark/core.c @@ -21,6 +21,9 @@ #include #include +#define IO_BASE 0xe0000000 +#define IO_SIZE 0x08000000 +#define IO_START 0x40000000 #define ROMCARD_SIZE 0x08000000 #define ROMCARD_START 0x10000000 @@ -101,6 +104,20 @@ arch_initcall(shark_init); extern void shark_init_irq(void); +static struct map_desc shark_io_desc[] __initdata = { + { + .virtual = IO_BASE, + .pfn = __phys_to_pfn(IO_START), + .length = IO_SIZE, + .type = MT_DEVICE + } +}; + +static void __init shark_map_io(void) +{ + iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc)); +} + #define IRQ_TIMER 0 #define HZ_TIME ((1193180 + HZ/2) / HZ) @@ -141,6 +158,7 @@ static void shark_init_early(void) MACHINE_START(SHARK, "Shark") /* Maintainer: Alexander Schulz */ .atag_offset = 0x3000, + .map_io = shark_map_io, .init_early = shark_init_early, .init_irq = shark_init_irq, .timer = &shark_timer, diff --git a/trunk/arch/arm/mach-shark/include/mach/debug-macro.S b/trunk/arch/arm/mach-shark/include/mach/debug-macro.S index d129119a3f69..20eb2bf2a42b 100644 --- a/trunk/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-shark/include/mach/debug-macro.S @@ -12,10 +12,9 @@ */ .macro addruart, rp, rv, tmp - mov \rp, #0x3f8 - orr \rv, \rp, #0xfe000000 - orr \rv, \rv, #0x00e00000 - orr \rp, \rp, #0x40000000 + mov \rp, #0xe0000000 + orr \rp, \rp, #0x000003f8 + mov \rv, \rp .endm .macro senduart,rd,rx diff --git a/trunk/arch/arm/mach-shark/include/mach/entry-macro.S b/trunk/arch/arm/mach-shark/include/mach/entry-macro.S index c9e49f049532..5901b09fc96a 100644 --- a/trunk/arch/arm/mach-shark/include/mach/entry-macro.S +++ b/trunk/arch/arm/mach-shark/include/mach/entry-macro.S @@ -8,8 +8,7 @@ * warranty of any kind, whether express or implied. */ .macro get_irqnr_preamble, base, tmp - mov \base, #0xfe000000 - orr \base, \base, #0x00e00000 + mov \base, #0xe0000000 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/trunk/arch/arm/mach-shark/include/mach/io.h b/trunk/arch/arm/mach-shark/include/mach/io.h new file mode 100644 index 000000000000..1a45fc01ff1d --- /dev/null +++ b/trunk/arch/arm/mach-shark/include/mach/io.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-shark/include/mach/io.h + * + * by Alexander Schulz + * + * derived from: + * arch/arm/mach-ebsa110/include/mach/io.h + * Copyright (C) 1997,1998 Russell King + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(0xe0000000 + (a))) + +#endif diff --git a/trunk/arch/arm/mach-shark/pci.c b/trunk/arch/arm/mach-shark/pci.c index b8b4ab323a3e..9089407d5326 100644 --- a/trunk/arch/arm/mach-shark/pci.c +++ b/trunk/arch/arm/mach-shark/pci.c @@ -8,15 +8,12 @@ #include #include #include -#include #include