From b2e113d6488256b5a6ec7885fc4e8ac3f4f88ea4 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Sun, 22 Apr 2012 12:01:19 +0200 Subject: [PATCH] --- yaml --- r: 303192 b: refs/heads/master c: 4de02e4a280678224bd12ec3b182e369c87c8fc5 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/Documentation/arm/SPEAr/overview.txt | 13 +- .../devicetree/bindings/arm/spear.txt | 18 - .../devicetree/bindings/net/lpc-eth.txt | 24 + trunk/arch/arm/boot/dts/omap3-beagle.dts | 49 -- trunk/arch/arm/boot/dts/omap3.dtsi | 102 ----- trunk/arch/arm/boot/dts/omap4-panda.dts | 56 --- trunk/arch/arm/boot/dts/omap4-sdp.dts | 97 ---- trunk/arch/arm/boot/dts/omap4.dtsi | 117 ----- trunk/arch/arm/boot/dts/sh7372.dtsi | 21 - trunk/arch/arm/boot/dts/spear300-evb.dts | 183 -------- trunk/arch/arm/boot/dts/spear300.dtsi | 72 --- trunk/arch/arm/boot/dts/spear310-evb.dts | 111 ----- trunk/arch/arm/boot/dts/spear310.dtsi | 75 ---- trunk/arch/arm/boot/dts/spear320-evb.dts | 112 ----- trunk/arch/arm/boot/dts/spear320.dtsi | 90 ---- trunk/arch/arm/boot/dts/spear3xx.dtsi | 144 ------ trunk/arch/arm/boot/dts/spear600-evb.dts | 4 - trunk/arch/arm/boot/dts/spear600.dtsi | 8 - trunk/arch/arm/boot/dts/twl4030.dtsi | 39 -- trunk/arch/arm/boot/dts/twl6030.dtsi | 86 ---- trunk/arch/arm/configs/spear3xx_defconfig | 52 +-- trunk/arch/arm/configs/spear6xx_defconfig | 41 +- trunk/arch/arm/mach-omap2/board-generic.c | 37 +- trunk/arch/arm/mach-omap2/devices.c | 4 +- trunk/arch/arm/mach-omap2/gpio.c | 8 +- .../arm/mach-shmobile/include/mach/common.h | 2 - .../arm/mach-shmobile/include/mach/intc.h | 44 -- .../arm/mach-shmobile/include/mach/irqs.h | 2 +- trunk/arch/arm/mach-shmobile/intc-sh7372.c | 34 +- trunk/arch/arm/mach-shmobile/setup-sh7372.c | 48 -- trunk/arch/arm/mach-shmobile/timer.c | 17 - trunk/arch/arm/mach-spear3xx/Kconfig | 34 +- trunk/arch/arm/mach-spear3xx/Makefile | 13 +- trunk/arch/arm/mach-spear3xx/Makefile.boot | 4 - trunk/arch/arm/mach-spear3xx/clock.c | 280 ++++-------- .../arm/mach-spear3xx/include/mach/generic.h | 42 +- .../arm/mach-spear3xx/include/mach/hardware.h | 24 +- .../arm/mach-spear3xx/include/mach/irqs.h | 130 +++++- .../mach-spear3xx/include/mach/misc_regs.h | 144 ++++++ .../arm/mach-spear3xx/include/mach/spear.h | 47 +- .../arm/mach-spear3xx/include/mach/spear300.h | 54 +++ .../arm/mach-spear3xx/include/mach/spear310.h | 58 +++ .../arm/mach-spear3xx/include/mach/spear320.h | 67 +++ trunk/arch/arm/mach-spear3xx/spear300.c | 335 ++------------ trunk/arch/arm/mach-spear3xx/spear300_evb.c | 75 ++++ trunk/arch/arm/mach-spear3xx/spear310.c | 391 +--------------- trunk/arch/arm/mach-spear3xx/spear310_evb.c | 81 ++++ trunk/arch/arm/mach-spear3xx/spear320.c | 390 +--------------- trunk/arch/arm/mach-spear3xx/spear320_evb.c | 79 ++++ trunk/arch/arm/mach-spear3xx/spear3xx.c | 152 +++---- trunk/arch/arm/mach-spear6xx/Makefile.boot | 2 - trunk/arch/arm/mach-spear6xx/clock.c | 186 ++------ .../arm/mach-spear6xx/include/mach/generic.h | 29 +- .../arm/mach-spear6xx/include/mach/hardware.h | 24 +- .../arm/mach-spear6xx/include/mach/irqs.h | 75 +++- .../mach-spear6xx/include/mach/misc_regs.h | 154 +++++++ .../arm/mach-spear6xx/include/mach/spear.h | 55 ++- .../arm/mach-spear6xx/include/mach/spear600.h | 21 + trunk/arch/arm/mach-spear6xx/spear6xx.c | 417 +----------------- trunk/arch/arm/plat-spear/Kconfig | 3 +- trunk/arch/arm/plat-spear/Makefile | 2 +- .../arm/plat-spear/include/plat/debug-macro.S | 2 +- .../arm/plat-spear/include/plat/hardware.h | 17 + .../arch/arm/plat-spear/include/plat/pl080.h | 21 - .../arm/plat-spear/include/plat/uncompress.h | 2 +- trunk/arch/arm/plat-spear/pl080.c | 80 ---- trunk/arch/arm/plat-spear/restart.c | 2 +- trunk/arch/arm/plat-spear/time.c | 17 +- trunk/drivers/net/ethernet/nxp/lpc_eth.c | 71 ++- trunk/drivers/of/address.c | 1 - 71 files changed, 1632 insertions(+), 3661 deletions(-) create mode 100644 trunk/Documentation/devicetree/bindings/net/lpc-eth.txt delete mode 100644 trunk/arch/arm/boot/dts/sh7372.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear300-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear300.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear310-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear310.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear320-evb.dts delete mode 100644 trunk/arch/arm/boot/dts/spear320.dtsi delete mode 100644 trunk/arch/arm/boot/dts/spear3xx.dtsi delete mode 100644 trunk/arch/arm/boot/dts/twl4030.dtsi delete mode 100644 trunk/arch/arm/boot/dts/twl6030.dtsi create mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear300.h create mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear310.h create mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear320.h create mode 100644 trunk/arch/arm/mach-spear3xx/spear300_evb.c create mode 100644 trunk/arch/arm/mach-spear3xx/spear310_evb.c create mode 100644 trunk/arch/arm/mach-spear3xx/spear320_evb.c create mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/spear600.h create mode 100644 trunk/arch/arm/plat-spear/include/plat/hardware.h delete mode 100644 trunk/arch/arm/plat-spear/include/plat/pl080.h delete mode 100644 trunk/arch/arm/plat-spear/pl080.c diff --git a/[refs] b/[refs] index 4244613341b1..905428dd7c42 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 48bfdb216ed7a2a75aa2909869f3266b3736f88a +refs/heads/master: 4de02e4a280678224bd12ec3b182e369c87c8fc5 diff --git a/trunk/Documentation/arm/SPEAr/overview.txt b/trunk/Documentation/arm/SPEAr/overview.txt index 28a9af953b9d..253a35c6f782 100644 --- a/trunk/Documentation/arm/SPEAr/overview.txt +++ b/trunk/Documentation/arm/SPEAr/overview.txt @@ -17,14 +17,14 @@ Introduction SPEAr (Platform) - SPEAr3XX (3XX SOC series, based on ARM9) - SPEAr300 (SOC) - - SPEAr300 Evaluation Board + - SPEAr300_EVB (Evaluation Board) - SPEAr310 (SOC) - - SPEAr310 Evaluation Board + - SPEAr310_EVB (Evaluation Board) - SPEAr320 (SOC) - - SPEAr320 Evaluation Board + - SPEAr320_EVB (Evaluation Board) - SPEAr6XX (6XX SOC series, based on ARM9) - SPEAr600 (SOC) - - SPEAr600 Evaluation Board + - SPEAr600_EVB (Evaluation Board) - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) - SPEAr1300 (SOC) @@ -51,11 +51,10 @@ Introduction Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine specific files, like spear300.c, spear310.c, spear320.c and spear600.c. - mach-spear* doesn't contains board specific files as they fully support - Flattened Device Tree. + mach-spear* also contains board specific files for each machine type. Document Author --------------- - Viresh Kumar , (c) 2010-2012 ST Microelectronics + Viresh Kumar, (c) 2010 ST Microelectronics diff --git a/trunk/Documentation/devicetree/bindings/arm/spear.txt b/trunk/Documentation/devicetree/bindings/arm/spear.txt index aa5f355cc947..f8e54f092328 100644 --- a/trunk/Documentation/devicetree/bindings/arm/spear.txt +++ b/trunk/Documentation/devicetree/bindings/arm/spear.txt @@ -6,21 +6,3 @@ Boards with the ST SPEAr600 SoC shall have the following properties: Required root node property: compatible = "st,spear600"; - -Boards with the ST SPEAr300 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear300"; - -Boards with the ST SPEAr310 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear310"; - -Boards with the ST SPEAr320 SoC shall have the following properties: - -Required root node property: - -compatible = "st,spear320"; diff --git a/trunk/Documentation/devicetree/bindings/net/lpc-eth.txt b/trunk/Documentation/devicetree/bindings/net/lpc-eth.txt new file mode 100644 index 000000000000..585021acd178 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/net/lpc-eth.txt @@ -0,0 +1,24 @@ +* NXP LPC32xx SoC Ethernet Controller + +Required properties: +- compatible: Should be "nxp,lpc-eth" +- reg: Address and length of the register set for the device +- interrupts: Should contain ethernet controller interrupt + +Optional properties: +- phy-mode: String, operation mode of the PHY interface. + Supported values are: "mii", "rmii" (default) +- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering +- local-mac-address : 6 bytes, mac address + +Example: + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupt-parent = <&mic>; + interrupts = <29 0>; + + phy-mode = "rmii"; + use-iram; + }; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts index 8c756be4d7ad..9f72cd4cf308 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts @@ -18,52 +18,3 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; }; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - vsim: regulator@10 { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; -}; - -/include/ "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - ti,bus-width = <8>; -}; - -&mmc2 { - status = "disable"; -}; - -&mmc3 { - status = "disable"; -}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index 99474fa5fac4..c6121357c1eb 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -69,60 +69,6 @@ reg = <0x48200000 0x1000>; }; - gpio1: gpio@48310000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio2: gpio@49050000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio3: gpio@49052000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio4: gpio@49054000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio5: gpio@49056000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio6: gpio@49058000 { - compatible = "ti,omap3-gpio"; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - uart1: serial@4806a000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; @@ -167,53 +113,5 @@ #size-cells = <0>; ti,hwmods = "i2c3"; }; - - mcspi1: spi@48098000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap2-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc1"; - ti,dual-volt; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc2"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap3-hsmmc"; - ti,hwmods = "mmc3"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap4-panda.dts b/trunk/arch/arm/boot/dts/omap4-panda.dts index ea6f5bb8a120..9755ad5917f8 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda.dts @@ -18,59 +18,3 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; }; - -&i2c1 { - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; - }; -}; - -/include/ "twl6030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in their EEPROM as EDID data. - * The EEPROM is connected as I2C slave device. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - ti,bus-width = <8>; -}; - -&mmc2 { - status = "disable"; -}; - -&mmc3 { - status = "disable"; -}; - -&mmc4 { - status = "disable"; -}; - -&mmc5 { - ti,non-removable; - ti,bus-width = <4>; -}; diff --git a/trunk/arch/arm/boot/dts/omap4-sdp.dts b/trunk/arch/arm/boot/dts/omap4-sdp.dts index 67b2e98074c6..63c6b2b2bf42 100644 --- a/trunk/arch/arm/boot/dts/omap4-sdp.dts +++ b/trunk/arch/arm/boot/dts/omap4-sdp.dts @@ -17,101 +17,4 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; - - vdd_eth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 16 0>; /* gpio line 48 */ - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; - }; -}; - -/include/ "twl6030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf - */ - tmp105@48 { - compatible = "ti,tmp105"; - reg = <0x48>; - }; - - /* - * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf - */ - bh1780@29 { - compatible = "rohm,bh1780"; - reg = <0x29>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - - /* - * 3-Axis Digital Compass - * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf - */ - hmc5843@1e { - compatible = "honeywell,hmc5843"; - reg = <0x1e>; - }; -}; - -&mcspi1 { - eth@0 { - compatible = "ks8851"; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <2>; /* gpio line 34 */ - vdd-supply = <&vdd_eth>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - ti,bus-width = <8>; -}; - -&mmc2 { - vmmc-supply = <&vaux1>; - ti,bus-width = <8>; - ti,non-removable; -}; - -&mmc3 { - status = "disable"; -}; - -&mmc4 { - status = "disable"; -}; - -&mmc5 { - ti,bus-width = <4>; - ti,non-removable; }; diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index 359c4979c8aa..3d35559e77bc 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -104,60 +104,6 @@ <0x48240100 0x0100>; }; - gpio1: gpio@4a310000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <1>; - }; - uart1: serial@4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; @@ -209,68 +155,5 @@ #size-cells = <0>; ti,hwmods = "i2c4"; }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/sh7372.dtsi b/trunk/arch/arm/boot/dts/sh7372.dtsi deleted file mode 100644 index 677fc603f8b3..000000000000 --- a/trunk/arch/arm/boot/dts/sh7372.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Device Tree Source for the sh7372 SoC - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,sh7372"; - - cpus { - cpu@0 { - compatible = "arm,cortex-a8"; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear300-evb.dts b/trunk/arch/arm/boot/dts/spear300-evb.dts deleted file mode 100644 index eaecc29b9d81..000000000000 --- a/trunk/arch/arm/boot/dts/spear300-evb.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * DTS file for SPEAr300 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear300.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - clcd@60000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@94000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - int-gpio = <&gpio1 0 0>; - power-gpio = <&gpio1 2 1>; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - gpio1: gpio@a9000000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - kbd@a0000000 { - linux,keymap = < 0x00010000 - 0x00020100 - 0x00030200 - 0x00040300 - 0x00050400 - 0x00060500 - 0x00070600 - 0x00080700 - 0x00090800 - 0x000a0001 - 0x000c0101 - 0x000d0201 - 0x000e0301 - 0x000f0401 - 0x00100501 - 0x00110601 - 0x00120701 - 0x00130801 - 0x00140002 - 0x00150102 - 0x00160202 - 0x00170302 - 0x00180402 - 0x00190502 - 0x001a0602 - 0x001b0702 - 0x001c0802 - 0x001d0003 - 0x001e0103 - 0x001f0203 - 0x00200303 - 0x00210403 - 0x00220503 - 0x00230603 - 0x00240703 - 0x00250803 - 0x00260004 - 0x00270104 - 0x00280204 - 0x00290304 - 0x002a0404 - 0x002b0504 - 0x002c0604 - 0x002d0704 - 0x002e0804 - 0x002f0005 - 0x00300105 - 0x00310205 - 0x00320305 - 0x00330405 - 0x00340505 - 0x00350605 - 0x00360705 - 0x00370805 - 0x00380006 - 0x00390106 - 0x003a0206 - 0x003b0306 - 0x003c0406 - 0x003d0506 - 0x003e0606 - 0x003f0706 - 0x00400806 - 0x00410007 - 0x00420107 - 0x00430207 - 0x00440307 - 0x00450407 - 0x00460507 - 0x00470607 - 0x00480707 - 0x00490807 - 0x004a0008 - 0x004b0108 - 0x004c0208 - 0x004d0308 - 0x004e0408 - 0x004f0508 - 0x00500608 - 0x00510708 - 0x00520808 >; - autorepeat; - st,mode = <0>; - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear300.dtsi b/trunk/arch/arm/boot/dts/spear300.dtsi deleted file mode 100644 index f9fcbf4f477b..000000000000 --- a/trunk/arch/arm/boot/dts/spear300.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -/* - * DTS file for SPEAr300 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x60000000 0x60000000 0x50000000 - 0xd0000000 0xd0000000 0x30000000>; - - clcd@60000000 { - compatible = "arm,clcd-pl110", "arm,primecell"; - reg = <0x60000000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - fsmc: flash@94000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <1>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - gpio1: gpio@a9000000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0xa9000000 0x1000>; - status = "disabled"; - }; - - kbd@a0000000 { - compatible = "st,spear300-kbd"; - reg = <0xa0000000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear310-evb.dts b/trunk/arch/arm/boot/dts/spear310-evb.dts deleted file mode 100644 index c86af33f700e..000000000000 --- a/trunk/arch/arm/boot/dts/spear310-evb.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * DTS file for SPEAr310 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear310.dtsi" - -/ { - model = "ST SPEAr310 Evaluation Board"; - compatible = "st,spear310-evb", "st,spear310"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@44000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - clock-rate=<50000000>; - - flash@f8000000 { - label = "m25p64"; - reg = <0xf8000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - st,smi-fast-mode; - }; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - serial@b2000000 { - status = "okay"; - }; - - serial@b2080000 { - status = "okay"; - }; - - serial@b2100000 { - status = "okay"; - }; - - serial@b2180000 { - status = "okay"; - }; - - serial@b2200000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear310.dtsi b/trunk/arch/arm/boot/dts/spear310.dtsi deleted file mode 100644 index dc7fa14da846..000000000000 --- a/trunk/arch/arm/boot/dts/spear310.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -/* - * DTS file for SPEAr310 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - fsmc: flash@44000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x10000>; - st,cle-off = <0x20000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - serial@b2000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2000000 0x1000>; - status = "disabled"; - }; - - serial@b2080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2080000 0x1000>; - status = "disabled"; - }; - - serial@b2100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2100000 0x1000>; - status = "disabled"; - }; - - serial@b2180000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2180000 0x1000>; - status = "disabled"; - }; - - serial@b2200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xb2200000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear320-evb.dts b/trunk/arch/arm/boot/dts/spear320-evb.dts deleted file mode 100644 index d43de712e863..000000000000 --- a/trunk/arch/arm/boot/dts/spear320-evb.dts +++ /dev/null @@ -1,112 +0,0 @@ -/* - * DTS file for SPEAr320 Evaluation Baord - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "spear320.dtsi" - -/ { - model = "ST SPEAr300 Evaluation Board"; - compatible = "st,spear300-evb", "st,spear300"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0 0x40000000>; - }; - - ahb { - clcd@90000000 { - status = "okay"; - }; - - dma@fc400000 { - status = "okay"; - }; - - fsmc: flash@4c000000 { - status = "okay"; - }; - - gmac: eth@e0800000 { - status = "okay"; - }; - - sdhci@70000000 { - power-gpio = <&gpio0 2 1>; - power_always_enb; - status = "okay"; - }; - - smi: flash@fc000000 { - status = "okay"; - }; - - spi0: spi@d0100000 { - status = "okay"; - }; - - spi1: spi@a5000000 { - status = "okay"; - }; - - spi2: spi@a6000000 { - status = "okay"; - }; - - ehci@e1800000 { - status = "okay"; - }; - - ohci@e1900000 { - status = "okay"; - }; - - ohci@e2100000 { - status = "okay"; - }; - - apb { - gpio0: gpio@fc980000 { - status = "okay"; - }; - - i2c0: i2c@d0180000 { - status = "okay"; - }; - - i2c1: i2c@a7000000 { - status = "okay"; - }; - - rtc@fc900000 { - status = "okay"; - }; - - serial@d0000000 { - status = "okay"; - }; - - serial@a3000000 { - status = "okay"; - }; - - serial@a4000000 { - status = "okay"; - }; - - wdt@fc880000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear320.dtsi b/trunk/arch/arm/boot/dts/spear320.dtsi deleted file mode 100644 index 9a0267a5a0b7..000000000000 --- a/trunk/arch/arm/boot/dts/spear320.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -/* - * DTS file for SPEAr320 SoC - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "spear3xx.dtsi" - -/ { - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x70000000 - 0xd0000000 0xd0000000 0x30000000>; - - clcd@90000000 { - compatible = "arm,clcd-pl110", "arm,primecell"; - reg = <0x90000000 0x1000>; - interrupts = <33>; - status = "disabled"; - }; - - fsmc: flash@4c000000 { - compatible = "st,spear600-fsmc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; - status = "disabled"; - }; - - sdhci@70000000 { - compatible = "st,sdhci-spear"; - reg = <0x70000000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - spi1: spi@a5000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa5000000 0x1000>; - status = "disabled"; - }; - - spi2: spi@a6000000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xa6000000 0x1000>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xa0000000 0xa0000000 0x10000000 - 0xd0000000 0xd0000000 0x30000000>; - - i2c1: i2c@a7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xa7000000 0x1000>; - status = "disabled"; - }; - - serial@a3000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa3000000 0x1000>; - status = "disabled"; - }; - - serial@a4000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xa4000000 0x1000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear3xx.dtsi b/trunk/arch/arm/boot/dts/spear3xx.dtsi deleted file mode 100644 index 0ae7c8e86311..000000000000 --- a/trunk/arch/arm/boot/dts/spear3xx.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -/* - * DTS file for all SPEAr3xx SoCs - * - * Copyright 2012 Viresh Kumar - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - interrupt-parent = <&vic>; - - cpus { - cpu@0 { - compatible = "arm,arm926ejs"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x40000000>; - }; - - ahb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - vic: interrupt-controller@f1100000 { - compatible = "arm,pl190-vic"; - interrupt-controller; - reg = <0xf1100000 0x1000>; - #interrupt-cells = <1>; - }; - - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic>; - interrupts = <8>; - status = "disabled"; - }; - - gmac: eth@e0800000 { - compatible = "st,spear600-gmac"; - reg = <0xe0800000 0x8000>; - interrupts = <23 22>; - interrupt-names = "macirq", "eth_wake_irq"; - status = "disabled"; - }; - - smi: flash@fc000000 { - compatible = "st,spear600-smi"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xfc000000 0x1000>; - interrupts = <9>; - status = "disabled"; - }; - - spi0: spi@d0100000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0xd0100000 0x1000>; - interrupts = <20>; - status = "disabled"; - }; - - ehci@e1800000 { - compatible = "st,spear600-ehci", "usb-ehci"; - reg = <0xe1800000 0x1000>; - interrupts = <26>; - status = "disabled"; - }; - - ohci@e1900000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe1900000 0x1000>; - interrupts = <25>; - status = "disabled"; - }; - - ohci@e2100000 { - compatible = "st,spear600-ohci", "usb-ohci"; - reg = <0xe2100000 0x1000>; - interrupts = <27>; - status = "disabled"; - }; - - apb { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0xd0000000 0xd0000000 0x30000000>; - - gpio0: gpio@fc980000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0xfc980000 0x1000>; - interrupts = <11>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - status = "disabled"; - }; - - i2c0: i2c@d0180000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xd0180000 0x1000>; - interrupts = <21>; - status = "disabled"; - }; - - rtc@fc900000 { - compatible = "st,spear-rtc"; - reg = <0xfc900000 0x1000>; - interrupts = <10>; - status = "disabled"; - }; - - serial@d0000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xd0000000 0x1000>; - interrupts = <19>; - status = "disabled"; - }; - - wdt@fc880000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0xfc880000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/spear600-evb.dts b/trunk/arch/arm/boot/dts/spear600-evb.dts index 790a7a8a5ccd..636292e18c90 100644 --- a/trunk/arch/arm/boot/dts/spear600-evb.dts +++ b/trunk/arch/arm/boot/dts/spear600-evb.dts @@ -24,10 +24,6 @@ }; ahb { - dma@fc400000 { - status = "okay"; - }; - gmac: ethernet@e0800000 { phy-mode = "gmii"; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/spear600.dtsi b/trunk/arch/arm/boot/dts/spear600.dtsi index d777e3a6f178..ebe0885a2b98 100644 --- a/trunk/arch/arm/boot/dts/spear600.dtsi +++ b/trunk/arch/arm/boot/dts/spear600.dtsi @@ -45,14 +45,6 @@ #interrupt-cells = <1>; }; - dma@fc400000 { - compatible = "arm,pl080", "arm,primecell"; - reg = <0xfc400000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <10>; - status = "disabled"; - }; - gmac: ethernet@e0800000 { compatible = "st,spear600-gmac"; reg = <0xe0800000 0x8000>; diff --git a/trunk/arch/arm/boot/dts/twl4030.dtsi b/trunk/arch/arm/boot/dts/twl4030.dtsi deleted file mode 100644 index a94654c9eb8d..000000000000 --- a/trunk/arch/arm/boot/dts/twl4030.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - */ -&twl { - compatible = "ti,twl4030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - vdac: regulator@0 { - compatible = "ti,twl4030-vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vpll2: regulator@1 { - compatible = "ti,twl4030-vpll2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vmmc1: regulator@2 { - compatible = "ti,twl4030-vmmc1"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <3150000>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/twl6030.dtsi b/trunk/arch/arm/boot/dts/twl6030.dtsi deleted file mode 100644 index 3b2f3510d7eb..000000000000 --- a/trunk/arch/arm/boot/dts/twl6030.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* - * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf - */ -&twl { - compatible = "ti,twl6030"; - interrupt-controller; - #interrupt-cells = <1>; - - rtc { - compatible = "ti,twl4030-rtc"; - interrupts = <11>; - }; - - vaux1: regulator@0 { - compatible = "ti,twl6030-vaux1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vaux2: regulator@1 { - compatible = "ti,twl6030-vaux2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - }; - - vaux3: regulator@2 { - compatible = "ti,twl6030-vaux3"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - }; - - vmmc: regulator@3 { - compatible = "ti,twl6030-vmmc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - }; - - vpp: regulator@4 { - compatible = "ti,twl6030-vpp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2500000>; - }; - - vusim: regulator@5 { - compatible = "ti,twl6030-vusim"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2900000>; - }; - - vdac: regulator@6 { - compatible = "ti,twl6030-vdac"; - }; - - vana: regulator@7 { - compatible = "ti,twl6030-vana"; - }; - - vcxio: regulator@8 { - compatible = "ti,twl6030-vcxio"; - }; - - vusb: regulator@9 { - compatible = "ti,twl6030-vusb"; - }; - - v1v8: regulator@10 { - compatible = "ti,twl6030-v1v8"; - }; - - v2v1: regulator@11 { - compatible = "ti,twl6030-v2v1"; - }; - - clk32kg: regulator@12 { - compatible = "ti,twl6030-clk32kg"; - }; -}; diff --git a/trunk/arch/arm/configs/spear3xx_defconfig b/trunk/arch/arm/configs/spear3xx_defconfig index 7ed42912d69a..fea7e1f026a3 100644 --- a/trunk/arch/arm/configs/spear3xx_defconfig +++ b/trunk/arch/arm/configs/spear3xx_defconfig @@ -2,67 +2,33 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR300=y -CONFIG_MACH_SPEAR310=y -CONFIG_MACH_SPEAR320=y +CONFIG_BOARD_SPEAR300_EVB=y +CONFIG_BOARD_SPEAR310_EVB=y +CONFIG_BOARD_SPEAR320_EVB=y CONFIG_BINFMT_MISC=y -CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=y -# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_SPEAR=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 -CONFIG_I2C=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y # CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SPEAR=y -CONFIG_RTC_CLASS=y -CONFIG_DMADEVICES=y -CONFIG_AMBA_PL08X=y -CONFIG_DMATEST=m +# CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -73,6 +39,8 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -80,4 +48,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/configs/spear6xx_defconfig b/trunk/arch/arm/configs/spear6xx_defconfig index cf94bc73a0e0..cef2e836afd2 100644 --- a/trunk/arch/arm/configs/spear6xx_defconfig +++ b/trunk/arch/arm/configs/spear6xx_defconfig @@ -2,58 +2,29 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y -CONFIG_BOARD_SPEAR600_DT=y +CONFIG_BOARD_SPEAR600_EVB=y CONFIG_BINFMT_MISC=y -CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -CONFIG_STMMAC_ETH=y -# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 -CONFIG_I2C=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_DMADEVICES=y -CONFIG_AMBA_PL08X=y -CONFIG_DMATEST=m +# CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -64,6 +35,8 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -71,4 +44,6 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y +# CONFIG_CRC32 is not set diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index 7302ba7ff1b9..098d183a0086 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -94,6 +95,22 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 +static struct twl4030_platform_data beagle_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, +}; + +static void __init omap3_i2c_init(void) +{ + omap3_pmic_init("twl4030", &beagle_twldata); +} + +static void __init omap3_init(void) +{ + omap3_i2c_init(); + omap_generic_init(); +} + static const char *omap3_boards_compat[] __initdata = { "ti,omap3", NULL, @@ -105,7 +122,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_early = omap3430_init_early, .init_irq = omap_init_irq, .handle_irq = omap3_intc_handle_irq, - .init_machine = omap_generic_init, + .init_machine = omap3_init, .timer = &omap3_timer, .dt_compat = omap3_boards_compat, .restart = omap_prcm_restart, @@ -113,6 +130,22 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 +static struct twl4030_platform_data sdp4430_twldata = { + .irq_base = TWL6030_IRQ_BASE, + .irq_end = TWL6030_IRQ_END, +}; + +static void __init omap4_i2c_init(void) +{ + omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0); +} + +static void __init omap4_init(void) +{ + omap4_i2c_init(); + omap_generic_init(); +} + static const char *omap4_boards_compat[] __initdata = { "ti,omap4", NULL, @@ -124,7 +157,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .init_early = omap4430_init_early, .init_irq = omap_init_irq, .handle_irq = gic_handle_irq, - .init_machine = omap_generic_init, + .init_machine = omap4_init, .timer = &omap4_timer, .dt_compat = omap4_boards_compat, .restart = omap_prcm_restart, diff --git a/trunk/arch/arm/mach-omap2/devices.c b/trunk/arch/arm/mach-omap2/devices.c index 98cab3a204b9..e4336035c0ea 100644 --- a/trunk/arch/arm/mach-omap2/devices.c +++ b/trunk/arch/arm/mach-omap2/devices.c @@ -705,9 +705,7 @@ static int __init omap2_init_devices(void) omap_init_dmic(); omap_init_camera(); omap_init_mbox(); - /* If dtb is there, the devices will be created dynamically */ - if (!of_have_populated_dt()) - omap_init_mcspi(); + omap_init_mcspi(); omap_init_pmu(); omap_hdq_init(); omap_init_sti(); diff --git a/trunk/arch/arm/mach-omap2/gpio.c b/trunk/arch/arm/mach-omap2/gpio.c index 18f9c7bd7200..2f994e5194e8 100644 --- a/trunk/arch/arm/mach-omap2/gpio.c +++ b/trunk/arch/arm/mach-omap2/gpio.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -147,10 +146,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) */ static int __init omap2_gpio_init(void) { - /* If dtb is there, the devices will be created dynamically */ - if (of_have_populated_dt()) - return -ENODEV; - - return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL); + return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, + NULL); } postcore_initcall(omap2_gpio_init); diff --git a/trunk/arch/arm/mach-shmobile/include/mach/common.h b/trunk/arch/arm/mach-shmobile/include/mach/common.h index cc1d73514ffa..83ad3fe0a75f 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/common.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/common.h @@ -3,8 +3,6 @@ extern void shmobile_earlytimer_init(void); extern struct sys_timer shmobile_timer; -extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, - unsigned int mult, unsigned int div); struct twd_local_timer; void shmobile_twd_init(struct twd_local_timer *twd_local_timer); extern void shmobile_setup_console(void); diff --git a/trunk/arch/arm/mach-shmobile/include/mach/intc.h b/trunk/arch/arm/mach-shmobile/include/mach/intc.h index a5603c76cfe0..8b22258c8caa 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/intc.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/intc.h @@ -142,50 +142,6 @@ static struct intc_desc p ## _desc __initdata = { \ p ## _sense_registers, p ## _ack_registers) \ } -#define INTC_IRQ_PINS_16H(p, base, vect, str) \ - \ -static struct resource p ## _resources[] __initdata = { \ - [0] = { \ - .start = base, \ - .end = base + 0x64, \ - .flags = IORESOURCE_MEM, \ - }, \ -}; \ - \ -enum { \ - p ## _UNUSED = 0, \ - INTC_IRQ_PINS_ENUM_16H(p), \ -}; \ - \ -static struct intc_vect p ## _vectors[] __initdata = { \ - INTC_IRQ_PINS_VECT_16H(p, vect), \ -}; \ - \ -static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ - INTC_IRQ_PINS_MASK_16H(p, base), \ -}; \ - \ -static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ - INTC_IRQ_PINS_PRIO_16H(p, base), \ -}; \ - \ -static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ - INTC_IRQ_PINS_SENSE_16H(p, base), \ -}; \ - \ -static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ - INTC_IRQ_PINS_ACK_16H(p, base), \ -}; \ - \ -static struct intc_desc p ## _desc __initdata = { \ - .name = str, \ - .resource = p ## _resources, \ - .num_resources = ARRAY_SIZE(p ## _resources), \ - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ - p ## _mask_registers, p ## _prio_registers, \ - p ## _sense_registers, p ## _ack_registers) \ -} - #define INTC_IRQ_PINS_32(p, base, vect, str) \ \ static struct resource p ## _resources[] __initdata = { \ diff --git a/trunk/arch/arm/mach-shmobile/include/mach/irqs.h b/trunk/arch/arm/mach-shmobile/include/mach/irqs.h index 06a5da3c3050..4e686cc201fc 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/irqs.h @@ -7,7 +7,7 @@ #define gic_spi(nr) ((nr) + 32) /* INTCS */ -#define INTCS_VECT_BASE 0x3400 +#define INTCS_VECT_BASE 0x2200 #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) diff --git a/trunk/arch/arm/mach-shmobile/intc-sh7372.c b/trunk/arch/arm/mach-shmobile/intc-sh7372.c index 2587a22842f2..6447e0af52d4 100644 --- a/trunk/arch/arm/mach-shmobile/intc-sh7372.c +++ b/trunk/arch/arm/mach-shmobile/intc-sh7372.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -306,16 +305,14 @@ static DECLARE_INTC_DESC(intca_desc, "sh7372-intca", intca_mask_registers, intca_prio_registers, NULL); -INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000, - INTC_VECT, "sh7372-intca-irq-lo"); - -INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000, - INTC_VECT, "sh7372-intca-irq-hi"); - +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTC_VECT, "sh7372-intca-irq-pins"); enum { UNUSED_INTCS = 0, ENABLED_INTCS, + INTCS, + /* interrupt sources INTCS */ /* IRQ0S - IRQ31S */ @@ -429,6 +426,8 @@ static struct intc_vect intcs_vectors[] = { INTCS_VECT(CPORTS2R, 0x1a20), /* CEC */ INTCS_VECT(JPU6E, 0x1a80), + + INTC_VECT(INTCS, 0xf80), }; static struct intc_group intcs_groups[] __initdata = { @@ -491,6 +490,9 @@ static struct intc_mask_reg intcs_mask_registers[] = { { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ { MFIS2_INTCS, CPORTS2R, 0, 0, JPU6E, 0, 0, 0 } }, + { 0xffd20104, 0, 16, /* INTAMASK */ + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } }, }; /* Priority is needed for INTCA to receive the INTCS interrupt */ @@ -555,30 +557,18 @@ static void __iomem *intcs_ffd5; void __init sh7372_init_irq(void) { void __iomem *intevtsa; - int n; intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); intevtsa = intcs_ffd2 + 0x100; intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_lo_desc); - register_intc_controller(&intca_irq_pins_hi_desc); + register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); - /* setup dummy cascade chip for INTCS */ - n = evt2irq(0xf80); - irq_alloc_desc_at(n, numa_node_id()); - irq_set_chip_and_handler_name(n, &dummy_irq_chip, - handle_level_irq, "level"); - set_irq_flags(n, IRQF_VALID); /* yuck */ - /* demux using INTEVTSA */ - irq_set_handler_data(n, (void *)intevtsa); - irq_set_chained_handler(n, intcs_demux); - - /* unmask INTCS in INTAMASK */ - iowrite16(0, intcs_ffd2 + 0x104); + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } static unsigned short ffd2[0x200]; diff --git a/trunk/arch/arm/mach-shmobile/setup-sh7372.c b/trunk/arch/arm/mach-shmobile/setup-sh7372.c index 4c7fece5ef92..2fe8f83ca124 100644 --- a/trunk/arch/arm/mach-shmobile/setup-sh7372.c +++ b/trunk/arch/arm/mach-shmobile/setup-sh7372.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -1093,50 +1092,3 @@ void __init sh7372_add_early_devices(void) /* override timer setup with soc-specific code */ shmobile_timer.init = sh7372_earlytimer_init; } - -#ifdef CONFIG_USE_OF - -void __init sh7372_add_early_devices_dt(void) -{ - shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */ - - early_platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); -} - -static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = { - { } -}; - -void __init sh7372_add_standard_devices_dt(void) -{ - /* clocks are setup late during boot in the case of DT */ - sh7372_clock_init(); - - platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - of_platform_populate(NULL, of_default_bus_match_table, - sh7372_auxdata_lookup, NULL); -} - -static const char *sh7372_boards_compat_dt[] __initdata = { - "renesas,sh7372", - NULL, -}; - -DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") - .map_io = sh7372_map_io, - .init_early = sh7372_add_early_devices_dt, - .nr_irqs = NR_IRQS_LEGACY, - .init_irq = sh7372_init_irq, - .handle_irq = shmobile_handle_irq_intc, - .init_machine = sh7372_add_standard_devices_dt, - .timer = &shmobile_timer, - .dt_compat = sh7372_boards_compat_dt, -MACHINE_END - -#endif /* CONFIG_USE_OF */ diff --git a/trunk/arch/arm/mach-shmobile/timer.c b/trunk/arch/arm/mach-shmobile/timer.c index 599e0081a533..2fba5f3d1c8a 100644 --- a/trunk/arch/arm/mach-shmobile/timer.c +++ b/trunk/arch/arm/mach-shmobile/timer.c @@ -19,26 +19,9 @@ * */ #include -#include #include #include -void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, - unsigned int mult, unsigned int div) -{ - /* calculate a worst-case loops-per-jiffy value - * based on maximum cpu core mhz setting and the - * __delay() implementation in arch/arm/lib/delay.S - * - * this will result in a longer delay than expected - * when the cpu core runs on lower frequencies. - */ - - unsigned int value = (1000000 * mult) / (HZ * div); - - lpj_fine = max_cpu_core_mhz * value; -} - static void __init shmobile_late_time_init(void) { /* diff --git a/trunk/arch/arm/mach-spear3xx/Kconfig b/trunk/arch/arm/mach-spear3xx/Kconfig index d9fe11cb6f16..2cee6b0de371 100644 --- a/trunk/arch/arm/mach-spear3xx/Kconfig +++ b/trunk/arch/arm/mach-spear3xx/Kconfig @@ -5,19 +5,39 @@ if ARCH_SPEAR3XX menu "SPEAr3xx Implementations" +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + select MACH_SPEAR300 + help + Supports ST SPEAr300 Evaluation Board + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + select MACH_SPEAR310 + help + Supports ST SPEAr310 Evaluation Board + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + select MACH_SPEAR320 + help + Supports ST SPEAr320 Evaluation Board + +endmenu + config MACH_SPEAR300 - bool "SPEAr300 Machine support with Device Tree" + bool "SPEAr300" help - Supports ST SPEAr300 machine configured via the device-tree + Supports ST SPEAr300 Machine config MACH_SPEAR310 - bool "SPEAr310 Machine support with Device Tree" + bool "SPEAr310" help - Supports ST SPEAr310 machine configured via the device-tree + Supports ST SPEAr310 Machine config MACH_SPEAR320 - bool "SPEAr320 Machine support with Device Tree" + bool "SPEAr320" help - Supports ST SPEAr320 machine configured via the device-tree -endmenu + Supports ST SPEAr320 Machine + endif #ARCH_SPEAR3XX diff --git a/trunk/arch/arm/mach-spear3xx/Makefile b/trunk/arch/arm/mach-spear3xx/Makefile index 17b5d83cf2d5..b24862489704 100644 --- a/trunk/arch/arm/mach-spear3xx/Makefile +++ b/trunk/arch/arm/mach-spear3xx/Makefile @@ -3,13 +3,24 @@ # # common files -obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o +obj-y += spear3xx.o clock.o # spear300 specific files obj-$(CONFIG_MACH_SPEAR300) += spear300.o +# spear300 boards files +obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o + + # spear310 specific files obj-$(CONFIG_MACH_SPEAR310) += spear310.o +# spear310 boards files +obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o + + # spear320 specific files obj-$(CONFIG_MACH_SPEAR320) += spear320.o + +# spear320 boards files +obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o diff --git a/trunk/arch/arm/mach-spear3xx/Makefile.boot b/trunk/arch/arm/mach-spear3xx/Makefile.boot index d93e2177e6ec..4674a4c221db 100644 --- a/trunk/arch/arm/mach-spear3xx/Makefile.boot +++ b/trunk/arch/arm/mach-spear3xx/Makefile.boot @@ -1,7 +1,3 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb -dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb -dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb diff --git a/trunk/arch/arm/mach-spear3xx/clock.c b/trunk/arch/arm/mach-spear3xx/clock.c index cd6c11099083..6c4841f55223 100644 --- a/trunk/arch/arm/mach-spear3xx/clock.c +++ b/trunk/arch/arm/mach-spear3xx/clock.c @@ -11,112 +11,12 @@ * warranty of any kind, whether express or implied. */ -#include #include #include #include -#include #include #include #include -#include - -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL1_MOD (MISC_BASE + 0x010) -#define PLL2_CTR (MISC_BASE + 0x014) -/* PLL_CTR register masks */ -#define PLL_ENABLE 2 -#define PLL_MODE_SHIFT 4 -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_NORMAL 0 -#define PLL_MODE_FRACTION 1 -#define PLL_MODE_DITH_DSB 2 -#define PLL_MODE_DITH_SSB 3 - -#define PLL2_FRQ (MISC_BASE + 0x018) -/* PLL FRQ register masks */ -#define PLL_DIV_N_SHIFT 0 -#define PLL_DIV_N_MASK 0xFF -#define PLL_DIV_P_SHIFT 8 -#define PLL_DIV_P_MASK 0x7 -#define PLL_NORM_FDBK_M_SHIFT 24 -#define PLL_NORM_FDBK_M_MASK 0xFF -#define PLL_DITH_FDBK_M_SHIFT 16 -#define PLL_DITH_FDBK_M_MASK 0xFFFF - -#define PLL2_MOD (MISC_BASE + 0x01C) -#define PLL_CLK_CFG (MISC_BASE + 0x020) -#define CORE_CLK_CFG (MISC_BASE + 0x024) -/* CORE CLK CFG register masks */ -#define PLL_HCLK_RATIO_SHIFT 10 -#define PLL_HCLK_RATIO_MASK 0x3 -#define HCLK_PCLK_RATIO_SHIFT 8 -#define HCLK_PCLK_RATIO_MASK 0x3 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) -/* PERIP_CLK_CFG register masks */ -#define UART_CLK_SHIFT 4 -#define UART_CLK_MASK 0x1 -#define FIRDA_CLK_SHIFT 5 -#define FIRDA_CLK_MASK 0x3 -#define GPT0_CLK_SHIFT 8 -#define GPT1_CLK_SHIFT 11 -#define GPT2_CLK_SHIFT 12 -#define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_VAL 0 -#define AUX_CLK_PLL1_VAL 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) -/* PERIP1_CLK_ENB register masks */ -#define UART_CLK_ENB 3 -#define SSP_CLK_ENB 5 -#define I2C_CLK_ENB 7 -#define JPEG_CLK_ENB 8 -#define FIRDA_CLK_ENB 10 -#define GPT1_CLK_ENB 11 -#define GPT2_CLK_ENB 12 -#define ADC_CLK_ENB 15 -#define RTC_CLK_ENB 17 -#define GPIO_CLK_ENB 18 -#define DMA_CLK_ENB 19 -#define SMI_CLK_ENB 21 -#define GMAC_CLK_ENB 23 -#define USBD_CLK_ENB 24 -#define USBH_CLK_ENB 25 -#define C3_CLK_ENB 31 - -#define RAS_CLK_ENB (MISC_BASE + 0x034) - -#define PRSC1_CLK_CFG (MISC_BASE + 0x044) -#define PRSC2_CLK_CFG (MISC_BASE + 0x048) -#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) -/* gpt synthesizer register masks */ -#define GPT_MSCALE_SHIFT 0 -#define GPT_MSCALE_MASK 0xFFF -#define GPT_NSCALE_SHIFT 12 -#define GPT_NSCALE_MASK 0xF - -#define AMEM_CLK_CFG (MISC_BASE + 0x050) -#define EXPI_CLK_CFG (MISC_BASE + 0x054) -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) -#define GMAC_CLK_SYNT (MISC_BASE + 0x068) -#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) -#define RAS2_CLK_SYNT (MISC_BASE + 0x070) -#define RAS3_CLK_SYNT (MISC_BASE + 0x074) -#define RAS4_CLK_SYNT (MISC_BASE + 0x078) -/* aux clk synthesiser register masks for irda to ras4 */ -#define AUX_SYNT_ENB 31 -#define AUX_EQ_SEL_SHIFT 30 -#define AUX_EQ_SEL_MASK 1 -#define AUX_EQ1_SEL 0 -#define AUX_EQ2_SEL 1 -#define AUX_XSCALE_SHIFT 16 -#define AUX_XSCALE_MASK 0xFFF -#define AUX_YSCALE_SHIFT 0 -#define AUX_YSCALE_MASK 0xFFF /* root clks */ /* 32 KHz oscillator clock */ @@ -511,21 +411,6 @@ static struct clk usbd_clk = { .recalc = &follow_parent, }; -/* clock derived from usbh clk */ -/* usbh0 clock */ -static struct clk usbh0_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &usbh_clk, - .recalc = &follow_parent, -}; - -/* usbh1 clock */ -static struct clk usbh1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &usbh_clk, - .recalc = &follow_parent, -}; - /* clock derived from ahb clk */ /* apb masks structure */ static struct bus_clk_masks apb_masks = { @@ -767,126 +652,109 @@ static struct clk pwm_clk = { /* array of all spear 3xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ - CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), - CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk), + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, /* clock derived from 32 KHz osc clk */ - CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk), + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 24 MHz osc clk */ - CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), - CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), - CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk), + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, /* clock derived from pll1 clk */ - CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), - CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), - CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), - CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), - CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), - CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk), - CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), - CLKDEV_INIT("d0000000.serial", NULL, &uart_clk), - CLKDEV_INIT("firda", NULL, &firda_clk), - CLKDEV_INIT("gpt0", NULL, &gpt0_clk), - CLKDEV_INIT("gpt1", NULL, &gpt1_clk), - CLKDEV_INIT("gpt2", NULL, &gpt2_clk), + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, + { .dev_id = "uart", .clk = &uart_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, /* clock derived from pll3 clk */ - CLKDEV_INIT("designware_udc", NULL, &usbd_clk), - CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk), - /* clock derived from usbh clk */ - CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), - CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh_clk", .clk = &usbh_clk}, /* clock derived from ahb clk */ - CLKDEV_INIT(NULL, "apb_clk", &apb_clk), - CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk), - CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), - CLKDEV_INIT("jpeg", NULL, &jpeg_clk), - CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk), - CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), - CLKDEV_INIT("c3", NULL, &c3_clk), + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "c3", .clk = &c3_clk}, /* clock derived from apb clk */ - CLKDEV_INIT("adc", NULL, &adc_clk), - CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk), - CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk), + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, + { .dev_id = "gpio", .clk = &gpio_clk}, }; /* array of all spear 300 clock lookups */ #ifdef CONFIG_MACH_SPEAR300 static struct clk_lookup spear300_clk_lookups[] = { - CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk), - CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk), - CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk), - CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "gpio1", .clk = &gpio1_clk}, + { .dev_id = "keyboard", .clk = &kbd_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, }; - -void __init spear300_clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++) - clk_register(&spear300_clk_lookups[i]); - - clk_init(); -} #endif /* array of all spear 310 clock lookups */ #ifdef CONFIG_MACH_SPEAR310 static struct clk_lookup spear310_clk_lookups[] = { - CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT(NULL, "emi", &emi_clk), - CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk), - CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk), - CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk), - CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk), - CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk), + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, + { .dev_id = "uart3", .clk = &uart3_clk}, + { .dev_id = "uart4", .clk = &uart4_clk}, + { .dev_id = "uart5", .clk = &uart5_clk}, }; - -void __init spear310_clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++) - clk_register(&spear310_clk_lookups[i]); - - clk_init(); -} #endif /* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 static struct clk_lookup spear320_clk_lookups[] = { - CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk), - CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk), - CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk), - CLKDEV_INIT(NULL, "emi", &emi_clk), - CLKDEV_INIT("pwm", NULL, &pwm_clk), - CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), - CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk), - CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk), - CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk), - CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk), - CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk), - CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk), -}; - -void __init spear320_clk_init(void) + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "pwm", .clk = &pwm_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, + { .dev_id = "c_can_platform.0", .clk = &can0_clk}, + { .dev_id = "c_can_platform.1", .clk = &can1_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, +}; +#endif + +void __init spear3xx_clk_init(void) { - int i; + int i, cnt; + struct clk_lookup *lookups; + + if (machine_is_spear300()) { + cnt = ARRAY_SIZE(spear300_clk_lookups); + lookups = spear300_clk_lookups; + } else if (machine_is_spear310()) { + cnt = ARRAY_SIZE(spear310_clk_lookups); + lookups = spear310_clk_lookups; + } else { + cnt = ARRAY_SIZE(spear320_clk_lookups); + lookups = spear320_clk_lookups; + } for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++) - clk_register(&spear320_clk_lookups[i]); + for (i = 0; i < cnt; i++) + clk_register(&lookups[i]); clk_init(); } -#endif diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h index e4f4d721cda2..14276e5a98d2 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h @@ -14,7 +14,6 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H -#include #include #include #include @@ -22,15 +21,26 @@ #include #include +/* spear3xx declarations */ +/* + * Each GPT has 2 timer channels + * Following GPT channels will be used as clock source and clockevent + */ +#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE +#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 + /* Add spear3xx family device structure declarations here */ +extern struct amba_device spear3xx_gpio_device; +extern struct amba_device spear3xx_uart_device; extern struct sys_timer spear3xx_timer; -extern struct pl022_ssp_controller pl022_plat_data; -extern struct pl08x_platform_data pl080_plat_data; /* Add spear3xx family function declarations here */ -void __init spear_setup_timer(resource_size_t base, int irq); +void __init spear3xx_clk_init(void); +void __init spear_setup_timer(void); void __init spear3xx_map_io(void); -void __init spear3xx_dt_init_irq(void); +void __init spear3xx_init_irq(void); +void __init spear3xx_init(void); void spear_restart(char, const char *); @@ -89,6 +99,9 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; /* spear300 declarations */ #ifdef CONFIG_MACH_SPEAR300 +/* Add spear300 machine device structure declarations here */ +extern struct amba_device spear300_gpio1_device; + /* pad mux modes */ extern struct pmx_mode spear300_nand_mode; extern struct pmx_mode spear300_nor_mode; @@ -120,13 +133,16 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; extern struct pmx_dev spear300_pmx_gpio1; -/* Add spear300 machine declarations here */ -void __init spear300_clk_init(void); +/* Add spear300 machine function declarations here */ +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR300 */ /* spear310 declarations */ #ifdef CONFIG_MACH_SPEAR310 +/* Add spear310 machine device structure declarations here */ + /* pad mux devices */ extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; extern struct pmx_dev spear310_pmx_emi_cs_2_3; @@ -137,13 +153,16 @@ extern struct pmx_dev spear310_pmx_fsmc; extern struct pmx_dev spear310_pmx_rs485_0_1; extern struct pmx_dev spear310_pmx_tdm0; -/* Add spear310 machine declarations here */ -void __init spear310_clk_init(void); +/* Add spear310 machine function declarations here */ +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR310 */ /* spear320 declarations */ #ifdef CONFIG_MACH_SPEAR320 +/* Add spear320 machine device structure declarations here */ + /* pad mux modes */ extern struct pmx_mode spear320_auto_net_smii_mode; extern struct pmx_mode spear320_auto_net_mii_mode; @@ -174,8 +193,9 @@ extern struct pmx_dev spear320_pmx_smii0; extern struct pmx_dev spear320_pmx_smii1; extern struct pmx_dev spear320_pmx_i2c1; -/* Add spear320 machine declarations here */ -void __init spear320_clk_init(void); +/* Add spear320 machine function declarations here */ +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR320 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h index 40a8c178f10d..4660c0d8ec0d 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -1 +1,23 @@ -/* empty */ +/* + * arch/arm/mach-spear3xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#include +#include + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __MACH_HARDWARE_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h b/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h index 319620a1afb4..6e265442808e 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -14,15 +14,141 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -/* FIXME: probe all these from DT */ +/* SPEAr3xx IRQ definitions */ +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 #define SPEAR3XX_IRQ_CPU_GPT1_1 2 +#define SPEAR3XX_IRQ_CPU_GPT1_2 3 +#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 +#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 +#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 +#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 +#define SPEAR3XX_IRQ_BASIC_DMA 8 +#define SPEAR3XX_IRQ_BASIC_SMI 9 +#define SPEAR3XX_IRQ_BASIC_RTC 10 +#define SPEAR3XX_IRQ_BASIC_GPIO 11 +#define SPEAR3XX_IRQ_BASIC_WDT 12 +#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 +#define SPEAR3XX_IRQ_SYS_ERROR 14 +#define SPEAR3XX_IRQ_WAKEUP_RCV 15 +#define SPEAR3XX_IRQ_JPEG 16 +#define SPEAR3XX_IRQ_IRDA 17 +#define SPEAR3XX_IRQ_ADC 18 +#define SPEAR3XX_IRQ_UART 19 +#define SPEAR3XX_IRQ_SSP 20 +#define SPEAR3XX_IRQ_I2C 21 +#define SPEAR3XX_IRQ_MAC_1 22 +#define SPEAR3XX_IRQ_MAC_2 23 +#define SPEAR3XX_IRQ_USB_DEV 24 +#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 +#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 +#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 +#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 #define SPEAR3XX_IRQ_GEN_RAS_1 28 #define SPEAR3XX_IRQ_GEN_RAS_2 29 #define SPEAR3XX_IRQ_GEN_RAS_3 30 +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 #define SPEAR3XX_IRQ_VIC_END 32 + #define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END -#define NR_IRQS 160 +/* SPEAr300 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM + +/* SPEAr310 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) + +/* SPEAr320 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) + +/* + * GPIO pins virtual irqs + * Use the lowest number for the GPIO virtual IRQs base on which subarchs + * we have compiled in + */ +#if defined(CONFIG_MACH_SPEAR310) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) +#elif defined(CONFIG_MACH_SPEAR320) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) +#else +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) +#endif + +#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_PLGPIO_COUNT 102 + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ + SPEAR3XX_PLGPIO_COUNT) +#else +#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) +#endif + +#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END +#define NR_IRQS SPEAR3XX_VIRQ_END #endif /* __MACH_IRQS_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h index e0ab72e61507..5bd8cd8d4852 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,7 +14,151 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H +#include + #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) + +#define SOC_CFG_CTR (MISC_BASE + 0x000) +#define DIAG_CFG_CTR (MISC_BASE + 0x004) +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ (MISC_BASE + 0x018) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG (MISC_BASE + 0x028) +/* PERIP_CLK_CFG register masks */ +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 11 +#define GPT2_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 + +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) +/* PERIP1_CLK_ENB register masks */ +#define UART_CLK_ENB 3 +#define SSP_CLK_ENB 5 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FIRDA_CLK_ENB 10 +#define GPT1_CLK_ENB 11 +#define GPT2_CLK_ENB 12 +#define ADC_CLK_ENB 15 +#define RTC_CLK_ENB 17 +#define GPIO_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH_CLK_ENB 25 +#define C3_CLK_ENB 31 + +#define SOC_CORE_ID (MISC_BASE + 0x030) +#define RAS_CLK_ENB (MISC_BASE + 0x034) +#define PERIP1_SOF_RST (MISC_BASE + 0x038) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID (MISC_BASE + 0x03C) +#define RAS_SOF_RST (MISC_BASE + 0x040) +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG (MISC_BASE + 0x07C) +#define ICM2_ARB_CFG (MISC_BASE + 0x080) +#define ICM3_ARB_CFG (MISC_BASE + 0x084) +#define ICM4_ARB_CFG (MISC_BASE + 0x088) +#define ICM5_ARB_CFG (MISC_BASE + 0x08C) +#define ICM6_ARB_CFG (MISC_BASE + 0x090) +#define ICM7_ARB_CFG (MISC_BASE + 0x094) +#define ICM8_ARB_CFG (MISC_BASE + 0x098) +#define ICM9_ARB_CFG (MISC_BASE + 0x09C) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) +#define USB2_PHY_CFG (MISC_BASE + 0x0A4) +#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) +#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) +#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) +#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) +#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) +#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) +#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) +#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) +#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) +#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) +#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) +#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) +#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) +#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) +#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) +#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) +#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) +#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) +#define BIST4_CFG_CTR (MISC_BASE + 0x100) +#define BIST5_CFG_CTR (MISC_BASE + 0x104) +#define BIST1_STS_RES (MISC_BASE + 0x108) +#define BIST2_STS_RES (MISC_BASE + 0x10C) +#define BIST3_STS_RES (MISC_BASE + 0x110) +#define BIST4_STS_RES (MISC_BASE + 0x114) +#define BIST5_STS_RES (MISC_BASE + 0x118) +#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h index 6d4dadc67633..63fd98356919 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h @@ -15,27 +15,60 @@ #define __MACH_SPEAR3XX_H #include +#include +#include +#include + +#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) + +#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) +#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) +#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) +#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) +#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) +#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) + +/* ICM2 - Application Subsystem */ +#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) +#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) + +/* ICM4 - High Speed Connection */ +#define SPEAR3XX_ICM4_BASE UL(0xE0000000) +#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) +#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) +#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) +#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) +#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) +#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) +#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) +#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) -#define SPEAR3XX_CPU_TMR_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) +#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) /* ICM3 - Basic Subsystem */ +#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) +#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) +#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) +#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) +#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) +#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) +#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h new file mode 100644 index 000000000000..3b6ea0729040 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -0,0 +1,54 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear300.h + * + * SPEAr300 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR300 + +#ifndef __MACH_SPEAR300_H +#define __MACH_SPEAR300_H + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE UL(0x50000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF + +#define SPEAR300_CLCD_BASE UL(0x60000000) +#define SPEAR300_SDHCI_BASE UL(0x70000000) +#define SPEAR300_NAND_0_BASE UL(0x80000000) +#define SPEAR300_NAND_1_BASE UL(0x84000000) +#define SPEAR300_NAND_2_BASE UL(0x88000000) +#define SPEAR300_NAND_3_BASE UL(0x8c000000) +#define SPEAR300_NOR_0_BASE UL(0x90000000) +#define SPEAR300_NOR_1_BASE UL(0x91000000) +#define SPEAR300_NOR_2_BASE UL(0x92000000) +#define SPEAR300_NOR_3_BASE UL(0x93000000) +#define SPEAR300_FSMC_BASE UL(0x94000000) +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) +#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) +#define SPEAR300_GPIO_BASE UL(0xA9000000) + +#endif /* __MACH_SPEAR300_H */ + +#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h new file mode 100644 index 000000000000..1567d0da725f --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -0,0 +1,58 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear310.h + * + * SPEAr310 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR310 + +#ifndef __MACH_SPEAR310_H +#define __MACH_SPEAR310_H + +#define SPEAR310_NAND_BASE UL(0x40000000) +#define SPEAR310_FSMC_BASE UL(0x44000000) +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_HDLC_BASE UL(0xB2800000) +#define SPEAR310_RS485_0_BASE UL(0xB3000000) +#define SPEAR310_RS485_1_BASE UL(0xB3800000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) + +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 + +#endif /* __MACH_SPEAR310_H */ + +#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h new file mode 100644 index 000000000000..8cfa83fa1296 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -0,0 +1,67 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear320.h + * + * SPEAr320 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR320 + +#ifndef __MACH_SPEAR320_H +#define __MACH_SPEAR320_H + +#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) +#define SPEAR320_FSMC_BASE UL(0x4C000000) +#define SPEAR320_NAND_BASE UL(0x50000000) +#define SPEAR320_I2S_BASE UL(0x60000000) +#define SPEAR320_SDHCI_BASE UL(0x70000000) +#define SPEAR320_CLCD_BASE UL(0x90000000) +#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) +#define SPEAR320_CAN0_BASE UL(0xA1000000) +#define SPEAR320_CAN1_BASE UL(0xA2000000) +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) +#define SPEAR320_I2C_BASE UL(0xA7000000) +#define SPEAR320_PWM_BASE UL(0xA8000000) +#define SPEAR320_SMII0_BASE UL(0xAA000000) +#define SPEAR320_SMII1_BASE UL(0xAB000000) +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) + +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 + +#endif /* __MACH_SPEAR320_H */ + +#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/trunk/arch/arm/mach-spear3xx/spear300.c b/trunk/arch/arm/mach-spear3xx/spear300.c index febcdd8d4e92..f7db66812abb 100644 --- a/trunk/arch/arm/mach-spear3xx/spear300.c +++ b/trunk/arch/arm/mach-spear3xx/spear300.c @@ -3,62 +3,21 @@ * * SPEAr300 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr300: " fmt - -#include -#include -#include -#include +#include +#include +#include +#include #include #include -#include - -/* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE UL(0x50000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR300_INT_ENB_MASK_REG 0x54 -#define SPEAR300_INT_STS_MASK_REG 0x58 -#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) -#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) -#define SPEAR300_I2S_IRQ_MASK (1 << 2) -#define SPEAR300_TDM_IRQ_MASK (1 << 3) -#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) -#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) -#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) -#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) -#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) - -#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF - -#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) - - -/* SPEAr300 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) -#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) -#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) -#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) -#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) -#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) -#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) -#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) -#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM +#include /* pad multiplexing support */ /* muxing registers */ @@ -464,275 +423,45 @@ static struct spear_shirq shirq_ras1 = { }, }; -/* padmux devices to enable */ -static struct pmx_dev *spear300_evb_pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp_cs, - &spear3xx_pmx_ssp, - &spear3xx_pmx_mii, - &spear3xx_pmx_uart0, - - /* spear300 specific devices */ - &spear300_pmx_fsmc_2_chips, - &spear300_pmx_clcd, - &spear300_pmx_telecom_sdhci_4bit, - &spear300_pmx_gpio1, +/* Add spear300 specific devices here */ +/* arm gpio1 device registration */ +static struct pl061_platform_data gpio1_plat_data = { + .gpio_base = 8, + .irq_base = SPEAR300_GPIO1_INT_BASE, }; -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear300_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, -}; +AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, + {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); -/* Add SPEAr300 auxdata to pass platform data */ -static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; - -static void __init spear300_dt_init(void) +/* spear300 routines */ +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { - int ret = -EINVAL; - - pl080_plat_data.slave_channels = spear300_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); + int ret = 0; - of_platform_populate(NULL, of_default_bus_match_table, - spear300_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); if (shirq_ras1.regs.base) { ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ\n"); + printk(KERN_ERR "Error registering Shared IRQ\n"); } - if (of_machine_is_compatible("st,spear300-evb")) { - /* pmx initialization */ - pmx_driver.mode = &spear300_photo_frame_mode; - pmx_driver.devs = spear300_evb_pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs); - - pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); - if (pmx_driver.base) { - ret = pmx_register(&pmx_driver); - if (ret) - pr_err("padmux: registration failed. err no: %d\n", - ret); - /* Free Mapping, device selection already done */ - iounmap(pmx_driver.base); - } + /* pmx initialization */ + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); + if (pmx_driver.base) { + ret = pmx_register(&pmx_driver); if (ret) - pr_err("Initialization Failed"); + printk(KERN_ERR "padmux: registration failed. err no" + ": %d\n", ret); + /* Free Mapping, device selection already done */ + iounmap(pmx_driver.base); } } - -static const char * const spear300_dt_board_compat[] = { - "st,spear300", - "st,spear300-evb", - NULL, -}; - -static void __init spear300_map_io(void) -{ - spear3xx_map_io(); - spear300_clk_init(); -} - -DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") - .map_io = spear300_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear300_dt_init, - .restart = spear_restart, - .dt_compat = spear300_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear300_evb.c b/trunk/arch/arm/mach-spear3xx/spear300_evb.c new file mode 100644 index 000000000000..3462ab9d6122 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear300_evb.c @@ -0,0 +1,75 @@ +/* + * arch/arm/mach-spear3xx/spear300_evb.c + * + * SPEAr300 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp_cs, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear300 specific devices */ + &spear300_pmx_fsmc_2_chips, + &spear300_pmx_clcd, + &spear300_pmx_telecom_sdhci_4bit, + &spear300_pmx_gpio1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear300 specific devices */ + &spear300_gpio1_device, +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear300 specific devices */ +}; + +static void __init spear300_evb_init(void) +{ + unsigned int i; + + /* call spear300 machine init function */ + spear300_init(&spear300_photo_frame_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear300_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear310.c b/trunk/arch/arm/mach-spear3xx/spear310.c index b26e41566b50..febaa6fcfb6a 100644 --- a/trunk/arch/arm/mach-spear3xx/spear310.c +++ b/trunk/arch/arm/mach-spear3xx/spear310.c @@ -3,84 +3,19 @@ * * SPEAr310 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr310: " fmt - -#include -#include -#include -#include -#include +#include +#include #include #include -#include - -#define SPEAR310_UART1_BASE UL(0xB2000000) -#define SPEAR310_UART2_BASE UL(0xB2080000) -#define SPEAR310_UART3_BASE UL(0xB2100000) -#define SPEAR310_UART4_BASE UL(0xB2180000) -#define SPEAR310_UART5_BASE UL(0xB2200000) -#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR310_INT_STS_MASK_REG 0x04 -#define SPEAR310_SMII0_IRQ_MASK (1 << 0) -#define SPEAR310_SMII1_IRQ_MASK (1 << 1) -#define SPEAR310_SMII2_IRQ_MASK (1 << 2) -#define SPEAR310_SMII3_IRQ_MASK (1 << 3) -#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define SPEAR310_UART1_IRQ_MASK (1 << 8) -#define SPEAR310_UART2_IRQ_MASK (1 << 9) -#define SPEAR310_UART3_IRQ_MASK (1 << 10) -#define SPEAR310_UART4_IRQ_MASK (1 << 11) -#define SPEAR310_UART5_IRQ_MASK (1 << 12) -#define SPEAR310_EMI_IRQ_MASK (1 << 13) -#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) -#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) -#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) - -#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF -#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 -#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 -#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 - -/* SPEAr310 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) -#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) -#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) -#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) -#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) -#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) -#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) -#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) -#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) -#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) -#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) - +#include /* pad multiplexing support */ /* muxing registers */ @@ -320,271 +255,17 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* padmux devices to enable */ -static struct pmx_dev *spear310_evb_pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp, - &spear3xx_pmx_gpio_pin0, - &spear3xx_pmx_gpio_pin1, - &spear3xx_pmx_gpio_pin2, - &spear3xx_pmx_gpio_pin3, - &spear3xx_pmx_gpio_pin4, - &spear3xx_pmx_gpio_pin5, - &spear3xx_pmx_uart0, - - /* spear310 specific devices */ - &spear310_pmx_emi_cs_0_1_4_5, - &spear310_pmx_emi_cs_2_3, - &spear310_pmx_uart1, - &spear310_pmx_uart2, - &spear310_pmx_uart3_4_5, - &spear310_pmx_fsmc, - &spear310_pmx_rs485_0_1, - &spear310_pmx_tdm0, -}; +/* Add spear310 specific devices here */ -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear310_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart3_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart4_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart5_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, -}; - -/* uart devices plat data */ -static struct amba_pl011_data spear310_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart3_tx", - .dma_rx_param = "uart3_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart4_tx", - .dma_rx_param = "uart4_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart5_tx", - .dma_rx_param = "uart5_rx", - }, -}; - -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, - &spear310_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, - &spear310_uart_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, - &spear310_uart_data[2]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, - &spear310_uart_data[3]), - OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, - &spear310_uart_data[4]), - {} -}; - -static void __init spear310_dt_init(void) +/* spear310 routines */ +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; - pl080_plat_data.slave_channels = spear310_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear310_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); @@ -593,59 +274,35 @@ static void __init spear310_dt_init(void) shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ 1\n"); + printk(KERN_ERR "Error registering Shared IRQ 1\n"); /* shirq 2 */ shirq_ras2.regs.base = base; ret = spear_shirq_register(&shirq_ras2); if (ret) - pr_err("Error registering Shared IRQ 2\n"); + printk(KERN_ERR "Error registering Shared IRQ 2\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - pr_err("Error registering Shared IRQ 3\n"); + printk(KERN_ERR "Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - pr_err("Error registering Shared IRQ 4\n"); - } - - if (of_machine_is_compatible("st,spear310-evb")) { - /* pmx initialization */ - pmx_driver.base = base; - pmx_driver.mode = NULL; - pmx_driver.devs = spear310_evb_pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs); - - ret = pmx_register(&pmx_driver); - if (ret) - pr_err("padmux: registration failed. err no: %d\n", - ret); + printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -static const char * const spear310_dt_board_compat[] = { - "st,spear310", - "st,spear310-evb", - NULL, -}; + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; -static void __init spear310_map_io(void) -{ - spear3xx_map_io(); - spear310_clk_init(); + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registration failed. err no: %d\n", + ret); } - -DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") - .map_io = spear310_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear310_dt_init, - .restart = spear_restart, - .dt_compat = spear310_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear310_evb.c b/trunk/arch/arm/mach-spear3xx/spear310_evb.c new file mode 100644 index 000000000000..f92c4993f65a --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear310_evb.c @@ -0,0 +1,81 @@ +/* + * arch/arm/mach-spear3xx/spear310_evb.c + * + * SPEAr310 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_gpio_pin0, + &spear3xx_pmx_gpio_pin1, + &spear3xx_pmx_gpio_pin2, + &spear3xx_pmx_gpio_pin3, + &spear3xx_pmx_gpio_pin4, + &spear3xx_pmx_gpio_pin5, + &spear3xx_pmx_uart0, + + /* spear310 specific devices */ + &spear310_pmx_emi_cs_0_1_4_5, + &spear310_pmx_emi_cs_2_3, + &spear310_pmx_uart1, + &spear310_pmx_uart2, + &spear310_pmx_uart3_4_5, + &spear310_pmx_fsmc, + &spear310_pmx_rs485_0_1, + &spear310_pmx_tdm0, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear310 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear310 specific devices */ +}; + +static void __init spear310_evb_init(void) +{ + unsigned int i; + + /* call spear310 machine init function */ + spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear310_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear320.c b/trunk/arch/arm/mach-spear3xx/spear320.c index 2f5979b0c169..deaaf199612c 100644 --- a/trunk/arch/arm/mach-spear3xx/spear320.c +++ b/trunk/arch/arm/mach-spear3xx/spear320.c @@ -3,85 +3,19 @@ * * SPEAr320 machine source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr320: " fmt - -#include -#include -#include -#include -#include -#include +#include +#include #include #include -#include - -#define SPEAR320_UART1_BASE UL(0xA3000000) -#define SPEAR320_UART2_BASE UL(0xA4000000) -#define SPEAR320_SSP0_BASE UL(0xA5000000) -#define SPEAR320_SSP1_BASE UL(0xA6000000) -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR320_INT_STS_MASK_REG 0x04 -#define SPEAR320_INT_CLR_MASK_REG 0x04 -#define SPEAR320_INT_ENB_MASK_REG 0x08 -#define SPEAR320_GPIO_IRQ_MASK (1 << 0) -#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) -#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) -#define SPEAR320_EMI_IRQ_MASK (1 << 7) -#define SPEAR320_CLCD_IRQ_MASK (1 << 8) -#define SPEAR320_SPP_IRQ_MASK (1 << 9) -#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) -#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) -#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) -#define SPEAR320_UART1_IRQ_MASK (1 << 13) -#define SPEAR320_UART2_IRQ_MASK (1 << 14) -#define SPEAR320_SSP1_IRQ_MASK (1 << 15) -#define SPEAR320_SSP2_IRQ_MASK (1 << 16) -#define SPEAR320_SMII0_IRQ_MASK (1 << 17) -#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) -#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define SPEAR320_I2C1_IRQ_MASK (1 << 21) - -#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 -#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 -#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 - -/* SPEAr320 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) -#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) -#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) -#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) -#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) -#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) -#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) -#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) -#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) -#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) -#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) +#include /* pad multiplexing support */ /* muxing registers */ @@ -574,271 +508,17 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* padmux devices to enable */ -static struct pmx_dev *spear320_evb_pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp, - &spear3xx_pmx_mii, - &spear3xx_pmx_uart0, - - /* spear320 specific devices */ - &spear320_pmx_fsmc, - &spear320_pmx_sdhci, - &spear320_pmx_i2s, - &spear320_pmx_uart1, - &spear320_pmx_uart2, - &spear320_pmx_can, - &spear320_pmx_pwm0, - &spear320_pmx_pwm1, - &spear320_pmx_pwm2, - &spear320_pmx_mii1, -}; - -/* DMAC platform data's slave info */ -struct pl08x_channel_data spear320_dma_info[] = { - { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c0_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "uart2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c1_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2c2_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "i2s_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "rs485_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, -}; - -static struct pl022_ssp_controller spear320_ssp_data[] = { - { - .bus_id = 1, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp1_tx", - .dma_rx_param = "ssp1_rx", - .num_chipselect = 2, - }, { - .bus_id = 2, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp2_tx", - .dma_rx_param = "ssp2_rx", - .num_chipselect = 2, - } -}; - -static struct amba_pl011_data spear320_uart_data[] = { - { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart1_tx", - .dma_rx_param = "uart1_rx", - }, { - .dma_filter = pl08x_filter_id, - .dma_tx_param = "uart2_tx", - .dma_rx_param = "uart2_rx", - }, -}; +/* Add spear320 specific devices here */ -/* Add SPEAr310 auxdata to pass platform data */ -static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, - &pl022_plat_data), - OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, - &spear320_ssp_data[0]), - OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, - &spear320_ssp_data[1]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, - &spear320_uart_data[0]), - OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, - &spear320_uart_data[1]), - {} -}; - -static void __init spear320_dt_init(void) +/* spear320 routines */ +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; - pl080_plat_data.slave_channels = spear320_dma_info; - pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); - - of_platform_populate(NULL, of_default_bus_match_table, - spear320_auxdata_lookup, NULL); + /* call spear3xx family common init function */ + spear3xx_init(); /* shared irq registration */ base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); @@ -847,53 +527,29 @@ static void __init spear320_dt_init(void) shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - pr_err("Error registering Shared IRQ 1\n"); + printk(KERN_ERR "Error registering Shared IRQ 1\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - pr_err("Error registering Shared IRQ 3\n"); + printk(KERN_ERR "Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - pr_err("Error registering Shared IRQ 4\n"); - } - - if (of_machine_is_compatible("st,spear320-evb")) { - /* pmx initialization */ - pmx_driver.base = base; - pmx_driver.mode = &spear320_auto_net_mii_mode; - pmx_driver.devs = spear320_evb_pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs); - - ret = pmx_register(&pmx_driver); - if (ret) - pr_err("padmux: registration failed. err no: %d\n", - ret); + printk(KERN_ERR "Error registering Shared IRQ 4\n"); } -} -static const char * const spear320_dt_board_compat[] = { - "st,spear320", - "st,spear320-evb", - NULL, -}; + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; -static void __init spear320_map_io(void) -{ - spear3xx_map_io(); - spear320_clk_init(); + ret = pmx_register(&pmx_driver); + if (ret) + printk(KERN_ERR "padmux: registration failed. err no: %d\n", + ret); } - -DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") - .map_io = spear320_map_io, - .init_irq = spear3xx_dt_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear320_dt_init, - .restart = spear_restart, - .dt_compat = spear320_dt_board_compat, -MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear320_evb.c b/trunk/arch/arm/mach-spear3xx/spear320_evb.c new file mode 100644 index 000000000000..105334ab7021 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/spear320_evb.c @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-spear3xx/spear320_evb.c + * + * SPEAr320 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* padmux devices to enable */ +static struct pmx_dev *pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear320 specific devices */ + &spear320_pmx_fsmc, + &spear320_pmx_sdhci, + &spear320_pmx_i2s, + &spear320_pmx_uart1, + &spear320_pmx_uart2, + &spear320_pmx_can, + &spear320_pmx_pwm0, + &spear320_pmx_pwm1, + &spear320_pmx_pwm2, + &spear320_pmx_mii1, +}; + +static struct amba_device *amba_devs[] __initdata = { + /* spear3xx specific devices */ + &spear3xx_gpio_device, + &spear3xx_uart_device, + + /* spear320 specific devices */ +}; + +static struct platform_device *plat_devs[] __initdata = { + /* spear3xx specific devices */ + + /* spear320 specific devices */ +}; + +static void __init spear320_evb_init(void) +{ + unsigned int i; + + /* call spear320 machine init function */ + spear320_init(&spear320_auto_net_mii_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") + .atag_offset = 0x100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear320_evb_init, + .restart = spear_restart, +MACHINE_END diff --git a/trunk/arch/arm/mach-spear3xx/spear3xx.c b/trunk/arch/arm/mach-spear3xx/spear3xx.c index bbb11efa6056..b1733c37f209 100644 --- a/trunk/arch/arm/mach-spear3xx/spear3xx.c +++ b/trunk/arch/arm/mach-spear3xx/spear3xx.c @@ -3,25 +3,83 @@ * * SPEAr3XX machines common source file * - * Copyright (C) 2009-2012 ST Microelectronics - * Viresh Kumar + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#define pr_fmt(fmt) "SPEAr3xx: " fmt - -#include -#include -#include +#include +#include +#include #include -#include #include -#include +#include +#include #include -#include +#include + +/* Add spear3xx machines common devices here */ +/* gpio device registration */ +static struct pl061_platform_data gpio_plat_data = { + .gpio_base = 0, + .irq_base = SPEAR3XX_GPIO_INT_BASE, +}; + +AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, + {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); + +/* uart device registration */ +AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, + {SPEAR3XX_IRQ_UART}, NULL); + +/* Do spear3xx familiy common initialization part here */ +void __init spear3xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear3xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ +struct map_desc spear3xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR3XX_ICM1_UART_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ML1_VIC_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear3xx_map_io(void) +{ + iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); + + /* This will initialize clock framework */ + spear3xx_clk_init(); +} /* pad multiplexing support */ /* devices */ @@ -448,68 +506,6 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { }; #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ -/* ssp device registration */ -struct pl022_ssp_controller pl022_plat_data = { - .bus_id = 0, - .enable_dma = 1, - .dma_filter = pl08x_filter_id, - .dma_tx_param = "ssp0_tx", - .dma_rx_param = "ssp0_rx", - /* - * This is number of spi devices that can be connected to spi. There are - * two type of chipselects on which slave devices can work. One is chip - * select provided by spi masters other is controlled through external - * gpio's. We can't use chipselect provided from spi master (because as - * soon as FIFO becomes empty, CS is disabled and transfer ends). So - * this number now depends on number of gpios available for spi. each - * slave on each master requires a separate gpio pin. - */ - .num_chipselect = 2, -}; - -/* dmac device registration */ -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, -}; - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xD0000000 0xFD000000 - * 0xFC000000 0xFC000000 - */ -struct map_desc spear3xx_io_desc[] __initdata = { - { - .virtual = VA_SPEAR3XX_ICM1_2_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), - .length = SZ_16M, - .type = MT_DEVICE - }, -}; - -/* This will create static memory mapping for selected devices */ -void __init spear3xx_map_io(void) -{ - iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); -} - static void __init spear3xx_timer_init(void) { char pclk_name[] = "pll3_48m_clk"; @@ -534,19 +530,9 @@ static void __init spear3xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1); + spear_setup_timer(); } struct sys_timer spear3xx_timer = { .init = spear3xx_timer_init, }; - -static const struct of_device_id vic_of_match[] __initconst = { - { .compatible = "arm,pl190-vic", .data = vic_of_init, }, - { /* Sentinel */ } -}; - -void __init spear3xx_dt_init_irq(void) -{ - of_irq_init(vic_of_match); -} diff --git a/trunk/arch/arm/mach-spear6xx/Makefile.boot b/trunk/arch/arm/mach-spear6xx/Makefile.boot index af493da37ab6..4674a4c221db 100644 --- a/trunk/arch/arm/mach-spear6xx/Makefile.boot +++ b/trunk/arch/arm/mach-spear6xx/Makefile.boot @@ -1,5 +1,3 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 - -dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb diff --git a/trunk/arch/arm/mach-spear6xx/clock.c b/trunk/arch/arm/mach-spear6xx/clock.c index bef77d43db87..a86499a8a15f 100644 --- a/trunk/arch/arm/mach-spear6xx/clock.c +++ b/trunk/arch/arm/mach-spear6xx/clock.c @@ -16,112 +16,6 @@ #include #include #include -#include - -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL1_MOD (MISC_BASE + 0x010) -#define PLL2_CTR (MISC_BASE + 0x014) -/* PLL_CTR register masks */ -#define PLL_ENABLE 2 -#define PLL_MODE_SHIFT 4 -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_NORMAL 0 -#define PLL_MODE_FRACTION 1 -#define PLL_MODE_DITH_DSB 2 -#define PLL_MODE_DITH_SSB 3 - -#define PLL2_FRQ (MISC_BASE + 0x018) -/* PLL FRQ register masks */ -#define PLL_DIV_N_SHIFT 0 -#define PLL_DIV_N_MASK 0xFF -#define PLL_DIV_P_SHIFT 8 -#define PLL_DIV_P_MASK 0x7 -#define PLL_NORM_FDBK_M_SHIFT 24 -#define PLL_NORM_FDBK_M_MASK 0xFF -#define PLL_DITH_FDBK_M_SHIFT 16 -#define PLL_DITH_FDBK_M_MASK 0xFFFF - -#define PLL2_MOD (MISC_BASE + 0x01C) -#define PLL_CLK_CFG (MISC_BASE + 0x020) -#define CORE_CLK_CFG (MISC_BASE + 0x024) -/* CORE CLK CFG register masks */ -#define PLL_HCLK_RATIO_SHIFT 10 -#define PLL_HCLK_RATIO_MASK 0x3 -#define HCLK_PCLK_RATIO_SHIFT 8 -#define HCLK_PCLK_RATIO_MASK 0x3 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) -/* PERIP_CLK_CFG register masks */ -#define CLCD_CLK_SHIFT 2 -#define CLCD_CLK_MASK 0x3 -#define UART_CLK_SHIFT 4 -#define UART_CLK_MASK 0x1 -#define FIRDA_CLK_SHIFT 5 -#define FIRDA_CLK_MASK 0x3 -#define GPT0_CLK_SHIFT 8 -#define GPT1_CLK_SHIFT 10 -#define GPT2_CLK_SHIFT 11 -#define GPT3_CLK_SHIFT 12 -#define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_VAL 0 -#define AUX_CLK_PLL1_VAL 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) -/* PERIP1_CLK_ENB register masks */ -#define UART0_CLK_ENB 3 -#define UART1_CLK_ENB 4 -#define SSP0_CLK_ENB 5 -#define SSP1_CLK_ENB 6 -#define I2C_CLK_ENB 7 -#define JPEG_CLK_ENB 8 -#define FSMC_CLK_ENB 9 -#define FIRDA_CLK_ENB 10 -#define GPT2_CLK_ENB 11 -#define GPT3_CLK_ENB 12 -#define GPIO2_CLK_ENB 13 -#define SSP2_CLK_ENB 14 -#define ADC_CLK_ENB 15 -#define GPT1_CLK_ENB 11 -#define RTC_CLK_ENB 17 -#define GPIO1_CLK_ENB 18 -#define DMA_CLK_ENB 19 -#define SMI_CLK_ENB 21 -#define CLCD_CLK_ENB 22 -#define GMAC_CLK_ENB 23 -#define USBD_CLK_ENB 24 -#define USBH0_CLK_ENB 25 -#define USBH1_CLK_ENB 26 - -#define PRSC1_CLK_CFG (MISC_BASE + 0x044) -#define PRSC2_CLK_CFG (MISC_BASE + 0x048) -#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) -/* gpt synthesizer register masks */ -#define GPT_MSCALE_SHIFT 0 -#define GPT_MSCALE_MASK 0xFFF -#define GPT_NSCALE_SHIFT 12 -#define GPT_NSCALE_MASK 0xF - -#define AMEM_CLK_CFG (MISC_BASE + 0x050) -#define EXPI_CLK_CFG (MISC_BASE + 0x054) -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) -#define GMAC_CLK_SYNT (MISC_BASE + 0x068) -#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) -#define RAS2_CLK_SYNT (MISC_BASE + 0x070) -#define RAS3_CLK_SYNT (MISC_BASE + 0x074) -#define RAS4_CLK_SYNT (MISC_BASE + 0x078) -/* aux clk synthesiser register masks for irda to ras4 */ -#define AUX_SYNT_ENB 31 -#define AUX_EQ_SEL_SHIFT 30 -#define AUX_EQ_SEL_MASK 1 -#define AUX_EQ1_SEL 0 -#define AUX_EQ2_SEL 1 -#define AUX_XSCALE_SHIFT 16 -#define AUX_XSCALE_MASK 0xFFF -#define AUX_YSCALE_SHIFT 0 -#define AUX_YSCALE_MASK 0xFFF /* root clks */ /* 32 KHz oscillator clock */ @@ -729,53 +623,53 @@ static struct clk dummy_apb_pclk; /* array of all spear 6xx clock lookups */ static struct clk_lookup spear_clk_lookups[] = { - CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, /* root clks */ - CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), - CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk), + { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, + { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, /* clock derived from 32 KHz os clk */ - CLKDEV_INIT("rtc-spear", NULL, &rtc_clk), + { .dev_id = "rtc-spear", .clk = &rtc_clk}, /* clock derived from 30 MHz os clk */ - CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), - CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), - CLKDEV_INIT("wdt", NULL, &wdt_clk), + { .con_id = "pll1_clk", .clk = &pll1_clk}, + { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, + { .dev_id = "wdt", .clk = &wdt_clk}, /* clock derived from pll1 clk */ - CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), - CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), - CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), - CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), - CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk), - CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), - CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), - CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk), - CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk), - CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk), - CLKDEV_INIT("firda", NULL, &firda_clk), - CLKDEV_INIT("clcd", NULL, &clcd_clk), - CLKDEV_INIT("gpt0", NULL, &gpt0_clk), - CLKDEV_INIT("gpt1", NULL, &gpt1_clk), - CLKDEV_INIT("gpt2", NULL, &gpt2_clk), - CLKDEV_INIT("gpt3", NULL, &gpt3_clk), + { .con_id = "cpu_clk", .clk = &cpu_clk}, + { .con_id = "ahb_clk", .clk = &ahb_clk}, + { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, + { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, + { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, + { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, + { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, + { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, + { .dev_id = "d0000000.serial", .clk = &uart0_clk}, + { .dev_id = "d0080000.serial", .clk = &uart1_clk}, + { .dev_id = "firda", .clk = &firda_clk}, + { .dev_id = "clcd", .clk = &clcd_clk}, + { .dev_id = "gpt0", .clk = &gpt0_clk}, + { .dev_id = "gpt1", .clk = &gpt1_clk}, + { .dev_id = "gpt2", .clk = &gpt2_clk}, + { .dev_id = "gpt3", .clk = &gpt3_clk}, /* clock derived from pll3 clk */ - CLKDEV_INIT("designware_udc", NULL, &usbd_clk), - CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), - CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + { .dev_id = "designware_udc", .clk = &usbd_clk}, + { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, + { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, /* clock derived from ahb clk */ - CLKDEV_INIT(NULL, "apb_clk", &apb_clk), - CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk), - CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), - CLKDEV_INIT("jpeg", NULL, &jpeg_clk), - CLKDEV_INIT("gmac", NULL, &gmac_clk), - CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), - CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk), + { .con_id = "apb_clk", .clk = &apb_clk}, + { .dev_id = "d0200000.i2c", .clk = &i2c_clk}, + { .dev_id = "dma", .clk = &dma_clk}, + { .dev_id = "jpeg", .clk = &jpeg_clk}, + { .dev_id = "gmac", .clk = &gmac_clk}, + { .dev_id = "smi", .clk = &smi_clk}, + { .dev_id = "fsmc-nand", .clk = &fsmc_clk}, /* clock derived from apb clk */ - CLKDEV_INIT("adc", NULL, &adc_clk), - CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk), - CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk), - CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk), - CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk), - CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk), - CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk), + { .dev_id = "adc", .clk = &adc_clk}, + { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, + { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, + { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, + { .dev_id = "f0100000.gpio", .clk = &gpio0_clk}, + { .dev_id = "fc980000.gpio", .clk = &gpio1_clk}, + { .dev_id = "d8100000.gpio", .clk = &gpio2_clk}, }; void __init spear6xx_clk_init(void) diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/generic.h b/trunk/arch/arm/mach-spear6xx/include/mach/generic.h index 7167fd331d86..116b99301cf5 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/generic.h @@ -15,9 +15,34 @@ #define __MACH_GENERIC_H #include +#include +#include +#include +#include -void __init spear_setup_timer(resource_size_t base, int irq); -void spear_restart(char, const char *); +/* + * Each GPT has 2 timer channels + * Following GPT channels will be used as clock source and clockevent + */ +#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE +#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 + +/* Add spear6xx family device structure declarations here */ +extern struct amba_device gpio_device[]; +extern struct amba_device uart_device[]; +extern struct sys_timer spear6xx_timer; + +/* Add spear6xx family function declarations here */ +void __init spear_setup_timer(void); +void __init spear6xx_map_io(void); +void __init spear6xx_init_irq(void); +void __init spear6xx_init(void); +void __init spear600_init(void); void __init spear6xx_clk_init(void); +void spear_restart(char, const char *); + +/* Add spear600 machine device structure declarations here */ + #endif /* __MACH_GENERIC_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h b/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h index 40a8c178f10d..0b3f96ae2848 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -1 +1,23 @@ -/* empty */ +/* + * arch/arm/mach-spear6xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H + +#include +#include + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __MACH_HARDWARE_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h b/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h index 2b735389e74b..8f214b03d75d 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -16,13 +16,82 @@ /* IRQ definitions */ /* VIC 1 */ -/* FIXME: probe this from DT */ +#define IRQ_INTRCOMM_SW_IRQ 0 +#define IRQ_INTRCOMM_CPU_1 1 +#define IRQ_INTRCOMM_CPU_2 2 +#define IRQ_INTRCOMM_RAS2A11_1 3 +#define IRQ_INTRCOMM_RAS2A11_2 4 +#define IRQ_INTRCOMM_RAS2A12_1 5 +#define IRQ_INTRCOMM_RAS2A12_2 6 +#define IRQ_GEN_RAS_0 7 +#define IRQ_GEN_RAS_1 8 +#define IRQ_GEN_RAS_2 9 +#define IRQ_GEN_RAS_3 10 +#define IRQ_GEN_RAS_4 11 +#define IRQ_GEN_RAS_5 12 +#define IRQ_GEN_RAS_6 13 +#define IRQ_GEN_RAS_7 14 +#define IRQ_GEN_RAS_8 15 #define IRQ_CPU_GPT1_1 16 +#define IRQ_CPU_GPT1_2 17 +#define IRQ_LOCAL_GPIO 18 +#define IRQ_PLL_UNLOCK 19 +#define IRQ_JPEG 20 +#define IRQ_FSMC 21 +#define IRQ_IRDA 22 +#define IRQ_RESERVED 23 +#define IRQ_UART_0 24 +#define IRQ_UART_1 25 +#define IRQ_SSP_1 26 +#define IRQ_SSP_2 27 +#define IRQ_I2C 28 +#define IRQ_GEN_RAS_9 29 +#define IRQ_GEN_RAS_10 30 +#define IRQ_GEN_RAS_11 31 + +/* VIC 2 */ +#define IRQ_APPL_GPT1_1 32 +#define IRQ_APPL_GPT1_2 33 +#define IRQ_APPL_GPT2_1 34 +#define IRQ_APPL_GPT2_2 35 +#define IRQ_APPL_GPIO 36 +#define IRQ_APPL_SSP 37 +#define IRQ_APPL_ADC 38 +#define IRQ_APPL_RESERVED 39 +#define IRQ_AHB_EXP_MASTER 40 +#define IRQ_DDR_CONTROLLER 41 +#define IRQ_BASIC_DMA 42 +#define IRQ_BASIC_RESERVED1 43 +#define IRQ_BASIC_SMI 44 +#define IRQ_BASIC_CLCD 45 +#define IRQ_EXP_AHB_1 46 +#define IRQ_EXP_AHB_2 47 +#define IRQ_BASIC_GPT1_1 48 +#define IRQ_BASIC_GPT1_2 49 +#define IRQ_BASIC_RTC 50 +#define IRQ_BASIC_GPIO 51 +#define IRQ_BASIC_WDT 52 +#define IRQ_BASIC_RESERVED 53 +#define IRQ_AHB_EXP_SLAVE 54 +#define IRQ_GMAC_1 55 +#define IRQ_GMAC_2 56 +#define IRQ_USB_DEV 57 +#define IRQ_USB_H_OHCI_0 58 +#define IRQ_USB_H_EHCI_0 59 +#define IRQ_USB_H_OHCI_1 60 +#define IRQ_USB_H_EHCI_1 61 +#define IRQ_EXP_AHB_3 62 +#define IRQ_EXP_AHB_4 63 #define IRQ_VIC_END 64 /* GPIO pins virtual irqs */ -#define VIRTUAL_IRQS 24 -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#define SPEAR_GPIO_INT_BASE IRQ_VIC_END +#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE +#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) +#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) +#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) +#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) #endif /* __MACH_IRQS_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h index 2b9aaa6cdd11..68c20a007b0d 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -14,7 +14,161 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H +#include + #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) + +#define SOC_CFG_CTR (MISC_BASE + 0x000) +#define DIAG_CFG_CTR (MISC_BASE + 0x004) +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ (MISC_BASE + 0x018) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG (MISC_BASE + 0x028) +/* PERIP_CLK_CFG register masks */ +#define CLCD_CLK_SHIFT 2 +#define CLCD_CLK_MASK 0x3 +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 10 +#define GPT2_CLK_SHIFT 11 +#define GPT3_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 + +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) +/* PERIP1_CLK_ENB register masks */ +#define UART0_CLK_ENB 3 +#define UART1_CLK_ENB 4 +#define SSP0_CLK_ENB 5 +#define SSP1_CLK_ENB 6 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FSMC_CLK_ENB 9 +#define FIRDA_CLK_ENB 10 +#define GPT2_CLK_ENB 11 +#define GPT3_CLK_ENB 12 +#define GPIO2_CLK_ENB 13 +#define SSP2_CLK_ENB 14 +#define ADC_CLK_ENB 15 +#define GPT1_CLK_ENB 11 +#define RTC_CLK_ENB 17 +#define GPIO1_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define CLCD_CLK_ENB 22 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH0_CLK_ENB 25 +#define USBH1_CLK_ENB 26 + +#define SOC_CORE_ID (MISC_BASE + 0x030) +#define RAS_CLK_ENB (MISC_BASE + 0x034) +#define PERIP1_SOF_RST (MISC_BASE + 0x038) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID (MISC_BASE + 0x03C) +#define RAS_SOF_RST (MISC_BASE + 0x040) +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG (MISC_BASE + 0x07C) +#define ICM2_ARB_CFG (MISC_BASE + 0x080) +#define ICM3_ARB_CFG (MISC_BASE + 0x084) +#define ICM4_ARB_CFG (MISC_BASE + 0x088) +#define ICM5_ARB_CFG (MISC_BASE + 0x08C) +#define ICM6_ARB_CFG (MISC_BASE + 0x090) +#define ICM7_ARB_CFG (MISC_BASE + 0x094) +#define ICM8_ARB_CFG (MISC_BASE + 0x098) +#define ICM9_ARB_CFG (MISC_BASE + 0x09C) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) +#define USB2_PHY_CFG (MISC_BASE + 0x0A4) +#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) +#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) +#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) +#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) +#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) +#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) +#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) +#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) +#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) +#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) +#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) +#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) +#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) +#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) +#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) +#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) +#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) +#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) +#define BIST4_CFG_CTR (MISC_BASE + 0x100) +#define BIST5_CFG_CTR (MISC_BASE + 0x104) +#define BIST1_STS_RES (MISC_BASE + 0x108) +#define BIST2_STS_RES (MISC_BASE + 0x10C) +#define BIST3_STS_RES (MISC_BASE + 0x110) +#define BIST4_STS_RES (MISC_BASE + 0x114) +#define BIST5_STS_RES (MISC_BASE + 0x118) +#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/spear.h b/trunk/arch/arm/mach-spear6xx/include/mach/spear.h index d278ed047a53..7fd621532def 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/spear.h @@ -15,26 +15,69 @@ #define __MACH_SPEAR6XX_H #include +#include +#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000) /* ICM1 - Low speed connection */ #define SPEAR6XX_ICM1_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) + #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) +#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) + +#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000) +#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000) +#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000) +#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000) +#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000) +#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000) +#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000) +#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000) +#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000) + +/* ICM2 - Application Subsystem */ +#define SPEAR6XX_ICM2_BASE UL(0xD8000000) +#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000) +#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000) +#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000) +#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000) +#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000) /* ML-1, 2 - Multi Layer CPU Subsystem */ #define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) -#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) #define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) +#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000) +#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000) +#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) +#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000) +#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) /* ICM3 - Basic Subsystem */ +#define SPEAR6XX_ICM3_BASE UL(0xF8000000) +#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) #define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) +#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000) +#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000) +#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000) +#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) #define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) + +/* ICM4 - High Speed Connection */ +#define SPEAR6XX_ICM4_BASE UL(0xE0000000) +#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000) +#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) +#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000) +#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) +#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000) +#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) +#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000) +#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) +#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h b/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h new file mode 100644 index 000000000000..c068cc50b0fb --- /dev/null +++ b/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-spear66xx/include/mach/spear600.h + * + * SPEAr600 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR600 + +#ifndef __MACH_SPEAR600_H +#define __MACH_SPEAR600_H + +#endif /* __MACH_SPEAR600_H */ + +#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/trunk/arch/arm/mach-spear6xx/spear6xx.c b/trunk/arch/arm/mach-spear6xx/spear6xx.c index de194dbb8371..2ed8b14c82c8 100644 --- a/trunk/arch/arm/mach-spear6xx/spear6xx.c +++ b/trunk/arch/arm/mach-spear6xx/spear6xx.c @@ -13,404 +13,41 @@ * warranty of any kind, whether express or implied. */ -#include -#include -#include #include #include #include #include -#include #include #include -#include -#include -#include #include -#include +#include -/* dmac device registration */ -static struct pl08x_channel_data spear600_dma_info[] = { +/* Following will create static virtual/physical mappings */ +static struct map_desc spear6xx_io_desc[] __initdata = { { - .bus_id = "ssp1_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp1_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart0_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "uart1_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp2_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp2_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ssp0_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ssp0_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "i2c_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "irda", - .min_signal = 12, - .max_signal = 12, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "adc", - .min_signal = 13, - .max_signal = 13, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "to_jpeg", - .min_signal = 14, - .max_signal = 14, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "from_jpeg", - .min_signal = 15, - .max_signal = 15, - .muxval = 0, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ras7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 1, - .cctl = 0, - .periph_buses = PL08X_AHB1, - }, { - .bus_id = "ext0_rx", - .min_signal = 0, - .max_signal = 0, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext0_tx", - .min_signal = 1, - .max_signal = 1, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_rx", - .min_signal = 2, - .max_signal = 2, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext1_tx", - .min_signal = 3, - .max_signal = 3, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_rx", - .min_signal = 4, - .max_signal = 4, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext2_tx", - .min_signal = 5, - .max_signal = 5, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_rx", - .min_signal = 6, - .max_signal = 6, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext3_tx", - .min_signal = 7, - .max_signal = 7, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_rx", - .min_signal = 8, - .max_signal = 8, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext4_tx", - .min_signal = 9, - .max_signal = 9, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_rx", - .min_signal = 10, - .max_signal = 10, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext5_tx", - .min_signal = 11, - .max_signal = 11, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_rx", - .min_signal = 12, - .max_signal = 12, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, { - .bus_id = "ext6_tx", - .min_signal = 13, - .max_signal = 13, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, + .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE }, { - .bus_id = "ext7_rx", - .min_signal = 14, - .max_signal = 14, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, + .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), + .length = SZ_4K, + .type = MT_DEVICE }, { - .bus_id = "ext7_tx", - .min_signal = 15, - .max_signal = 15, - .muxval = 2, - .cctl = 0, - .periph_buses = PL08X_AHB2, - }, -}; - -struct pl08x_platform_data pl080_plat_data = { - .memcpy_channel = { - .bus_id = "memcpy", - .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ - PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ - PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ - PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ - PL080_CONTROL_PROT_SYS), - }, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, - .get_signal = pl080_get_signal, - .put_signal = pl080_put_signal, - .slave_channels = spear600_dma_info, - .num_slave_channels = ARRAY_SIZE(spear600_dma_info), -}; - -/* - * Following will create 16MB static virtual/physical mappings - * PHYSICAL VIRTUAL - * 0xF0000000 0xF0000000 - * 0xF1000000 0xF1000000 - * 0xD0000000 0xFD000000 - * 0xFC000000 0xFC000000 - */ -struct map_desc spear6xx_io_desc[] __initdata = { - { - .virtual = VA_SPEAR6XX_ML_CPU_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), - .length = 2 * SZ_16M, + .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), + .length = SZ_4K, .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_ICM1_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), - .length = SZ_16M, + }, { + .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), + .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), - .length = SZ_16M, + .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), + .length = SZ_4K, .type = MT_DEVICE }, }; @@ -448,24 +85,16 @@ static void __init spear6xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1); + spear_setup_timer(); } struct sys_timer spear6xx_timer = { .init = spear6xx_timer_init, }; -/* Add auxdata to pass platform data */ -struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, - &pl080_plat_data), - {} -}; - static void __init spear600_dt_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, - spear6xx_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *spear600_dt_board_compat[] = { diff --git a/trunk/arch/arm/plat-spear/Kconfig b/trunk/arch/arm/plat-spear/Kconfig index 6c066fcb2979..1bb3dbce8810 100644 --- a/trunk/arch/arm/plat-spear/Kconfig +++ b/trunk/arch/arm/plat-spear/Kconfig @@ -9,10 +9,9 @@ choice default ARCH_SPEAR3XX config ARCH_SPEAR3XX - bool "ST SPEAr3xx with Device Tree" + bool "SPEAr3XX" select ARM_VIC select CPU_ARM926T - select USE_OF help Supports for ARM's SPEAR3XX family diff --git a/trunk/arch/arm/plat-spear/Makefile b/trunk/arch/arm/plat-spear/Makefile index 4af6258d0fee..e0f2e5b9530c 100644 --- a/trunk/arch/arm/plat-spear/Makefile +++ b/trunk/arch/arm/plat-spear/Makefile @@ -3,6 +3,6 @@ # # Common support -obj-y := clock.o restart.o time.o pl080.o +obj-y := clock.o restart.o time.o obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o diff --git a/trunk/arch/arm/plat-spear/include/plat/debug-macro.S b/trunk/arch/arm/plat-spear/include/plat/debug-macro.S index ab3de721c5db..02b160a1ec9b 100644 --- a/trunk/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/trunk/arch/arm/plat-spear/include/plat/debug-macro.S @@ -12,7 +12,7 @@ */ #include -#include +#include .macro addruart, rp, rv, tmp mov \rp, #SPEAR_DBG_UART_BASE @ Physical base diff --git a/trunk/arch/arm/plat-spear/include/plat/hardware.h b/trunk/arch/arm/plat-spear/include/plat/hardware.h new file mode 100644 index 000000000000..70187d763e26 --- /dev/null +++ b/trunk/arch/arm/plat-spear/include/plat/hardware.h @@ -0,0 +1,17 @@ +/* + * arch/arm/plat-spear/include/plat/hardware.h + * + * Hardware definitions for SPEAr + * + * Copyright (C) 2010 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_HARDWARE_H +#define __PLAT_HARDWARE_H + +#endif /* __PLAT_HARDWARE_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/pl080.h b/trunk/arch/arm/plat-spear/include/plat/pl080.h deleted file mode 100644 index e14a3e4932f9..000000000000 --- a/trunk/arch/arm/plat-spear/include/plat/pl080.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/pl080.h - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_PL080_H -#define __PLAT_PL080_H - -struct pl08x_dma_chan; -int pl080_get_signal(struct pl08x_dma_chan *ch); -void pl080_put_signal(struct pl08x_dma_chan *ch); - -#endif /* __PLAT_PL080_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/uncompress.h b/trunk/arch/arm/plat-spear/include/plat/uncompress.h index 6dd455bafdfd..1bf84527aee4 100644 --- a/trunk/arch/arm/plat-spear/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-spear/include/plat/uncompress.h @@ -13,7 +13,7 @@ #include #include -#include +#include #ifndef __PLAT_UNCOMPRESS_H #define __PLAT_UNCOMPRESS_H diff --git a/trunk/arch/arm/plat-spear/pl080.c b/trunk/arch/arm/plat-spear/pl080.c deleted file mode 100644 index a56a067717c1..000000000000 --- a/trunk/arch/arm/plat-spear/pl080.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/plat-spear/pl080.c - * - * DMAC pl080 definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); - -struct { - unsigned char busy; - unsigned char val; -} signals[16] = {{0, 0}, }; - -int pl080_get_signal(struct pl08x_dma_chan *ch) -{ - const struct pl08x_channel_data *cd = ch->cd; - unsigned int signal = cd->min_signal, val; - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* Return if signal is already acquired by somebody else */ - if (signals[signal].busy && - (signals[signal].val != cd->muxval)) { - spin_unlock_irqrestore(&lock, flags); - return -EBUSY; - } - - /* If acquiring for the first time, configure it */ - if (!signals[signal].busy) { - val = readl(DMA_CHN_CFG); - - /* - * Each request line has two bits in DMA_CHN_CFG register. To - * goto the bits of current request line, do left shift of - * value by 2 * signal number. - */ - val &= ~(0x3 << (signal * 2)); - val |= cd->muxval << (signal * 2); - writel(val, DMA_CHN_CFG); - } - - signals[signal].busy++; - signals[signal].val = cd->muxval; - spin_unlock_irqrestore(&lock, flags); - - return signal; -} - -void pl080_put_signal(struct pl08x_dma_chan *ch) -{ - const struct pl08x_channel_data *cd = ch->cd; - unsigned long flags; - - spin_lock_irqsave(&lock, flags); - - /* if signal is not used */ - if (!signals[cd->min_signal].busy) - BUG(); - - signals[cd->min_signal].busy--; - - spin_unlock_irqrestore(&lock, flags); -} diff --git a/trunk/arch/arm/plat-spear/restart.c b/trunk/arch/arm/plat-spear/restart.c index 4471a232713a..16f203e78d89 100644 --- a/trunk/arch/arm/plat-spear/restart.c +++ b/trunk/arch/arm/plat-spear/restart.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include void spear_restart(char mode, const char *cmd) diff --git a/trunk/arch/arm/plat-spear/time.c b/trunk/arch/arm/plat-spear/time.c index a3164d1647fd..abb5bdecd509 100644 --- a/trunk/arch/arm/plat-spear/time.c +++ b/trunk/arch/arm/plat-spear/time.c @@ -15,13 +15,14 @@ #include #include #include -#include #include #include #include #include #include #include +#include +#include /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. @@ -174,7 +175,7 @@ static struct irqaction spear_timer_irq = { .handler = spear_timer_interrupt }; -static void __init spear_clockevent_init(int irq) +static void __init spear_clockevent_init(void) { u32 tick_rate; @@ -194,19 +195,19 @@ static void __init spear_clockevent_init(int irq) clockevents_register_device(&clkevt); - setup_irq(irq, &spear_timer_irq); + setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); } -void __init spear_setup_timer(resource_size_t base, int irq) +void __init spear_setup_timer(void) { int ret; - if (!request_mem_region(base, SZ_1K, "gpt0")) { + if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { pr_err("%s:cannot get IO addr\n", __func__); return; } - gpt_base = ioremap(base, SZ_1K); + gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); if (!gpt_base) { pr_err("%s:ioremap failed for gpt\n", __func__); goto err_mem; @@ -224,7 +225,7 @@ void __init spear_setup_timer(resource_size_t base, int irq) goto err_clk; } - spear_clockevent_init(irq); + spear_clockevent_init(); spear_clocksource_init(); return; @@ -234,5 +235,5 @@ void __init spear_setup_timer(resource_size_t base, int irq) err_iomap: iounmap(gpt_base); err_mem: - release_mem_region(base, SZ_1K); + release_mem_region(SPEAR_GPT0_BASE, SZ_1K); } diff --git a/trunk/drivers/net/ethernet/nxp/lpc_eth.c b/trunk/drivers/net/ethernet/nxp/lpc_eth.c index 6dfc26d85e47..52deec0b22ea 100644 --- a/trunk/drivers/net/ethernet/nxp/lpc_eth.c +++ b/trunk/drivers/net/ethernet/nxp/lpc_eth.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -340,13 +341,17 @@ */ #define LPC_POWERDOWN_MACAHB (1 << 31) -/* Upon the upcoming introduction of device tree usage in LPC32xx, - * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a - * device parameter for access to device tree information at runtime, instead - * of defining the values at compile time - */ -static inline phy_interface_t lpc_phy_interface_mode(void) +static phy_interface_t lpc_phy_interface_mode(struct device *dev) { + if (dev && dev->of_node) { + const char *mode = of_get_property(dev->of_node, + "phy-mode", NULL); + if (mode && !strcmp(mode, "mii")) + return PHY_INTERFACE_MODE_MII; + return PHY_INTERFACE_MODE_RMII; + } + + /* non-DT */ #ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT return PHY_INTERFACE_MODE_MII; #else @@ -354,12 +359,16 @@ static inline phy_interface_t lpc_phy_interface_mode(void) #endif } -static inline int use_iram_for_net(void) +static bool use_iram_for_net(struct device *dev) { + if (dev && dev->of_node) + return of_property_read_bool(dev->of_node, "use-iram"); + + /* non-DT */ #ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET - return 1; + return true; #else - return 0; + return false; #endif } @@ -664,7 +673,7 @@ static void __lpc_eth_init(struct netdata_local *pldat) LPC_ENET_CLRT(pldat->net_base)); writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) writel(LPC_COMMAND_PASSRUNTFRAME, LPC_ENET_COMMAND(pldat->net_base)); else { @@ -804,12 +813,13 @@ static int lpc_mii_probe(struct net_device *ndev) } /* Attach to the PHY */ - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) netdev_info(ndev, "using MII interface\n"); else netdev_info(ndev, "using RMII interface\n"); phydev = phy_connect(ndev, dev_name(&phydev->dev), - &lpc_handle_link_change, 0, lpc_phy_interface_mode()); + &lpc_handle_link_change, 0, + lpc_phy_interface_mode(&pldat->pdev->dev)); if (IS_ERR(phydev)) { netdev_err(ndev, "Could not attach to PHY\n"); @@ -843,7 +853,7 @@ static int lpc_mii_init(struct netdata_local *pldat) } /* Setup MII mode */ - if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII) + if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) writel(LPC_COMMAND_PASSRUNTFRAME, LPC_ENET_COMMAND(pldat->net_base)); else { @@ -1315,18 +1325,26 @@ static const struct net_device_ops lpc_netdev_ops = { static int lpc_eth_drv_probe(struct platform_device *pdev) { struct resource *res; - struct resource *dma_res; struct net_device *ndev; struct netdata_local *pldat; struct phy_device *phydev; dma_addr_t dma_handle; int irq, ret; + u32 tmp; + + /* Setup network interface for RMII or MII mode */ + tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; + if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII) + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; + else + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); /* Get platform resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); irq = platform_get_irq(pdev, 0); - if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) { + if ((!res) || (irq < 0) || (irq >= NR_IRQS)) { dev_err(&pdev->dev, "error getting resources.\n"); ret = -ENXIO; goto err_exit; @@ -1389,17 +1407,19 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); pldat->dma_buff_base_v = 0; - if (use_iram_for_net()) { - dma_handle = dma_res->start; + if (use_iram_for_net(&pldat->pdev->dev)) { + dma_handle = LPC32XX_IRAM_BASE; if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) pldat->dma_buff_base_v = - io_p2v(dma_res->start); + io_p2v(LPC32XX_IRAM_BASE); else netdev_err(ndev, "IRAM not big enough for net buffers, using SDRAM instead.\n"); } if (pldat->dma_buff_base_v == 0) { + pldat->pdev->dev.coherent_dma_mask = 0xFFFFFFFF; + pldat->pdev->dev.dma_mask = &pldat->pdev->dev.coherent_dma_mask; pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size); /* Allocate a chunk of memory for the DMA ethernet buffers @@ -1488,7 +1508,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); unregister_netdev(ndev); err_out_dma_unmap: - if (!use_iram_for_net() || + if (!use_iram_for_net(&pldat->pdev->dev) || pldat->dma_buff_size > lpc32xx_return_iram_size()) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, @@ -1515,7 +1535,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) unregister_netdev(ndev); platform_set_drvdata(pdev, NULL); - if (!use_iram_for_net() || + if (!use_iram_for_net(&pldat->pdev->dev) || pldat->dma_buff_size > lpc32xx_return_iram_size()) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, @@ -1584,6 +1604,14 @@ static int lpc_eth_drv_resume(struct platform_device *pdev) } #endif +#ifdef CONFIG_OF +static const struct of_device_id lpc_eth_match[] = { + { .compatible = "nxp,lpc-eth" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpc_eth_match); +#endif + static struct platform_driver lpc_eth_driver = { .probe = lpc_eth_drv_probe, .remove = __devexit_p(lpc_eth_drv_remove), @@ -1593,6 +1621,7 @@ static struct platform_driver lpc_eth_driver = { #endif .driver = { .name = MODNAME, + .of_match_table = of_match_ptr(lpc_eth_match), }, }; diff --git a/trunk/drivers/of/address.c b/trunk/drivers/of/address.c index 7e262a6124c5..66d96f14c274 100644 --- a/trunk/drivers/of/address.c +++ b/trunk/drivers/of/address.c @@ -1,5 +1,4 @@ -#include #include #include #include