From b35bad50afda3558465a43f1ca6b668b1ea24888 Mon Sep 17 00:00:00 2001 From: Raphael Assenat Date: Tue, 3 Oct 2006 01:15:03 -0700 Subject: [PATCH] --- yaml --- r: 38071 b: refs/heads/master c: 8bc218410d6c2b22a7581fac6f3dc2ac1f8fc99f h: refs/heads/master i: 38069: b276f9b71e40f8a7bf474e643f7a2f2d5324cd45 38067: c8baa690a41827cf11f6dc24ff288dd359834cb2 38063: 5999a518ef5cf64a3bab17e749d68642595d203b v: v3 --- [refs] | 2 +- trunk/drivers/video/mbx/mbxfb.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index d04bafe3ca57..dbf5f9d765d6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9c5b39e0bcb407a95716de4650a2d1e6064baffa +refs/heads/master: 8bc218410d6c2b22a7581fac6f3dc2ac1f8fc99f diff --git a/trunk/drivers/video/mbx/mbxfb.c b/trunk/drivers/video/mbx/mbxfb.c index 6849ab75d403..cfc6bf3615b5 100644 --- a/trunk/drivers/video/mbx/mbxfb.c +++ b/trunk/drivers/video/mbx/mbxfb.c @@ -118,8 +118,19 @@ static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps, /* convert pixclock to KHz */ pixclock = PICOS2KHZ(pixclock_ps); + /* PLL output freq = (ref_clk * M) / (N * 2^P) + * + * M: 1 to 63 + * N: 1 to 7 + * P: 0 to 7 + */ + + /* RAPH: When N==1, the resulting pixel clock appears to + * get divided by 2. Preventing N=1 by starting the following + * loop at 2 prevents this. Is this a bug with my chip + * revision or something I dont understand? */ for (m = 1; m < 64; m++) { - for (n = 1; n < 8; n++) { + for (n = 2; n < 8; n++) { for (p = 0; p < 8; p++) { clk = (ref_clk * m) / (n * (1 << p)); err = (clk > pixclock) ? (clk - pixclock) :