From b3908821652391a6bb315e8fb11b8007dac88dbe Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 6 Jan 2011 21:19:20 -0500 Subject: [PATCH] --- yaml --- r: 228867 b: refs/heads/master c: d07f4e83506712f31ad661415ea28d536a70a939 h: refs/heads/master i: 228865: 62826a3957812f4ad8d01484b0dab0573cc2cec7 228863: 40b41663b11443c2202cf53648e27f649b346462 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/radeon_encoders.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index b93a276a918a..2f76da30362c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 69c74525c26a1b71116d9bd3a136bf1314a3e8cd +refs/heads/master: d07f4e83506712f31ad661415ea28d536a70a939 diff --git a/trunk/drivers/gpu/drm/radeon/radeon_encoders.c b/trunk/drivers/gpu/drm/radeon/radeon_encoders.c index 2e1d720fca06..3866c648423b 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_encoders.c @@ -1228,6 +1228,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) int index = 0; bool is_dig = false; bool is_dce5_dac = false; + bool is_dce5_dvo = false; memset(&args, 0, sizeof(args)); @@ -1250,7 +1251,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - if (ASIC_IS_DCE3(rdev)) + if (ASIC_IS_DCE5(rdev)) + is_dce5_dvo = true; + else if (ASIC_IS_DCE3(rdev)) is_dig = true; else index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); @@ -1345,6 +1348,17 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) atombios_dac_setup(encoder, ATOM_DISABLE); break; } + } else if (is_dce5_dvo) { + switch (mode) { + case DRM_MODE_DPMS_ON: + atombios_dvo_setup(encoder, ATOM_ENABLE); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + atombios_dvo_setup(encoder, ATOM_DISABLE); + break; + } } else { switch (mode) { case DRM_MODE_DPMS_ON: