From b3a130d6312d28f9cb0697a4e009ec4d9d60a4d8 Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Tue, 19 Apr 2011 15:04:20 -0400 Subject: [PATCH] --- yaml --- r: 286291 b: refs/heads/master c: 22605f96810d073eb74051d0295b6577d6a6a563 h: refs/heads/master i: 286289: 27f7b9928a546077789135d400aad60f4bf00094 286287: c1fabb3a91298a098b39c43b121bec912f2d98b5 v: v3 --- [refs] | 2 +- trunk/drivers/block/nvme.c | 10 ++++++++++ trunk/include/linux/nvme.h | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 10b3c7ddc5fd..08d2d8cf855a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: aba2080f3f1639f9202f1a52993669844abcfb80 +refs/heads/master: 22605f96810d073eb74051d0295b6577d6a6a563 diff --git a/trunk/drivers/block/nvme.c b/trunk/drivers/block/nvme.c index bcc780ac4ec0..57f2b33a47dd 100644 --- a/trunk/drivers/block/nvme.c +++ b/trunk/drivers/block/nvme.c @@ -893,6 +893,8 @@ static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) { int result; u32 aqa; + u64 cap; + unsigned long timeout; struct nvme_queue *nvmeq; dev->dbs = ((void __iomem *)dev->bar) + 4096; @@ -915,10 +917,18 @@ static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) writeq(nvmeq->cq_dma_addr, &dev->bar->acq); writel(dev->ctrl_config, &dev->bar->cc); + cap = readq(&dev->bar->cap); + timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; + while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { msleep(100); if (fatal_signal_pending(current)) return -EINTR; + if (time_after(jiffies, timeout)) { + dev_err(&dev->pci_dev->dev, + "Device not ready; aborting initialisation\n"); + return -ENODEV; + } } result = queue_request_irq(dev, nvmeq, "nvme admin"); diff --git a/trunk/include/linux/nvme.h b/trunk/include/linux/nvme.h index 9d6febb91521..a19304fefa7d 100644 --- a/trunk/include/linux/nvme.h +++ b/trunk/include/linux/nvme.h @@ -35,6 +35,8 @@ struct nvme_bar { __u64 acq; /* Admin CQ Base Address */ }; +#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) + enum { NVME_CC_ENABLE = 1 << 0, NVME_CC_CSS_NVM = 0 << 4,