From b3dff12c9e092e4b662f584db6d81af8afea1efe Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 21 Mar 2013 19:01:49 +0100
Subject: [PATCH] --- yaml --- r: 375139 b: refs/heads/master c:
 bb19fea238daead66ab3630ad09fba50aa563048 h: refs/heads/master i:   375137:
 310430a613b3c59996bf2d9c1ea261982add5933   375135:
 5395bb2a1469ca05f22d86d41df8bb0914050572 v: v3

---
 [refs]                                           |  2 +-
 trunk/arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 165efc0162fc..5616ce597c67 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 48b4aba7a8a2b098f12259ffa13301243349cfab
+refs/heads/master: bb19fea238daead66ab3630ad09fba50aa563048
diff --git a/trunk/arch/mips/include/asm/mach-ralink/rt305x.h b/trunk/arch/mips/include/asm/mach-ralink/rt305x.h
index 7d344f2d7d0a..e36c3c529423 100644
--- a/trunk/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/trunk/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
 #define RT305X_GPIO_MODE_SDRAM		BIT(8)
 #define RT305X_GPIO_MODE_RGMII		BIT(9)
 
+#define RT3352_SYSC_REG_SYSCFG0		0x010
+#define RT3352_SYSC_REG_SYSCFG1         0x014
+#define RT3352_SYSC_REG_CLKCFG1         0x030
+#define RT3352_SYSC_REG_RSTCTRL         0x034
+#define RT3352_SYSC_REG_USB_PS          0x05c
+
+#define RT3352_CLKCFG0_XTAL_SEL		BIT(20)
+#define RT3352_CLKCFG1_UPHY0_CLK_EN	BIT(18)
+#define RT3352_CLKCFG1_UPHY1_CLK_EN	BIT(20)
+#define RT3352_RSTCTRL_UHST		BIT(22)
+#define RT3352_RSTCTRL_UDEV		BIT(25)
+#define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
+
 #endif