diff --git a/[refs] b/[refs]
index 625349308cb4..4d14a712fe1e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5a668651bf0da3891c46ea2cfcac227ded783a5a
+refs/heads/master: 8d5fb297cc8f9f7de2840864e497bc38330abba6
diff --git a/trunk/include/asm-sh/cache.h b/trunk/include/asm-sh/cache.h
index 01e5cf51ba9b..083419f47c65 100644
--- a/trunk/include/asm-sh/cache.h
+++ b/trunk/include/asm-sh/cache.h
@@ -12,11 +12,6 @@
 #include <linux/init.h>
 #include <asm/cpu/cache.h>
 
-#define SH_CACHE_VALID		1
-#define SH_CACHE_UPDATED	2
-#define SH_CACHE_COMBINED	4
-#define SH_CACHE_ASSOC		8
-
 #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
 
 #define __read_mostly __attribute__((__section__(".data.read_mostly")))
diff --git a/trunk/include/asm-sh/cpu-sh2/cache.h b/trunk/include/asm-sh/cpu-sh2/cache.h
index f02ba7a672b2..66388ce16c30 100644
--- a/trunk/include/asm-sh/cpu-sh2/cache.h
+++ b/trunk/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT	4
 
+#define SH_CACHE_VALID		1
+#define SH_CACHE_UPDATED	2
+#define SH_CACHE_COMBINED	4
+#define SH_CACHE_ASSOC		8
+
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
 #define CCR1		0xffffffec
 #define CCR		CCR1
diff --git a/trunk/include/asm-sh/cpu-sh2a/cache.h b/trunk/include/asm-sh/cpu-sh2a/cache.h
index 3e4b9e480982..d88774169b58 100644
--- a/trunk/include/asm-sh/cpu-sh2a/cache.h
+++ b/trunk/include/asm-sh/cpu-sh2a/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT	4
 
+#define SH_CACHE_VALID		1
+#define SH_CACHE_UPDATED	2
+#define SH_CACHE_COMBINED	4
+#define SH_CACHE_ASSOC		8
+
 #define CCR1		0xfffc1000
 #define CCR2		0xfffc1004
 
diff --git a/trunk/include/asm-sh/cpu-sh3/cache.h b/trunk/include/asm-sh/cpu-sh3/cache.h
index 255016fc91f0..77dd45d82414 100644
--- a/trunk/include/asm-sh/cpu-sh3/cache.h
+++ b/trunk/include/asm-sh/cpu-sh3/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT	4
 
+#define SH_CACHE_VALID		1
+#define SH_CACHE_UPDATED	2
+#define SH_CACHE_COMBINED	4
+#define SH_CACHE_ASSOC		8
+
 #define CCR		0xffffffec	/* Address of Cache Control Register */
 
 #define CCR_CACHE_CE	0x01	/* Cache Enable */
diff --git a/trunk/include/asm-sh/cpu-sh4/cache.h b/trunk/include/asm-sh/cpu-sh4/cache.h
index f92b20a0983d..1c61ebf5c8e3 100644
--- a/trunk/include/asm-sh/cpu-sh4/cache.h
+++ b/trunk/include/asm-sh/cpu-sh4/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT	5
 
+#define SH_CACHE_VALID		1
+#define SH_CACHE_UPDATED	2
+#define SH_CACHE_COMBINED	4
+#define SH_CACHE_ASSOC		8
+
 #define CCR		0xff00001c	/* Address of Cache Control Register */
 #define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */
 #define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/