From b469b009936fd5b940468009760fdde2171a36cf Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 25 Oct 2012 12:15:43 -0700 Subject: [PATCH] --- yaml --- r: 345270 b: refs/heads/master c: 5c9664d75a65adcdb9763a6df1da1d8d3f417c0c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 80a5ce6acc45..b43ce81d4b22 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8ab4397640de51f4a93845b09270ad717244ccb3 +refs/heads/master: 5c9664d75a65adcdb9763a6df1da1d8d3f417c0c diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index aef23641fbcc..871bfe49b913 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -3695,6 +3695,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + /* WaForceL3Serialization */ + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & + ~L3SQ_URB_READ_CAM_MATCH_DISABLE); + /* This is required by WaCatErrorRejectionIssue */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |