From b46f482b451073b1f3005de6cb5fd4a2ac8016e0 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 Aug 2012 08:25:42 +0000
Subject: [PATCH] --- yaml --- r: 332230 b: refs/heads/master c:
 f40e1f9d856ec417468c090c4b56826171daa670 h: refs/heads/master v: v3

---
 [refs]                                | 2 +-
 trunk/arch/mips/lantiq/xway/sysctrl.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index f292275c7478..1c5a567e1151 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a
+refs/heads/master: f40e1f9d856ec417468c090c4b56826171daa670
diff --git a/trunk/arch/mips/lantiq/xway/sysctrl.c b/trunk/arch/mips/lantiq/xway/sysctrl.c
index befbb760ab76..67c3a91e54e7 100644
--- a/trunk/arch/mips/lantiq/xway/sysctrl.c
+++ b/trunk/arch/mips/lantiq/xway/sysctrl.c
@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
 {
 	unsigned int val = ltq_cgu_r32(ifccr);
 	/* set bus clock speed */
-	if (of_machine_is_compatible("lantiq,ar9")) {
+	if (of_machine_is_compatible("lantiq,ar9") ||
+			of_machine_is_compatible("lantiq,vr9")) {
 		val &= ~0x1f00000;
 		if (clk->rate == CLOCK_33M)
 			val |= 0xe00000;