From b479bb7a4a09b363571e0259979fe2b409b9bc74 Mon Sep 17 00:00:00 2001 From: Brian Gerst Date: Mon, 21 May 2007 14:31:53 +0200 Subject: [PATCH] --- yaml --- r: 56676 b: refs/heads/master c: 17304383ebc1ce68a88030ac4d18ea549d9578c7 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/i386/kernel/cpu/mtrr/cyrix.c | 2 +- trunk/arch/i386/kernel/cpu/mtrr/state.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index ddb2e73f44ae..a65a4337bdc3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d0aff6e6f4e54f79f9c89d147d371bad384454e9 +refs/heads/master: 17304383ebc1ce68a88030ac4d18ea549d9578c7 diff --git a/trunk/arch/i386/kernel/cpu/mtrr/cyrix.c b/trunk/arch/i386/kernel/cpu/mtrr/cyrix.c index 0737a596db43..9edf5625584f 100644 --- a/trunk/arch/i386/kernel/cpu/mtrr/cyrix.c +++ b/trunk/arch/i386/kernel/cpu/mtrr/cyrix.c @@ -136,7 +136,7 @@ static void prepare_set(void) /* Save value of CR4 and clear Page Global Enable (bit 7) */ if ( cpu_has_pge ) { cr4 = read_cr4(); - write_cr4(cr4 & (unsigned char) ~(1 << 7)); + write_cr4(cr4 & ~X86_CR4_PGE); } /* Disable and flush caches. Note that wbinvd flushes the TLBs as diff --git a/trunk/arch/i386/kernel/cpu/mtrr/state.c b/trunk/arch/i386/kernel/cpu/mtrr/state.c index f62ecd15811a..7b39a2f954d9 100644 --- a/trunk/arch/i386/kernel/cpu/mtrr/state.c +++ b/trunk/arch/i386/kernel/cpu/mtrr/state.c @@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) /* Save value of CR4 and clear Page Global Enable (bit 7) */ if ( cpu_has_pge ) { ctxt->cr4val = read_cr4(); - write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7)); + write_cr4(ctxt->cr4val & ~X86_CR4_PGE); } /* Disable and flush caches. Note that wbinvd flushes the TLBs as