From b4caded7fc443b4f1cdbcce1bb6113d52047f97b Mon Sep 17 00:00:00 2001
From: Changhwan Youn <chaos.youn@samsung.com>
Date: Tue, 4 Oct 2011 17:08:57 +0900
Subject: [PATCH] --- yaml --- r: 272807 b: refs/heads/master c:
 90a454b4c5ef16ec71797b3dcaf454e604c786a3 h: refs/heads/master i:   272805:
 b39d15f7a8d2432c2a5d1ea7e5766ac8e67a12e5   272803:
 747babe199192c2f12c18844460138269cbf71e4   272799:
 f9355822979103f51da6bc902b6cb453ab43a82f v: v3

---
 [refs]                                        |  2 +-
 trunk/arch/arm/mach-exynos4/cpu.c             |  8 +++++--
 .../mach-exynos4/include/mach/entry-macro.S   | 23 +++++++++++++++----
 .../arch/arm/mach-exynos4/include/mach/map.h  |  1 -
 trunk/arch/arm/mach-exynos4/platsmp.c         |  5 ++--
 5 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/[refs] b/[refs]
index 87b122b59ceb..ec6de54c0cfb 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b88b1cc72e2bbb55c56f2df55b5ad59a18ad1464
+refs/heads/master: 90a454b4c5ef16ec71797b3dcaf454e604c786a3
diff --git a/trunk/arch/arm/mach-exynos4/cpu.c b/trunk/arch/arm/mach-exynos4/cpu.c
index 940bc12f7547..a348434f17b5 100644
--- a/trunk/arch/arm/mach-exynos4/cpu.c
+++ b/trunk/arch/arm/mach-exynos4/cpu.c
@@ -32,6 +32,8 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 
+unsigned int gic_bank_offset __read_mostly;
+
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
 			 unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -203,16 +205,18 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 
 	gic_data->cpu_base = S5P_VA_GIC_CPU +
-			    (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+			    (gic_bank_offset * smp_processor_id());
 
 	gic_data->dist_base = S5P_VA_GIC_DIST +
-			    (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+			    (gic_bank_offset * smp_processor_id());
 }
 
 void __init exynos4_init_irq(void)
 {
 	int irq;
 
+	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
diff --git a/trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S b/trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 61393dcf5559..4c9adbd87eac 100644
--- a/trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/trunk/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
 		.endm
 
 		.macro  get_irqnr_preamble, base, tmp
-		ldr	\base, =gic_cpu_base_addr
+		mov	\tmp, #0
+
+		mrc	p15, 0, \base, c0, c0, 5
+		and	\base, \base, #3
+		cmp	\base, #0
+		beq	1f
+
+		ldr	\tmp, =gic_bank_offset
+		ldr	\tmp, [\tmp]
+		cmp	\base, #1
+		beq	1f
+
+		cmp	\base, #2
+		addeq	\tmp, \tmp, \tmp
+		addne	\tmp, \tmp, \tmp, LSL #1
+
+1:		ldr	\base, =gic_cpu_base_addr
 		ldr	\base, [\base]
-		mrc     p15, 0, \tmp, c0, c0, 5
-		and     \tmp, \tmp, #3
-		cmp     \tmp, #1
-		addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
+		add	\base, \base, \tmp
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
diff --git a/trunk/arch/arm/mach-exynos4/include/mach/map.h b/trunk/arch/arm/mach-exynos4/include/mach/map.h
index 7073ac730855..9f97eb8499ee 100644
--- a/trunk/arch/arm/mach-exynos4/include/mach/map.h
+++ b/trunk/arch/arm/mach-exynos4/include/mach/map.h
@@ -62,7 +62,6 @@
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
-#define EXYNOS4_GIC_BANK_OFFSET		0x8000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
diff --git a/trunk/arch/arm/mach-exynos4/platsmp.c b/trunk/arch/arm/mach-exynos4/platsmp.c
index a3346e36d0ae..d5f0f299ba0d 100644
--- a/trunk/arch/arm/mach-exynos4/platsmp.c
+++ b/trunk/arch/arm/mach-exynos4/platsmp.c
@@ -32,6 +32,7 @@
 
 #include <plat/cpu.h>
 
+extern unsigned int gic_bank_offset;
 extern void exynos4_secondary_startup(void);
 
 #define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -67,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos4_gic_secondary_init(void)
 {
 	void __iomem *dist_base = S5P_VA_GIC_DIST +
-				 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+				(gic_bank_offset * smp_processor_id());
 	void __iomem *cpu_base = S5P_VA_GIC_CPU +
-				(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+				(gic_bank_offset * smp_processor_id());
 	int i;
 
 	/*