From b4d784f04227a32fcd6fd6de3a8bc6cf9fbf313e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 10 Apr 2009 21:20:19 +0000 Subject: [PATCH] --- yaml --- r: 148545 b: refs/heads/master c: 78f28a0a83a86dfe021f7d8169208b9af2a23201 h: refs/heads/master i: 148543: 7f3de34954bbce0263afcdd063e622e6f7ecddcf v: v3 --- [refs] | 2 +- trunk/arch/blackfin/mach-common/cache.S | 30 ++++++++++++------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/[refs] b/[refs] index 8111e73298ed..ba8c526ff868 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f8b556514c4481a500ace4745731f04a77c08d54 +refs/heads/master: 78f28a0a83a86dfe021f7d8169208b9af2a23201 diff --git a/trunk/arch/blackfin/mach-common/cache.S b/trunk/arch/blackfin/mach-common/cache.S index c295e8f837c0..d9666fe6c3d6 100644 --- a/trunk/arch/blackfin/mach-common/cache.S +++ b/trunk/arch/blackfin/mach-common/cache.S @@ -15,6 +15,13 @@ .text +/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ +#if ANOMALY_05000443 +# define BROK_FLUSH_INST "IFLUSH" +#else +# define BROK_FLUSH_INST "no anomaly! yeah!" +#endif + /* Since all L1 caches work the same way, we use the same method for flushing * them. Only the actual flush instruction differs. We write this in asm as * GCC can be hard to coax into writing nice hardware loops. @@ -23,7 +30,7 @@ * R0 = start address * R1 = end address */ -.macro do_flush flushins:req optflushins optnopins label +.macro do_flush flushins:req label R2 = -L1_CACHE_BYTES; @@ -44,22 +51,15 @@ \label : .endif P0 = R0; + LSETUP (1f, 2f) LC1 = P1; 1: -.ifnb \optflushins - \optflushins [P0]; -.endif -#if ANOMALY_05000443 -.ifb \optnopins -2: -.endif +.ifeqs "\flushins", BROK_FLUSH_INST \flushins [P0++]; -.ifnb \optnopins -2: \optnopins; -.endif -#else +2: nop; +.else 2: \flushins [P0++]; -#endif +.endif RTS; .endm @@ -77,7 +77,7 @@ ENTRY(_blackfin_icache_flush_range) */ P0 = R0; IFLUSH[P0]; - do_flush IFLUSH, , nop + do_flush IFLUSH ENDPROC(_blackfin_icache_flush_range) /* Throw away all D-cached data in specified region without any obligation to @@ -91,7 +91,7 @@ ENDPROC(_blackfin_dcache_invalidate_range) /* Flush all data cache lines assocoiated with this memory area */ ENTRY(_blackfin_dcache_flush_range) - do_flush FLUSH, , , .Ldfr + do_flush FLUSH, .Ldfr ENDPROC(_blackfin_dcache_flush_range) /* Our headers convert the page structure to an address, so just need to flush