From b549e5941ddd35b946b74b60efb82f0fa18f4727 Mon Sep 17 00:00:00 2001 From: Lior Levy Date: Sat, 4 Jun 2011 06:05:03 +0000 Subject: [PATCH] --- yaml --- r: 314527 b: refs/heads/master c: f00b0da776fda1abc481578e3932a668f603d72d h: refs/heads/master i: 314525: c243633a08ad5181b7377999e72d177bbd6308af 314523: e1ff58e55e5ab529673f33100d7a206b29564faf 314519: 7f9b2d95269a006300bf7c2ed94f7c1d863b087d 314511: 8e3a9a503ada9edb75a7d7d1d3a3ced88c83f5fa 314495: f33d7aeecf75aae74f3c6e090d0d4b9bfabf4bac v: v3 --- [refs] | 2 +- trunk/drivers/net/ethernet/intel/igb/e1000_regs.h | 1 + trunk/drivers/net/ethernet/intel/igb/igb_main.c | 5 +++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 58c7110ef26a..a96c1887cf62 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7500673be30f9467cd1a0e065c93e75c5213b44d +refs/heads/master: f00b0da776fda1abc481578e3932a668f603d72d diff --git a/trunk/drivers/net/ethernet/intel/igb/e1000_regs.h b/trunk/drivers/net/ethernet/intel/igb/e1000_regs.h index 35d1e4f2c92c..10efcd88dca0 100644 --- a/trunk/drivers/net/ethernet/intel/igb/e1000_regs.h +++ b/trunk/drivers/net/ethernet/intel/igb/e1000_regs.h @@ -117,6 +117,7 @@ /* TX Rate Limit Registers */ #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */ +#define E1000_RTTBCNRM 0x3690 /* Tx BCN Rate-scheduler MMW */ #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */ /* Split and Replication RX Control - RW */ diff --git a/trunk/drivers/net/ethernet/intel/igb/igb_main.c b/trunk/drivers/net/ethernet/intel/igb/igb_main.c index dd3bfe8cd36c..64090549722d 100644 --- a/trunk/drivers/net/ethernet/intel/igb/igb_main.c +++ b/trunk/drivers/net/ethernet/intel/igb/igb_main.c @@ -6997,6 +6997,11 @@ static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, } wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ + /* + * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM + * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. + */ + wr32(E1000_RTTBCNRM, 0x14); wr32(E1000_RTTBCNRC, bcnrc_val); }