From b58280d91c0b58cb3f633ea2f6761b0dd031ea8a Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Sun, 24 Jun 2012 19:24:49 +0300 Subject: [PATCH] --- yaml --- r: 315855 b: refs/heads/master c: c1af87dc96cd0f8f17694d0cd9be01b80b2c7a6a h: refs/heads/master i: 315853: c5ffd87bb3427dbfb88c6a1df149056aec778a98 315851: 2bb439769ec1106f75d4523da951a78b265b8b77 315847: 6375a8f210d54ba44c789b690f67ea6c0589dab1 315839: c948ee773ac1ec0f4295d65aa5e22aa18b89b5bf v: v3 --- [refs] | 2 +- trunk/Documentation/virtual/kvm/msr.txt | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 7453810f4326..64bf0abb22ba 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d0a69d6321ca759bb8d47803d06ba8571ab42d07 +refs/heads/master: c1af87dc96cd0f8f17694d0cd9be01b80b2c7a6a diff --git a/trunk/Documentation/virtual/kvm/msr.txt b/trunk/Documentation/virtual/kvm/msr.txt index 96b41bd97523..730471048583 100644 --- a/trunk/Documentation/virtual/kvm/msr.txt +++ b/trunk/Documentation/virtual/kvm/msr.txt @@ -223,3 +223,36 @@ MSR_KVM_STEAL_TIME: 0x4b564d03 steal: the amount of time in which this vCPU did not run, in nanoseconds. Time during which the vcpu is idle, will not be reported as steal time. + +MSR_KVM_EOI_EN: 0x4b564d04 + data: Bit 0 is 1 when PV end of interrupt is enabled on the vcpu; 0 + when disabled. Bit 1 is reserved and must be zero. When PV end of + interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned + physical address of a 4 byte memory area which must be in guest RAM and + must be zeroed. + + The first, least significant bit of 4 byte memory location will be + written to by the hypervisor, typically at the time of interrupt + injection. Value of 1 means that guest can skip writing EOI to the apic + (using MSR or MMIO write); instead, it is sufficient to signal + EOI by clearing the bit in guest memory - this location will + later be polled by the hypervisor. + Value of 0 means that the EOI write is required. + + It is always safe for the guest to ignore the optimization and perform + the APIC EOI write anyway. + + Hypervisor is guaranteed to only modify this least + significant bit while in the current VCPU context, this means that + guest does not need to use either lock prefix or memory ordering + primitives to synchronise with the hypervisor. + + However, hypervisor can set and clear this memory bit at any time: + therefore to make sure hypervisor does not interrupt the + guest and clear the least significant bit in the memory area + in the window between guest testing it to detect + whether it can skip EOI apic write and between guest + clearing it to signal EOI to the hypervisor, + guest must both read the least significant bit in the memory area and + clear it using a single CPU instruction, such as test and clear, or + compare and exchange.