diff --git a/[refs] b/[refs] index 4da985cd1e6d..227e2e4a5c3d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 76c2f6e513b3df8031dda383838da2a3820adbe3 +refs/heads/master: 8bc4f556bd740789cf6fab36d1776d6d4d8bd375 diff --git a/trunk/arch/arm/mach-tegra/dma.c b/trunk/arch/arm/mach-tegra/dma.c index 998c55ddca42..abea4f6e2dd5 100644 --- a/trunk/arch/arm/mach-tegra/dma.c +++ b/trunk/arch/arm/mach-tegra/dma.c @@ -52,8 +52,6 @@ #define CSR_ONCE (1<<27) #define CSR_FLOW (1<<21) #define CSR_REQ_SEL_SHIFT 16 -#define CSR_REQ_SEL_MASK (0x1F<lock, irq_flags); while (!list_empty(&ch->list)) list_del(ch->list.next); - csr = readl(ch->addr + APB_DMA_CHAN_CSR); - csr &= ~CSR_REQ_SEL_MASK; - csr |= CSR_REQ_SEL_INVALID; - writel(csr, ch->addr + APB_DMA_CHAN_CSR); - tegra_dma_stop(ch); spin_unlock_irqrestore(&ch->lock, irq_flags);